CN111131809A - Detection system and detection method of CIS chip - Google Patents
Detection system and detection method of CIS chip Download PDFInfo
- Publication number
- CN111131809A CN111131809A CN201911294063.1A CN201911294063A CN111131809A CN 111131809 A CN111131809 A CN 111131809A CN 201911294063 A CN201911294063 A CN 201911294063A CN 111131809 A CN111131809 A CN 111131809A
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- China
- Prior art keywords
- cis chip
- image data
- probe station
- clock
- fpga
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/002—Diagnosis, testing or measuring for television systems or their details for television cameras
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
Abstract
The invention discloses a detection system of a CIS chip, which comprises the CIS chip, an FPGA and a probe platform, wherein the FPGA is simultaneously connected with the CIS chip and the probe platform; image data generated by the CIS chip is transmitted to the FPGA for caching based on a CIS chip clock; and transmitting the image data after buffering to a probe station based on a probe station clock for testing the image data. According to the detection system and the detection method of the CIS chip, provided by the invention, the image data generated by the CIS chip can be accurately transmitted to the probe station for detection through the cache effect of the FPGA, so that the performance of the CIS chip can be accurately judged.
Description
Technical Field
The invention relates to the field of signal processing, in particular to a detection system of a CIS chip and a detection method thereof.
Background
Before the CIS chip is packaged, the CIS chip is generally required to be tested, and if the CIS chip passes the test, the subsequent packaging work is continued; if the test fails, the CIS chip is indicated to have problems, and further testing or maintenance is required.
In the prior art, an unpackaged CIS chip is usually probed by using an ATE probe station, and as shown in fig. 1, the ATE probe station is directly connected to pins of the CIS chip to perform image data acquisition. Since the ATE prober and the CIS chip have respective clocks, the ATE prober clock refers to a clock for receiving image data by the ATE, and the CIS chip clock refers to a clock for generating image data or transmitting image data by the CIS chip, where the clocks include a phase and a frequency, it is difficult in the prior art to set the CIS chip clock and the ATE prober clock to be identical, and it is difficult to ensure that the phases are identical even if the frequencies of the two clocks are identical. When the clock of the ATE probe station is inconsistent with the clock of the CIS chip, the ATE probe station generally acquires image data generated by the CIS chip with reference to the clock Clk' of the ATE probe station; due to the mismatching of the clocks, data acquired by the ATE probe station is wrong, and image data generated by the CIS chip cannot be accurately acquired by the ATE probe station, so that the performance of the CIS chip cannot be accurately judged, and misleading is caused to subsequent processes.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a detection system and a detection method of a CIS chip, and the image data generated by the CIS chip can be accurately transmitted to a probe station for detection through the cache function of an FPGA, so that the performance of the CIS chip can be accurately judged.
In order to achieve the purpose, the invention adopts the following technical scheme: a detection system of a CIS chip comprises the CIS chip, an FPGA and a probe station, wherein the FPGA is simultaneously connected with the CIS chip and the probe station; image data generated by the CIS chip is transmitted to the FPGA for caching based on a CIS chip clock; and transmitting the image data after buffering to a probe station based on a probe station clock for testing the image data.
Further, the probe station is an ATE probe station.
Further, the FPGA comprises a FIFO, and image data generated by the CIS chip are transmitted to the FIFO for buffering.
Further, the FIFO transmits image data to the probe station line by line through a ping-pong operation.
A method for detecting by using a detection system of a CIS chip comprises the following steps:
s01: image data generated by the CIS chip is transmitted to the FPGA for caching on the basis of a CIS chip clock;
s02: and transmitting the image data after buffering to a probe station for testing the image data on the basis of a probe station clock.
Further, in step S01, based on the CIS chip clock, the CIS chip sequentially sends a frame signal, a line signal, and image data corresponding to the line signal to the FPGA.
Further, in step S02, when the FPGA receives a next frame signal and a next line signal, based on the probe station clock, the FPGA sequentially sends a corresponding frame signal, a line signal, and image data corresponding to the line signal to the probe station.
Further, the FPGA comprises a FIFO, and image data generated by the CIS chip are transmitted to the FIFO for buffering.
Further, the FIFO transmits image data to the probe station line by line through a ping-pong operation.
Further, the probe station performs different CIS chip tests under a fixed probe station clock.
The invention has the beneficial effects that: when the CIS chip is detected, the FPGA is introduced to serve as the cache processor, so that the CIS chip generates and transmits image data based on a CIS chip clock, the probe station acquires the image data from the FPGA based on the probe station clock, and even if the probe station clock is not matched with the CIS chip clock, the probe station can completely and accurately receive the image data generated by the CIS chip, and the CIS chip can be accurately detected. The invention can enlarge the application range of the clock based on the probe station, and can also lead the probe station to test different chips under the fixed clock without changing the frequency of the clock of the probe station according to the clock of the CIS chip.
Drawings
FIG. 1 is a schematic diagram illustrating a CIS chip and an ATE probe station in the prior art;
FIG. 2 is a schematic view of a detection system of a CIS chip according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 2, the CIS chip detection system provided by the present invention includes a CIS chip, an FPGA and a probe station, wherein the FPGA is connected to the CIS chip and the probe station at the same time; image data generated by the CIS chip is transmitted to the FPGA for caching on the basis of a CIS chip clock; and transmitting the image data after buffering to a probe station for testing the image data on the basis of a probe station clock. In the invention, the CIS chip clock refers to a clock for generating image data or transmitting the image data by the CIS chip, and the ATE probe station clock refers to a clock for receiving the image data by the ATE. The clock specifically includes a frequency and a phase. The detection system is suitable for the CIS chip clock and the probe station clock which are asynchronous or synchronous.
As shown in fig. 2, the prober of the present invention may be specifically an ATE prober, or may be other probers in practical applications.
Preferably, the FPGA of the present invention includes a FIFO (First Input First Output), the image data generated by the CIS chip is transmitted to the FIFO for buffering, and the FIFO is used as a buffer to ensure that the image data transmitted to the FPGA can be transmitted to the probe station again according to the sequence of transmission time.
Preferably, the FIFO transmits the image data to the probe station line by line through a ping-pong operation. Ping-pong operation is a processing technique for data flow control that can be used in pipelined data transfer processing to accomplish seamless buffering and processing of image data.
With reference to fig. 2, preferably, when the CIS chip transmits image data line by line, the CIS chip of the present invention needs to first transmit the frame signal hsync and the row signal vsync corresponding to the row signal, and then transmit the image data corresponding to the row, so as to ensure that the row image data received by the FPGA is valid data; in the same way, when the FPGA transmits the line image data to the probe station, the frame signal hsync and the line signal vsync need to be sent first, and then the image data corresponding to the line needs to be transmitted, so as to ensure that the line image data received by the probe station is valid data. In the invention, when judging whether a line of image data is received completely, the FPGA takes a received frame signal hsync and a received line signal vsync as a boundary; when the next frame signal hsync and the line signal vsync are received, the image data of the previous line is completely received, and the image data can be transmitted to the probe station as a whole based on the probe station clock.
Due to the existence of the FPGA, the problem that a clock of a CIS chip is not matched with a clock of a probe station in the prior art can be effectively solved, and when image data generated by the CIS chip is transmitted to the FPGA, the image data only needs to be transmitted according to the clock of the CIS chip; when the image data cached by the FPGA is transmitted to the probe station, the image data is transmitted according to the probe station clock, so that the detection system can ensure the integrity and accuracy of the image data received by the probe station regardless of whether the probe station clock is the same as the CIS chip clock, and the performance of the CIS chip can be accurately judged. The invention can enlarge the application range of the clock based on the probe station, and can also lead the probe station to test different chips under the fixed clock without changing the frequency of the clock of the probe station according to the clock of the CIS chip.
With reference to fig. 2, the method for detecting by using a detection system of a CIS chip according to the present invention includes the following steps:
s01: image data generated by the CIS chip is transmitted to the FPGA for caching on the basis of a CIS chip clock. Preferably, the present invention performs transmission of image data in units of line image data of a CIS chip image. Based on the CIS chip clock Clk, the CIS chip transmits the frame signal hsync, the line signal vsync, and the image data of the mth line of image data into the FPGA, and the transmitted image data is buffered in the FIFO. The CIS chip image comprises N lines of image data, wherein N is a positive integer larger than 0, and M is a positive integer larger than 0 and smaller than or equal to N.
S02: and transmitting the image data after buffering to a probe station for testing the image data on the basis of a probe station clock. Specifically, when the FPGA receives the next frame signal hsync and the next row signal vsync, it indicates that the image data in the mth row is completely transmitted, and at this time, based on the clock Clk' of the probe station, the FPGA sends the frame signal hsync, the row signal vsync, and the image data of the image data in the mth row to the probe station.
S03 repeats steps S01-S02, and transfers the line 1 to line N image data in sequence until all the line data of the frame image are transferred.
When the CIS chip is detected, the FPGA is introduced to serve as the cache processor, so that the CIS chip generates and transmits image data based on a CIS chip clock, the probe station acquires the image data from the FPGA based on the probe station clock, and the CIS chip can be accurately detected even if the probe station clock is not matched with the CIS chip clock. The invention can enlarge the application range of the clock based on the probe station, and can also lead the probe station to test different chips under the fixed clock without changing the frequency of the clock of the probe station according to the clock of the CIS chip.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the appended claims.
Claims (10)
1. The detection system of the CIS chip is characterized by comprising the CIS chip, an FPGA and a probe station, wherein the FPGA is simultaneously connected with the CIS chip and the probe station; image data generated by the CIS chip is transmitted to the FPGA for caching based on a CIS chip clock; and transmitting the image data after buffering to a probe station based on a probe station clock for testing the image data.
2. The CIS chip probing system of claim 1, wherein the probe station is an ATE probe station.
3. The detection system of the CIS chip is characterized in that the FPGA comprises a FIFO, and image data generated by the CIS chip is transmitted to the FIFO for buffering.
4. The CIS chip probing system as claimed in claim 3 wherein the FIFO transfers image data to the probe station line by ping-pong operation.
5. A method for detecting by using a detection system of a CIS chip is characterized by comprising the following steps:
s01: image data generated by the CIS chip is transmitted to the FPGA for caching on the basis of a CIS chip clock;
s02: and transmitting the image data after buffering to a probe station for testing the image data on the basis of a probe station clock.
6. The method for detecting by using a detection system of a CIS chip according to claim 5, wherein in step S01, based on the CIS chip clock, the CIS chip sequentially sends a frame signal, a line signal and image data corresponding to the line signal to the FPGA.
7. The method for detecting by using a detection system of a CIS chip according to claim 6, wherein in step S02, when the FPGA receives a next frame signal and a next line signal, based on the probe station clock, the FPGA sequentially sends a corresponding frame signal, a line signal and image data corresponding to the line signal to the probe station.
8. The method for detecting by using the detection system of the CIS chip is characterized in that the FPGA comprises a FIFO, and image data generated by the CIS chip is transmitted to the FIFO for buffering.
9. The method for detecting by using a CIS chip detection system according to claim 8, wherein the FIFO transfers image data to the probe station line by line through a ping-pong operation.
10. The method for detecting by using the detection system of the CIS chip is characterized in that the probe station carries out different CIS chip tests under a fixed probe station clock.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911294063.1A CN111131809A (en) | 2019-12-16 | 2019-12-16 | Detection system and detection method of CIS chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911294063.1A CN111131809A (en) | 2019-12-16 | 2019-12-16 | Detection system and detection method of CIS chip |
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| CN111131809A true CN111131809A (en) | 2020-05-08 |
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| CN201911294063.1A Pending CN111131809A (en) | 2019-12-16 | 2019-12-16 | Detection system and detection method of CIS chip |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| CN104484885A (en) * | 2014-12-25 | 2015-04-01 | 上海华岭集成电路技术股份有限公司 | ATE test method for CIS chip YUV format output |
| JP2015224990A (en) * | 2014-05-28 | 2015-12-14 | セイコーエプソン株式会社 | Electronic component conveying apparatus and electronic component inspection apparatus |
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2019
- 2019-12-16 CN CN201911294063.1A patent/CN111131809A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| JP2015224990A (en) * | 2014-05-28 | 2015-12-14 | セイコーエプソン株式会社 | Electronic component conveying apparatus and electronic component inspection apparatus |
| CN104484885A (en) * | 2014-12-25 | 2015-04-01 | 上海华岭集成电路技术股份有限公司 | ATE test method for CIS chip YUV format output |
Non-Patent Citations (1)
| Title |
|---|
| 潘曦，闫建华，郑建君: "《数字系统与微处理器》", 30 July 2018 * |
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Application publication date: 20200508 |