CN102109572B - Method for testing and method for testing and controlling transmission chip - Google Patents

Method for testing and method for testing and controlling transmission chip Download PDF

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Publication number
CN102109572B
CN102109572B CN200910189437.3A CN200910189437A CN102109572B CN 102109572 B CN102109572 B CN 102109572B CN 200910189437 A CN200910189437 A CN 200910189437A CN 102109572 B CN102109572 B CN 102109572B
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test
chip
measured
described
according
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CN200910189437.3A
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CN102109572A (en
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张爱萍
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中兴通讯股份有限公司
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Abstract

The invention discloses a method for testing a transmission chip. The method comprises the following steps: test data sent to a chip to be tested is produced and constructed by programmable equipment in accordance with a test case; and the programmable equipment submits a test report according to the result that the chip to be tested processes and returns the test data. The invention further discloses a method for testing and controlling a transmission chip. Under the condition that an instrument is not depended on, the test data is constructed by the programmable equipment according to the test case; test result is returned to the programmable equipment, and the correctness of the result is judged by the programmable equipment, so that universal test on the chip is realized; by the adoption of the invention, the all-sided automatization of the test execution is realized through the control on test process, thereby improving the test efficiency and lowering the test cost.

Description

A kind of method of testing and test control method transmitting chip

Technical field

The present invention relates to measuring technology, particularly relate to a kind of method of testing and the test control method that transmit chip.

Background technology

Checking and test have played vital role in chip development, and have become requisite link in development process.Current, the design of chip, the difficulties and problems of the aspect such as test and manufacture are progressively increasing, and some also becomes and is becoming increasingly acute.Along with improving constantly of current chip performance and complexity, the defect never occurred before various proposes new challenge to conventional test methodologies, and manufacturer needs to formulate new Test Strategy; Simultaneously due to the lasting reduction of integrated circuit (IC)-components average price, rate of profit is also in continuous decline, and manufacturers must take into full account testing cost and economy.

In prior art, test signal is produced by concrete equipment, instrument, the checking of result also often depends on instrument, or be only be converted to signal required for test chip by programming device, this proving installation versatility is lower, and the corresponding a kind of instrument of a kind of proving installation, only can test a kind of chip, so just cause testing cost to strengthen, the dirigibility of test is poor.

Summary of the invention

The main technical problem to be solved in the present invention is, provides a kind of method of testing of general transmission chip;

The technical matters that the present invention also will solve is, provides a kind of test control method of robotization.

For solving the problems of the technologies described above, the invention provides a kind of method of testing transmitting chip, comprising: produced by programmable device and construct according to test case the test data sending to chip to be measured; Described programmable device according to chip to be measured to described test data process and the result returned provides test report.

Wherein said test case comprises the output desired value of the configuration item of programmable device, the active configuration parameter of chip to be measured, the test function item of chip to be measured, the test function item correspondence of described chip to be measured.

Wherein said programmable device comprises FPGA, and described method also comprises FPGA and receives test data and transform described test data according to test case.

Wherein said programmable device also comprises processor, and described generation by programmable device sends to the test data of chip to be measured to comprise according to test case structure: described processor configures described FPGA according to the configuration item of the programmable device in test case; FPGA after configuration constructs described test data according to the active configuration parameter of the chip to be measured in described test case, test function item.

Wherein said programmable device according to chip to be measured to described test data process and the result returned provides test report comprises: the output desired value of the chip to be measured in the result returned and described test case compares by described FPGA.

Also comprise the process that test chip clock to be measured draws bias energy.

Wherein said test chip clock to be measured draws the process of bias energy to comprise: draw inclined clock signal to chip input to be measured, whether normally chip service operation to be measured is tested by described programmable device, if normal, then continue the frequency deviation strengthening clock signal, until chip service operation to be measured is abnormal.

Also comprise accurately the test voltage power supply scope of chip to be measured and the process of power consumption.

The voltage power supply scope of wherein said accurate test chip to be measured and the process of power consumption comprise: provide required voltage to chip to be measured, the electric current that the test that described programmable device is corresponding according to described voltage is arrived, obtain the power consumption of described chip to be measured.

Also comprise the process of test chip to be measured and processor interface ability.

Wherein said test chip to be measured comprises with the process of processor interface ability: the control interface of described processor is docked with chip to be measured by described FPGA, described FPGA is according to the interface sequence of chip to be tested, the interface sequence of processor is constructed/transformed, the register of described processor to chip to be measured completes to be read and write repeatedly, verifies that whether the sequential of chip to be measured and described processor interface is normal.

For solving the problems of the technologies described above, the present invention also provides a kind of test control method transmitting chip further, and it adopts above-mentioned transmission chip detecting method automatically to complete test according to test case, comprising:

Read test use-case, described test case comprises the configuration item of programmable device, the active configuration parameter of chip to be tested, test function item;

Described programmable device is configured according to the configuration item of the programmable device in test case;

Issue the active configuration parameter of chip to be tested, test function item;

Active configuration parameter according to obtaining test chip is configured chip to be measured;

Test is started according to test function item;

Generating test use case test report.

Describedly start test according to test function item and comprise: control described programmable device structure test data stream; The state of chip monitoring is carried out by chip alarm interruption, error monitoring; Monitoring state described in statistical treatment.

The invention has the beneficial effects as follows:

(1) the present invention can under the condition not relying on instrument, and construct test data by programmable device according to test case, test result passes back to programmable device, by the correctness of its judged result, thus realizes the universal test to chip.

(2) the present invention adopts FPGA, can further improve the dirigibility of test.

(3) the present invention is by the test to the skew of chip voltage working range, power consumption, clock, achieves the test to chip performance, thus improves the comprehensive of test.

(4) control of the present invention to test process makes test execution be able to comprehensive automation, improves testing efficiency, reduces testing cost.

(5) the present invention is easy to implement, and expansion is convenient.

Accompanying drawing explanation

Fig. 1 is the proving installation structural representation according to a proving installation of the present invention embodiment;

Fig. 2 is the proving installation structural representation according to another embodiment of proving installation of the present invention;

Fig. 3 is the proving installation structural representation according to another embodiment of proving installation of the present invention;

Fig. 4 is the proving installation structural representation according to another embodiment of proving installation of the present invention;

Fig. 5 is the process flow diagram of the performance test according to a method of testing of the present invention embodiment;

Fig. 6 is the proving installation structural representation according to proving installation of the present invention another embodiment again;

Fig. 7 is the process flow diagram of the functional test according to another embodiment of method of testing of the present invention;

Fig. 8 is the process flow diagram of an embodiment according to test control method of the present invention;

Fig. 9 is the structural representation of an embodiment according to test control device of the present invention;

Figure 10 is the process flow diagram of another embodiment according to test control method of the present invention.

Embodiment

By reference to the accompanying drawings the present invention is described in further detail below by embodiment.

Transmit a proving installation for chip, comprising: programmable device, send to the test data of chip to be measured for generation of according to test case structure, according to chip to be measured to described test data process and the result returned provides test report.

Wherein said test case comprises the configuration item of programmable device, the active configuration parameter of chip to be tested, test function item, output desired value that described chip testing function items to be tested is corresponding.

Wherein said programmable device comprises FPGA, and described FPGA is for receiving test data and transforming described test data according to test case.

Wherein said programmable device also comprises processor, for configuring described FPGA according to the configuration item of the programmable device in described test case; Described FPGA is also for receiving the configuration of described processor and constructing described test data according to the active configuration parameter of the chip to be measured in described test case, test function item.

Also comprise be connected with chip to be measured draw inclined clock signal unit, inclined clock signal is drawn for giving chip to be measured input, whether described device is also normal for being tested chip service operation to be measured by described programmable device, if normal, then continue the frequency deviation strengthening clock signal, until chip service operation to be measured is abnormal.

Also comprise the pressure-adjustable power module be connected with described chip to be measured, for providing required voltage to chip to be measured, described programmable device, also for the electric current that the test corresponding according to described voltage is arrived, obtains the power consumption of described chip to be measured.

The control interface of described processor is docked with chip to be measured by described FPGA, described FPGA is also for the interface sequence according to chip to be tested, the interface sequence of processor is constructed/transformed, described processor is is also read and write repeatedly for completing the register of chip to be measured, verifies that whether the sequential of chip to be measured and described processor interface is normal.

Transmit a test control device for chip, automatically complete test for adopting above-mentioned transmission apparatus for testing chip according to test case; For:

Read test use-case, described test case comprises the configuration item of programmable device, the active configuration parameter of chip to be tested, test function item, output desired value that described chip testing function items to be tested is corresponding;

Described programmable device is configured according to the configuration item of the programmable device in test case;

Issue the active configuration parameter of chip to be tested, test function item;

Active configuration parameter according to obtaining test chip is configured chip to be measured;

Test is started according to test function item;

Generating test use case test report.

The present invention will improve traditional validation test flow process as breach, by designing a kind of method of comprehensive test transmission chip, formulate complete, a detailed testing scheme, design effective test case, become the universal test environment platform of transmission class chip, ensure to transmit the automatic Verification of class chip under various applied environment and test by the versatility of test environment platform.

A kind of embodiment of the method for testing of chip is transmitted in the present invention, comprising: produced by programmable device and construct according to test case the test data sending to chip to be measured; Programmable device according to chip to be measured to test data process and the result returned provides test report.

According to an embodiment of method of testing of the present invention, this test case comprises the output desired value of test function item correspondence of the configuration item of programmable device, the active configuration parameter of chip to be measured, the test function item of chip to be measured, chip to be measured.

According to an embodiment of method of testing of the present invention, this programmable device comprises FPGA, and FPGA, for receiving test data and transforming test data according to test case, changes into the data needed for test.According to an alternative of the present invention, programmable device can comprise other programming device.

According to an embodiment of method of testing of the present invention, this programmable device also comprises processor, its configuration item according to the programmable device in test case configuration FPGA; FPGA after configuration is according to active configuration parameter, the test function item structure test data of the chip to be measured in test case.

According to an embodiment of method of testing of the present invention, the output desired value of the chip to be measured in the result returned and described test case compares by FPGA.

According to an embodiment of method of testing of the present invention, it also comprises the process that test chip clock to be measured draws bias energy, this process comprises: draw inclined clock signal to chip input to be measured, whether normally chip service operation to be measured is tested by programmable device, if normal, then continue the frequency deviation strengthening clock signal, until chip service operation to be measured is abnormal.

According to an embodiment of method of testing of the present invention, also comprise accurately the test voltage power supply scope of chip to be measured and the process of power consumption, this process comprises: provide required voltage to chip to be measured, the electric current that the test that programmable device is corresponding according to voltage is arrived, and obtains the power consumption of chip to be measured.In the present embodiment, the multiple adjustable voltage that can be exported to chip to be measured by adjustable voltage source module, as 1V, 1.2V, 1.8V, 2.5V and 3.3V, or other any required magnitude of voltage.

According to an embodiment of method of testing of the present invention, also comprise the process of test chip to be measured and processor interface ability, this process comprises: the control interface of processor is docked with chip to be measured by FPGA, FPGA is according to the interface sequence of chip to be tested, the sequential of processor is constructed/transformed, the register of processor to chip to be measured completes to be read and write repeatedly, verifies that whether the sequential of chip to be measured and described processor interface is normal.

A kind of embodiment of the proving installation of chip is transmitted in the present invention, as shown in Figure 1, comprise programmable device 101, send to the test data of chip to be measured for generation of according to test case structure, according to chip to be measured to described test data process and the result returned provides test report.

According to an embodiment of proving installation of the present invention, test case comprises the configuration item of programmable device, the active configuration parameter of chip to be tested, test function item, output desired value that chip testing function items to be tested is corresponding.

According to an embodiment of proving installation of the present invention, as shown in Figure 2, programmable device 201 comprises FPGA202 and storer 203; Wherein, FPGA202 is for receiving test case and constructing described test data; Storer 203 is for storing Large Volume Data.According to an alternative of the present invention, programmable device can comprise other programming device.

According to an embodiment of proving installation of the present invention, programmable device also comprises processor 204, for the configuration item configuration FPGA202 according to the programmable device in test case; FPGA202 also for receiving processor 204 configuration and according to the active configuration parameter of the chip to be measured 207 in test case, test function item structure test data.

According to an embodiment of proving installation of the present invention, also comprise be connected with chip 207 to be measured draw inclined clock signal unit 205, inclined clock signal is drawn for giving chip to be measured input, whether this device 200 also runs normal for being tested chip 207 to be measured by programmable device 201, if normal, then continue the frequency deviation strengthening clock signal, until chip to be measured 207 runs abnormal.

According to an embodiment of proving installation of the present invention, also comprise the pressure-adjustable power module 206 be connected with chip 207 to be measured, there is provided required voltage for independent to chip to be measured, programmable device 201 also for the electric current that the test corresponding according to this voltage is arrived, obtains the power consumption of chip to be measured.In the present embodiment, the multiple adjustable voltage that can be exported to chip to be measured by variable voltage source 206, as 1V, 1.2V, 1.8V, 2.5V and 3.3V, or other any required magnitude of voltage.

According to an embodiment of proving installation of the present invention, the control interface of processor 204 is docked with chip 207 to be measured by FPGA202, FPGA202 is also for the interface sequence according to chip 207 to be tested, the sequential of processor is constructed/transformed, processor 204 is is also read and write repeatedly for completing the register of chip 207 to be measured, verifies that whether chip 207 to be measured is normal with the sequential of processor interface.

Fig. 3 illustrates the module diagram of proving installation 300 according to an embodiment of the invention, comprising: draw inclined clock module 302 needed for chip 311 to be measured, this module can realize the high low bias test to chip clock; Regulated power supply module 301 needed for chip 311 to be measured, it can realize the test to chip power voltage working range, power consumption; Clock/reset module 304 needed for other chip of whole device; Power supply 303 needed for other chip of whole device; 307 is the data signal source possible used; The PC305 managing 307 and drive; FPGA (field programmable logic array (FPLA)) 309; The storage unit 310 of hanging under FPGA309; CPU minimum system 306, processor wherein can be can with the multiple of the same type or dissimilar processor of chip interface adaptation to be tested.FPGA309 is connected with chip 300 relevant interface to be measured, tests each interface sequence of chip to be measured, completes test the function of chip 311 to be measured additionally by FPGA309.

According to one embodiment of present invention, proving installation 300 can be utilized to carry out comprehensive test, comprising performance test to transmission chip.Performance test in the present embodiment comprises accurately test and treats voltage power supply scope, the power consumption of side chip; The clock skew scope of flexible test chip to be measured; The interface sequence of accurate test chip.

Fig. 4 illustrates the module diagram of proving installation 400 pairs of performance tests according to an embodiment of the invention.Pressure controlled constant tempeature crystal oscillator can be selected in precision interval clock source, nominal frequency 77.76MHZ, original frequency deviation ± 0.1ppm; SI5326 selected by clock multiplier/Jitter Attenuation device 404, can realize 2k-945M optional frequency and export; Realize controlling by 411,411 is processor MPC8321E; In the present embodiment, clock needs to draw between 76.76M to 78.76M partially, and granularity is 100Hz.In the present embodiment, 1V (406), 1.2V (407), 1.8V (408), 2.5V (409) DC-DC power module select AXH016A0X3-SRZ//BSM16A-3SXG, input voltage 3.0 ~ 5.5V, output voltage 0.75 ~ 3.3V, output current 16A, 3.3V (410) DC-DC power module selects PMM4218TWP//PTH04040WAD, input voltage 2.95 ~ 5.5VDC, output voltage 0.8 ~ 2.5VDC, output current 60A, power inductance (413-417) selects DHC-5121-R33R-LF1, rated current 16A.By regulating the divider resistance of DC-DC power module, can realizing drawing of voltage inclined, by measuring electric current at power inductance place, accurately can obtain the power consumption of each voltage of chip.

Fig. 5 illustrates according to the process flow diagram of one embodiment of the invention based on the performance test of proving installation 400, comprising:

Step 502: according to testing requirement, determine appropriate test case, need in test case to provide as follows content: the desired value that the reference result that parameter renewal possible in the active configuration parameter of chip 418 to be measured and test process etc., supporting data stream, chip to be measured 418 export, chip to be measured 418 export was ready to before enforcement test, specified every content in test case;

Step 504: applying performance test condition, starts performance test;

Step 506: according to the feature of current chip design to low-voltage future development, as shown in module 401: 1V, 1.2V, 1.8V, 2.5V, 3.3V covers the whole operating voltage of transmission needed for chip operation at present, in order to voltage power supply scope, the power consumption of accurate test chip, adopts the mode of powering separately to chip to be measured; For the feature that transmission chip power-consumption is at present large, adjustable voltage module type selecting pays special attention to output current index, and on circuit, has done compatible design, both can select adjustable voltage module, can select stabilized voltage supply again, each supply voltage of chip to be measured is set to representative value;

Step 508: in order to test the interface capability of chip to be measured and multiple of the same type or dissimilar processor, on plate, the control interface of processor is docked with chip to be measured by FPGA402, the interface sequence that FPGA402 provides according to chip to be tested, structure/the conversion of sequential is carried out by FPGA internal module 412, the register of processor to chip to be measured completes to be read and write repeatedly, verifies that whether the sequential of chip to be measured and dissimilar processor interface is normal;

Step 510: processor 419 configurating programmable logic array FPGA402, FPGA402 gives chip 418 to be measured by test case complete construction data stream, chip 418 to be measured processes according to the data stream of configuration parameter and input, output processing result passes back to FPGA402, FPGA402 produces the reference result of expection according to test case, authentication module compares passback result and desired value, and result of determination is correct, goes to step 506; Otherwise chip cisco unity malfunction, goes to step 518;

Step 512: the electric current testing out each supply voltage at testing power consumption node respectively, thus the power consumption accurately obtaining each supply voltage;

Step 514: high feature is required to clock accuracy for transmission chip, select pressure controlled constant tempeature crystal oscillator 403, drawing of clock is realized by multi tate clock multiplier/Jitter Attenuation device 404 partially, inclined control module 411 is drawn by clock, can realize 2k-945M optional frequency to export, precision is at 100Hz; Signal source of clock is drawn partially, whether normally watches service operation, after running a period of time, if still normal, then continue to strengthen frequency deviation, the boundary value of chip clock frequency deviation can be found by this method;

Step 516: clock setting, to representative value, regulates each power work in minimum value, representative value, maximal value successively.Watch business whether normal operation, whether long-play, watch service operation within the test duration and stablize;

Step 518: terminate.

The present embodiment can the operating voltage range of test chip exactly, each voltage power consumption; Also can the skew of accurately test clock, to confirm the requirement of chip to clock offset.

Fig. 6 illustrates the module map of the proving installation 600 according to the embodiment of the present invention, wherein FPGA601 can select the Virtex-5 series of X C5VTX240T of Xilinx, realize the generation of control signal, the conversion of LocalBus interface sequence, structure/the conversion completely of SDH data source, the automatic Verification of Output rusults; Chip 618 to be measured, this chip monolithic realizes 20G branch road process (pointer leakage and branch road overhead processing) and time division and crossing, 4 stacking realizes 80G capacity, supports that 2.5G bus 1+1 and AU4 rank 2:4 protects, and provides branch road 1+1 APS function; The communication purpose processor MPC8321E of the high integration that a cost performance that processor 615 adopts FREESCALE newly to release is high, in order to realize the automatic acquisition of FPGA601, the configuration of chip to be measured 618 running parameter, test result, generates.Fig. 7 illustrates according to the process flow diagram of the embodiment of the present invention based on the functional test of proving installation 600, comprising:

Step 702: according to testing requirement, determines appropriate test case;

Step 704: apply function test condition, starts functional test;

Step 706: processor 615 configurating programmable logic array FPGA601, by the complete construction data source of FPGA601, produces data stream to chip 618 to be measured by test case;

Step 708: the running parameter that processor 615 is specified according to test case, correct configuration chip 618 to be measured;

Step 710: chip 618 to be tested processes according to the data stream of configuration parameter and input, and output processing result passes back to FPGA601;

Step 712: the result that chip 618 to be tested exports passes back to FPGA601, automatically processed by the authentication module of FPGA601 inside, authentication module compares passback result and desired value, the correctness of result of determination.

FPGA601 can construct test signal completely, and is verified result by FPGA601, and existing proving installation is confined to produce test signal by instrument and verify.

A kind of embodiment of the test control method of chip is transmitted in the present invention, automatically can complete testing process, as shown in Figure 8, comprising:

Step 802: read test use-case, described test case comprises the configuration item of programmable device, the active configuration parameter of chip to be tested, test function item;

Step 804: configure described programmable device according to the configuration item of the programmable device in test case;

Step 806: issue the active configuration parameter of chip to be tested, test function item;

Step 808: the active configuration parameter according to obtaining test chip is configured chip to be measured;

Step 810: start test according to test function item;

Step 812: generating test use case test report.

According to an embodiment of control method of the present invention, 810 comprise further: control described programmable device structure test data stream; The state of chip monitoring is carried out by chip alarm interruption, error monitoring; Monitoring state described in statistical treatment.

A kind of embodiment of the test control device of chip is transmitted in the present invention, for automatically completing test according to test case; Read test use-case, described test case comprises the configuration item of programmable device, the active configuration parameter of chip to be tested, test function item, output desired value that described chip testing function items to be tested is corresponding; Described programmable device is configured according to the configuration item of the programmable device in test case; Issue the active configuration parameter of chip to be tested, test function item;

Active configuration parameter according to obtaining test chip is configured chip to be measured; Test is started according to test function item; Generating test use case test report.

Fig. 9 illustrates the module map of test control device 900 according to an embodiment of the invention, and Figure 10 illustrates that it comprises according to the process flow diagram of one embodiment of the invention based on test control device 900:

Step 1002: test case starts to perform, the configuration item of reading instrument 902 and chip to be measured 914 test function item and configuration parameter from test case configuration file 901, this instrument 902 can be the measurement instrument of prior art also can be aforementioned proving installation;

Step 1004: automation collaborative control section 905 calls instrument drive 903 according to instrument arrangement item and configures instrument setting option;

Step 1006: automation collaborative control section 905 issues 907 to testing single-board according to function items to be measured and configuration parameter by order;

Step 1008; After testing single-board receives order, obtain test function item and parameter by command analysis item 910;

Step 1010: test function configuration section 912 is configured chip 914 to be measured according to the parameter obtained;

Step 1012: automation collaborative control section 905 starts test;

Step 1014: in test process, automation collaborative control section 905 can call instrument drive 903 and construct various test data stream;

Step 1016: in test process, test board is by the state of chip alarm interruption, error monitoring and statistical treatment part 913 chip monitoring;

Step 1018: can by the state reporting of chip to the automated system control section 905 of control desk by alarm and Bit Error Code Statistics information reporting part 911;

Step 1020: after having tested, reports the generating test use case execution result report automatically of automatic generating portion 906 by test result.

Like this can practical function test comprehensive automation: structure source data robotization, the robotization of chip under test configuration, the robotization of chip under test state information acquisition, the robotization of test result obtains, the robotization of test report generates, the automatic switchover of test case.

Above content is in conjunction with concrete embodiment further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.

Claims (12)

1. transmit a method of testing for chip, it is characterized in that, comprising:
Constructed the test data sending to chip to be measured according to test case by programmable device; Wherein said test case comprises the output desired value of the configuration item of programmable device, the active configuration parameter of chip to be measured, the test function item of chip to be measured, the test function item correspondence of described chip to be measured;
Described programmable device according to chip to be measured to described test data process and the result returned provides test report.
2. the method for claim 1, is characterized in that, wherein said programmable device comprises FPGA, and described method also comprises FPGA and receives test data and transform described test data according to test case.
3. method as claimed in claim 2, it is characterized in that, wherein said programmable device also comprises processor, and described generation by programmable device sends to the test data of chip to be measured to comprise according to test case structure:
Described processor configures described FPGA according to the configuration item of the programmable device in test case;
FPGA after configuration constructs described test data according to the active configuration parameter of the chip to be measured in described test case, test function item.
4. method as claimed in claim 3, is characterized in that, wherein said programmable device according to chip to be measured to described test data process and the result returned provides test report comprises:
The output desired value of the chip to be measured in the result returned and described test case compares by described FPGA.
5. the method as described in as arbitrary in Claims 1-4, is characterized in that, also comprise test chip clock to be measured draw bias can process.
6. method as claimed in claim 5, it is characterized in that, wherein said test chip clock to be measured draws the process of bias energy to comprise: draw inclined clock signal to chip input to be measured, whether normally chip service operation to be measured is tested by described programmable device, if normal, then continue the frequency deviation strengthening clock signal, until chip service operation to be measured is abnormal.
7. the method as described in as arbitrary in Claims 1-4, is characterized in that, also comprises accurately the test voltage power supply scope of chip to be measured and the process of power consumption.
8. method as claimed in claim 7, it is characterized in that, the voltage power supply scope of wherein said accurate test chip to be measured and the process of power consumption comprise: provide required voltage to chip to be measured, the electric current that the test that described programmable device is corresponding according to described voltage is arrived, obtains the power consumption of described chip to be measured.
9. the method as described in claim 3 or 4, is characterized in that, also comprises the process of test chip to be measured and processor interface ability.
10. method as claimed in claim 9, it is characterized in that, wherein said test chip to be measured comprises with the process of processor interface ability: the control interface of described processor is docked with chip to be measured by described FPGA, described FPGA is according to the interface sequence of chip to be tested, the interface sequence of processor is constructed/transformed, the register of described processor to chip to be measured completes to be read and write repeatedly, verifies that whether the sequential of chip to be measured and described processor interface is normal.
11. 1 kinds of test control methods transmitting chip, is characterized in that, according to test case adopt as arbitrary in claim 1 to 10 as described in method of testing automatically complete test, comprising:
Read test use-case, described test case comprises the configuration item of programmable device, the active configuration parameter of chip to be tested, test function item;
Described programmable device is configured according to the configuration item of the programmable device in test case;
Issue the active configuration parameter of chip to be tested, test function item;
Active configuration parameter according to obtaining test chip is configured chip to be measured;
Test is started according to test function item;
Generating test use case test report.
12. methods as claimed in claim 11, is characterized in that, described according to test function item start test comprise:
Control described programmable device structure test data stream;
The state of chip monitoring is carried out by chip alarm interruption, error monitoring;
Monitoring state described in statistical treatment.
CN200910189437.3A 2009-12-23 2009-12-23 Method for testing and method for testing and controlling transmission chip CN102109572B (en)

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