CN105093001A - Automatic analysis test system for characteristics of high-speed PLL and clock chip - Google Patents
Automatic analysis test system for characteristics of high-speed PLL and clock chip Download PDFInfo
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- CN105093001A CN105093001A CN201410216027.4A CN201410216027A CN105093001A CN 105093001 A CN105093001 A CN 105093001A CN 201410216027 A CN201410216027 A CN 201410216027A CN 105093001 A CN105093001 A CN 105093001A
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Abstract
The invention provides an automatic analysis test system for characteristics of a high-speed PLL and a clock chip. The automatic analysis test system comprises equipment operating software for executing automatic test analyses, an FPGA hardware system, high-speed clock characteristic analysis equipment working independently, and auxiliary equipment working independently; and data communication between the equipment operating the software for executing the automatic test analyses and the FPGA hardware system is achieved through a serial port/USB2.0, and the equipment operating the software for executing the automatic test analyses achieves control for the high-speed clock characteristic analysis equipment and the auxiliary equipment through a universal interface bus. According to the automatic analysis test system, an automatic analysis test for the characteristics of the PLL/clock chip is achieved by utilizing existing conventional test equipment, so test cost is reduced, and test precision is improved.
Description
Technical field
The present invention relates to chip testing field, in particular to a kind of high-speed pll and clock chip characteristic automatic analysis test macro.
Background technology
Present chip system travelling speed is more and more faster, more and more higher to the performance requirement of the various aspects of clock, so need to carry out comprehensive specificity analysis to phaselocked loop (PLL) isochronon module, wherein most importantly comprise the parameters such as shake, phase noise, stabilization time, also need to arrange at different voltage, clock system simultaneously, carry out test analysis at temperature.So, the workload of test analysis can increase greatly, does a set of test analysis, and the test event that complete has hundreds of bar usually, needs to spend time a couple of days, and special labor intensive resource.For this reason, how to utilize the equipment such as high-speed oscilloscope (sampling rate >20GS/S), signal analyzer, spectrum analyzer, realize the automated analysis of clock characteristic, become important topic urgently to be resolved hurrily.
The main method addressed this problem at present is exactly the high end configuration utilizing high-end ATE board, and as 93K, it can provide the clock analysis of high bandwidth, and can carry out automatic test.But, such high-end devices also comes with some shortcomings part: mainly involve great expense, simultaneously sampling rate, bandwidth, make an uproar the end also not as existing high-end oscillograph (sampling rate >20GS/S), signal analyzer and spectrum analyzer.Although adopt said method can solve the problem of automatic test, the problems such as the precision of test, the cost of test, still do not solve completely.
Therefore, need to propose a kind of high-speed pll and clock chip characteristic automatic analysis test macro, while realizing the automated analysis of clock characteristic, improve the precision of test and reduce the cost tested.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of high-speed pll and clock chip characteristic automatic analysis test macro, comprising: the equipment running the software for performing automatic test analysis; FPGA hardware system; The high-frequency clock specificity analysis testing apparatus worked alone and utility appliance, wherein, described operation realizes data communication for performing between the equipment of the software of automatic test analysis and described FPGA hardware system by serial ports/USB2.0, the control that described operation realizes described high-frequency clock specificity analysis testing apparatus and described utility appliance for the equipment that performs the software of automatic test analysis by general purpose interface bus.
Further, described operation comprises PC for the equipment of the software performing automatic test analysis, described software is write based on labview and is formed, control described FPGA hardware system and control described high-frequency clock specificity analysis testing apparatus by described general purpose interface bus to carry out full-automatic testing to described PLL/ clock chip by described serial ports/USB2.0, test data is arranged to be written in storage file and goes, or carry out semi-automatic test by controlling described high-frequency clock specificity analysis testing apparatus and described utility appliance and described FPGA hardware system, realize testing the debugging of described PLL/ clock chip.
Further, the hardware in described FPGA hardware system comprises: the serial ports/usb interface module connected with the serial ports/USB2.0 in described test macro, FPGA module, signal relay array, Power Management Unit module, power module, signal processing module, 3 state impact dampers, function key, AC parameter test point, the test access connected with described high-frequency clock characteristic testing equipment and described high-speed pll/clock chip and be connected for the golden finger that described FPGA hardware system is expanded.
Further, described high-frequency clock specificity analysis testing apparatus comprises high-speed sampling oscillograph, signal analyzer or spectrum analyzer.
Further, the oscillographic sampling rate >20GS/S of described high-speed sampling.
Further, in described control, the control to the oscillographic jitter analysis software of described high-speed sampling is comprised for the oscillographic control of described high-speed sampling.
Further, described high-speed pll/clock chip is placed on the test run circuit board of described test macro, by realizing data communication between connector and described FPGA hardware system.
Further, described utility appliance comprises power supply, AWG (Arbitrary Waveform Generator) and temperature control system.
Further, programmed by Verilog, described FPGA hardware system carries out logic configuration to described PLL/ clock chip, and tests the DC parameter of described PLL/ clock chip and the connectivity of described PLL/ clock chip and described test macro.
According to the present invention, realize utilizing existing Conventional test equipment to realize testing the automatic analysis of the characteristic of PLL/ clock chip, and then reduce testing cost, improve measuring accuracy.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the schematic block diagram of the clock characteristic automatic analysis test macro that the present invention proposes;
Fig. 2 is for the operation shown in Fig. 1 is for performing the workflow of the software for performing automatic test analysis installed in the equipment of the software of automatic test analysis;
Fig. 3 is the schematic block diagram of the FPGA hardware system shown in Fig. 1.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain high-speed pll and the clock chip characteristic automatic analysis test macro of the present invention's proposition.Obviously, the specific details that the technician that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other embodiments.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
In order to solve the weak point of existing clock chip specificity analysis test macro, the present invention proposes a kind of high-speed pll and clock chip characteristic automatic analysis test macro, while realizing the automated analysis of clock characteristic, improve the precision of test and reduce the cost tested.The present invention utilizes existing relatively independent clock characteristic analysis tool, as desk type high speed sampling oscilloscope, signal analyzer, spectrum analyzer, high and low-temperature apparatus, design corresponding software and hardware, set up a set of automated analysis test macro, complete and the automated analysis of the characteristic of high-speed clock signal is tested.
With reference to shown in Fig. 1, illustrated therein is the schematic block diagram of the clock characteristic automatic analysis test macro (hereinafter referred to as test macro) that the present invention proposes.
The PLL/ clock chip 104 carrying out analytical test is needed to be placed in test run circuit board 101, by realizing data communication between connector 105 and FPGA hardware system 103.Programmed by Verilog, FPGA hardware system 103 can carry out logic configuration to PLL/ clock chip 104, the DC parameter of PLL/ clock chip 104 and the connectivity of PLL/ clock chip 104 and test macro are tested simultaneously, then test result is uploaded to the equipment 100 of the software run for performing automatic test analysis by serial ports/USB2.0102, such as PC.Had FPGA hardware system 103, test macro can adapt to the testing requirement of various PLL and clock chip more flexibly.
Be provided with the software for performing automatic test analysis in equipment 100, this software writes form based on the labview of American National instrument (NI) company exploitation, and based on the visualization interface of windowsXP, simple to operate and reliable and stable.This software can complete the reading required the dependence test of PLL/ clock chip 104, the control to the conventional high-frequency clock specificity analysis testing apparatus worked alone and other utility appliance is realized by general purpose interface bus (GPIB) 111, described conventional analysis testing apparatus comprises high-speed sampling oscillograph 107 (sampling rate >20GS/S), signal analyzer/spectrum analyzer 106 etc., described utility appliance comprises power supply 110, AWG (Arbitrary Waveform Generator) (AWG) 109, temperature control system 108 etc., carry out full-automatic testing by USB2.0/ serial ports RS232 control FPGA hardware system 103 pairs of PLL/ clock chips 104 simultaneously, test data is arranged to be written in storage file and goes, also semi-automatic test can be carried out by control the said equipment and FPGA hardware system 103, realize testing the debugging of PLL/ clock chip 104.Equipment 100 realizes with the general purpose interface bus (GPIB) 111 of the data communication between above-mentioned conventional analysis testing apparatus and other utility appliance by daisy chain, to the control of shake (Jitter) analysis software of high-speed sampling oscillograph 107, be also realized by general purpose interface bus (GPIB) 111.Thus, the control of equipment 100 pairs of high-speed sampling oscillographs 107, does not just complete the control to basic hardware, completes simultaneously and docks with the interface of the jitter analysis software of high-speed sampling oscillograph 107, thus can obtain more accurate statistical test data.
With reference to Fig. 2, illustrated therein is the workflow of the software for performing automatic test analysis installed in equipment 100.
First, perform step 201, hardware in checkout system (sending agreement to hardware by general purpose interface bus 111 and serial ports/USB2.0102), described hardware comprises the hardware in FPGA hardware system 103 and above-mentioned conventional analysis testing apparatus and other utility appliance.
Then, perform step 202, accept by general purpose interface bus 111 and serial ports/USB2.0102 the frame data that described hard wired feed back returns, if the frame data mistake accepted, then re-execute step 201 until the frame data accepted are correct.
Then, perform step 203, load test configurations, to meet the test request of PLL/ clock chip 104.
Then, perform step 204, implement open circuit short-circuit test, to check whether general purpose interface bus 111 and serial ports/USB2.0102 normally work;
Then, performing step 205, implement the configuration that functional pin distributes, completing test to meeting PLL/ clock chip 104 to indicate relevant device;
Then, perform step 206, the related test parameters of power supply 110, AWG (Arbitrary Waveform Generator) 109, temperature control system 108, high-speed sampling oscillograph 107, signal analyzer/spectrum analyzer 106 is arranged;
Then, perform step 207, trigger the jitter analysis implement software test of high-speed sampling oscillograph 107;
Then, perform step 208, read the test data from high-speed sampling oscillograph 107 by general purpose interface bus 111;
Then, perform step 209, test implemented by trigger pip analyser/spectrum analyzer 106;
Then, perform step 210, preserve the test data from signal analyzer/spectrum analyzer 106;
Then, perform step 211, analyze above-mentioned test data, if test result does not meet the demands, then return step 207, repeatedly implement test 3 times, if test result meets the demands, then perform step 212, judge that whether the test event of current enforcement is last of the test event needing to implement, if not, then return step 206, reset test parameter, test is implemented to next test event, if so, then perform step 213, stop test.
With reference to Fig. 3, illustrated therein is the schematic block diagram of FPGA hardware system 103.
Hardware in FPGA hardware system 103 comprises: the serial ports/usb interface module 301 connected with the serial ports/USB2.0102 in test macro, FPGA module 302, signal relay array (SignalRelayArray) 303, Power Management Unit module 304, power module 306, signal processing module 305, 3 state impact dampers 307, function key 308, AC parameter test point 309, the test access 310 connected with the Conventional test equipment in test macro and PLL/ clock chip 104 and be connected 311 for the golden finger of system extension.Input dc power 5V is as the working power of FPGA hardware system 103.
According to the present invention, labview is utilized to develop automatic testing software, it connects high-speed sampling oscillograph 107, signal analyzer/spectrum analyzer 106, temperature control system 108, power-supply device 110 by general purpose interface bus 111, carries out the management of process of test automatically, the work such as data storage; Design FPGA hardware system 103 pairs of PLL/ clock chips 104 carry out basic DC parameter test; This automatic testing software and FPGA hardware system 103 exchange data by serial ports/USB2.0102.Thus, realize utilizing existing Conventional test equipment to realize testing the automatic analysis of the characteristic of PLL/ clock chip 104, and then reduce testing cost, improve measuring accuracy.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. high-speed pll and a clock chip characteristic automatic analysis test macro, comprising:
Run the equipment of the software for performing automatic test analysis;
FPGA hardware system;
The high-frequency clock specificity analysis testing apparatus worked alone and utility appliance, wherein, described operation realizes data communication for performing between the equipment of the software of automatic test analysis and described FPGA hardware system by serial ports/USB2.0, the control that described operation realizes described high-frequency clock specificity analysis testing apparatus and described utility appliance for the equipment that performs the software of automatic test analysis by general purpose interface bus.
2. test macro according to claim 1, it is characterized in that, described operation comprises PC for the equipment of the software performing automatic test analysis, described software is write based on labview and is formed, control described FPGA hardware system and control described high-frequency clock specificity analysis testing apparatus by described general purpose interface bus to carry out full-automatic testing to described PLL/ clock chip by described serial ports/USB2.0, test data is arranged to be written in storage file and goes, or carry out semi-automatic test by controlling described high-frequency clock specificity analysis testing apparatus and described utility appliance and described FPGA hardware system, realize testing the debugging of described PLL/ clock chip.
3. test macro according to claim 1, it is characterized in that, the hardware in described FPGA hardware system comprises: the serial ports/usb interface module connected with the serial ports/USB2.0 in described test macro, FPGA module, signal relay array, Power Management Unit module, power module, signal processing module, 3 state impact dampers, function key, AC parameter test point, the test access connected with described high-frequency clock characteristic testing equipment and described high-speed pll/clock chip and be connected for the golden finger that described FPGA hardware system is expanded.
4. test macro according to claim 1, is characterized in that, described high-frequency clock specificity analysis testing apparatus comprises high-speed sampling oscillograph, signal analyzer or spectrum analyzer.
5. test macro according to claim 4, is characterized in that, the oscillographic sampling rate >20GS/S of described high-speed sampling.
6. test macro according to claim 4, is characterized in that, comprises the control to the oscillographic jitter analysis software of described high-speed sampling in described control for the oscillographic control of described high-speed sampling.
7. test macro according to claim 1, is characterized in that, described high-speed pll/clock chip is placed on the test run circuit board of described test macro, by realizing data communication between connector and described FPGA hardware system.
8. test macro according to claim 1, is characterized in that, described utility appliance comprises power supply, AWG (Arbitrary Waveform Generator) and temperature control system.
9. test macro according to claim 1, it is characterized in that, programmed by Verilog, described FPGA hardware system carries out logic configuration to described PLL/ clock chip, and tests the DC parameter of described PLL/ clock chip and the connectivity of described PLL/ clock chip and described test macro.
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| CN107991600A (en) * | 2017-11-29 | 2018-05-04 | 成都锐成芯微科技股份有限公司 | Automatic test approach and its test system |
| CN109541443A (en) * | 2019-01-10 | 2019-03-29 | 北京智芯微电子科技有限公司 | Real-time clock detection device and method |
| CN109885434A (en) * | 2019-01-25 | 2019-06-14 | 华北水利水电大学 | A kind of integrated test system and method for FPGA high speed SerDes interface |
| CN111308330A (en) * | 2020-04-07 | 2020-06-19 | 华北水利水电大学 | FPGA DCM test system and method |
| CN111736655A (en) * | 2020-06-24 | 2020-10-02 | 山东大学 | Configuration method applied to clock chip |
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