CN109426594A

CN109426594A - A kind of chip debugging apparatus, method and computer readable storage medium

Info

Publication number: CN109426594A
Application number: CN201710743553.XA
Authority: CN
Inventors: 袁赛峰
Original assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Current assignee: Shenzhen ZTE Microelectronics Technology Co Ltd
Priority date: 2017-08-25
Filing date: 2017-08-25
Publication date: 2019-03-05

Abstract

The embodiment of the invention discloses a kind of chip debugging apparatus, which includes: command acquisition unit and command process unit；Wherein, the command acquisition unit, for obtaining encrypted debug command；Encrypted debug command is decrypted to obtain debug command, debug command is used to indicate the debugging operations to objective chip；Command acquisition unit is also used to for debug command to be sent to command process unit；Command process unit is converted into corresponding clock signal for receiving debug command, and by debug command；Command process unit is also used to clock signal being sent to objective chip, and objective chip is made to execute debugging operations according to clock signal.The embodiment of the invention also discloses the methods and computer readable storage medium of a kind of debugging of chip.

Description

Chip debugging device and method and computer readable storage medium

Technical Field

The present invention relates to chip debugging technologies, and in particular, to a chip debugging apparatus and method, and a computer readable storage medium.

Background

At present, the microelectronic industry in China is very rapidly developed under the promotion of market demands, and when the chip is applied to a product, the most important point is to develop software application on the chip, and the chip needs to be debugged in the development process of the software, so that a corresponding debugging device is needed to complete chip debugging.

Currently, Joint Test Action Group (JTAG) standards are mostly used for debugging chips, JTAG debugging is a chip debugging method formed according to the JTAG standards, many chips in the market also adopt JTAG debugging to complete debugging, and in practical application, many chip manufacturers have introduced debugging devices matched with chips produced by themselves, but the performance of the debugging devices is generally not high, only some relatively simple application programs can be debugged, and some efforts are not paid to the slightly complex application programs. For example: the downloading time of the application program of the new version is usually in the level of minutes, and the problems of slow refreshing speed, single step debugging blockage and the like exist during multi-thread debugging, so that the debugging speed of the chip is reduced.

Disclosure of Invention

In order to solve the foregoing technical problems, embodiments of the present invention are directed to providing a device and a method for debugging a chip, and a computer-readable storage medium, so as to improve the debugging speed of the chip.

The technical scheme of the invention is realized as follows: the embodiment of the invention provides a chip debugging device, which comprises: a command acquisition unit and a command processing unit; wherein,

the command acquisition unit is used for acquiring the encrypted debugging command; decrypting the encrypted debugging command to obtain a debugging command, wherein the debugging command is used for indicating debugging operation on a target chip;

the command acquisition unit is also used for sending the debugging command to the command processing unit;

the command processing unit is used for receiving the debugging command and converting the debugging command into a corresponding time sequence signal;

the command processing unit is further configured to send the timing signal to the target chip, so that the target chip executes a debugging operation according to the timing signal.

In the above scheme, the command obtaining unit is an advanced reduced instruction set processor (Acorn RISC Machine, ARM), and the command processing unit is a Field Programmable Gate Array (FPGA).

In the above solution, the debug command is a joint test action group JTAG debug command, and the timing sequence includes: a test clock signal, a test mode select signal, a test data input signal and a test data output signal;

the command processing unit is specifically used for converting the JTAG debugging command into a JTAG time sequence signal comprising a test clock signal, a test mode selection signal and a test data input signal;

the command processing unit is further configured to receive a test data output signal sent by the target chip.

In the above scheme, the apparatus further comprises: a level conversion unit;

the level conversion unit is used for converting the level of the time sequence signal into a level adaptive to the target chip; and outputting the time sequence signal after the level conversion to the target chip.

In the above scheme, the apparatus further comprises: a command setting unit;

the command setting unit is used for setting a corresponding debugging command for the target chip;

the debug command includes: a command portion and a data portion; the command part comprises N command bytes, the data part comprises M data bytes, and N and M are positive integers;

the command part is used for instructing the target chip to execute debugging operation, and the data part comprises data input to the target chip.

In the above solution, each command byte in the command part includes: the command code located at the lower four bits and the command code parameter located at the upper four bits, or the command code located at the lower four bits and an arbitrary value located at the upper four bits;

the command code parameter refers to an execution parameter corresponding to a command code located in low and medium bits of the same byte, and the execution parameter is used for specifically indicating the debugging operation executed by the target chip.

The embodiment of the invention also provides a chip debugging method, which comprises the following steps:

acquiring an encrypted debugging command;

decrypting the encrypted debugging command to obtain a debugging command, wherein the debugging command is used for indicating debugging operation on a target chip;

converting the debugging command into a corresponding time sequence signal;

and sending the time sequence signal to the target chip, so that the target chip executes debugging operation according to the time sequence signal.

In the foregoing scheme, the obtaining the encrypted debug command includes: controlling an advanced reduced instruction set processor ARM to acquire a debugging command;

correspondingly, the decrypting the encrypted debugging command to obtain the debugging command includes:

controlling the ARM to decrypt the encrypted debugging command to obtain a debugging command;

correspondingly, the converting the debug command into a corresponding timing signal includes:

controlling a Field Programmable Gate Array (FPGA) to convert the debugging command into a time sequence signal;

correspondingly, the sending the timing signal to the target chip includes:

and controlling the FPGA to send the timing signal to the target chip.

In the above scheme, the debug command is a Joint Test Action Group (JTAG) debug command; the timing sequence includes: a test clock signal, a test mode select signal, a test data input signal and a test data output signal;

the converting the debug command into a corresponding timing signal includes: converting the JTAG debug command into a JTAG timing signal including a test clock signal, a test mode selection signal and a test data input signal;

correspondingly, after the sending the timing signal to the target chip, the method further includes: and receiving a test data output signal sent by the target chip.

In the foregoing solution, the sending the timing signal to the target chip includes:

converting the level of the time sequence signal into a level adapted to the target chip;

and outputting the time sequence signal after the level conversion to the target chip.

In the foregoing solution, before the obtaining the encrypted debug command, the method further includes:

setting a corresponding debugging command for the target chip; wherein the debug command comprises: a command portion and a data portion; the command part comprises N command bytes, the data part comprises M data bytes, and N and M are positive integers; the command part is used for instructing the target chip to execute debugging operation, and the data part comprises data input to the target chip.

the command code parameter refers to an execution parameter corresponding to a command code of lower four bits located in the same byte, and the execution parameter is used for specifically indicating a debugging operation executed by the target chip.

An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps of any one of the methods described above.

The embodiment of the invention provides a chip debugging device, a chip debugging method and a computer readable storage medium, wherein the device comprises: a command acquisition unit and a command processing unit; the command acquisition unit is used for acquiring the encrypted debugging command; decrypting the encrypted debugging command to obtain a debugging command, wherein the debugging command is used for indicating the debugging operation of the target chip; the command acquisition unit is also used for sending the debugging command to the command processing unit; the command processing unit is used for receiving the debugging command and converting the debugging command into a corresponding time sequence signal; and the command processing unit is also used for sending the time sequence signal to the target chip so that the target chip executes debugging operation according to the time sequence signal. By adopting the technical scheme, the two different processing units can be used for respectively realizing the acquisition and conversion of the debugging command, and compared with the single processing unit, the acquisition speed and the conversion speed of the debugging command are improved, so that the debugging speed of the chip is improved.

Drawings

FIG. 1 is a schematic diagram of a first component structure of a chip debugging apparatus according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a second component structure of the chip debugging apparatus according to the embodiment of the present invention;

FIG. 3 is a schematic diagram of a JTAG module of a target chip according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating the operation flow of the TAP controller in the target chip according to the embodiment of the present invention;

FIG. 5 is a schematic diagram of a third component structure of the chip debugging apparatus according to the embodiment of the present invention;

fig. 6 is a flowchart illustrating a method for debugging a chip according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Example one

The embodiment of the invention provides a chip debugging device, which can realize the debugging of a target chip, for example: and performing JTAG debugging on the target chip, wherein the device can output a self-defined debugging command to a JTAG interface of the target chip, and the target chip executes corresponding debugging operation according to the obtained debugging command.

Fig. 1 is a schematic diagram of a first component structure of a chip debugging apparatus according to an embodiment of the present invention, and as shown in fig. 1, a chip debugging apparatus 10 includes: a command acquisition unit 101 and a command processing unit 102; wherein,

a command obtaining unit 101, configured to obtain an encrypted debug command; and decrypting the encrypted debugging command to obtain a debugging command, wherein the debugging command is used for indicating the debugging operation of the target chip.

The command acquiring unit 101 may further be configured to send a debug command to the command processing unit.

The command processing unit 102 may be configured to receive a debug command and convert the debug command into a corresponding timing signal.

The command processing unit 102 may be further configured to send the timing signal to the target chip, so that the target chip performs a debugging operation according to the timing signal.

In actual implementation, the command acquiring unit may be an ARM, the command processing unit may be an FPGA, and the ARM may communicate with the FPGA through an Advanced eXtensible Interface (AXI) bus. In the embodiment of the invention, the chip debugging device formed by combining the ARM and the FPGA can realize high-speed chip debugging, has the advantages of simple structure and low cost compared with a high-end chip debugging product with complex structure and high cost, and can be compared with the debugging performance of the high-end product.

In practical implementation, the debug command may be a joint test action group JTAG debug command, and the command processing unit converts the JTAG debug command into a JTAG timing signal conforming to IEEE1149.1 standard, and communicates with the target chip through a JTAG interface in the chip debug apparatus, where the JTAG interface may include the following 4 pins:

test Clock input (TCK);

a Test Mode Select (TMS) for setting a Test Access Port (TAP) controller;

test Data In (TDI), wherein Data are input to the TAP controller through the TDI;

test Data Output (TDO), through which Data is Output from the TAP controller.

Here, the TAP controller is a state machine in JTAG, and the state machine of the TAP controller converts between different states through TCK and TMS to realize input of data and commands.

Accordingly, the timing signal may include: a test clock signal, a test mode select signal, a test data input signal, and a test data output signal.

Illustratively, the command processing unit is specifically configured to convert a JTAG debug command into a JTAG timing signal including a test clock signal, a test mode selection signal, and a test data input signal; and the command processing unit is also used for receiving the test data output signal sent by the target chip.

In practical implementation, the apparatus may further include: a level conversion unit; the level conversion unit is used for converting the level of the time sequence signal into a level adaptive to the target chip; and outputting the level-converted timing signal to the target chip. For example, the level conversion unit may be a MAX232 chip, a MAX485 chip, or the like, or may select a corresponding level conversion chip according to a service requirement, and the type of the level conversion chip is not specifically limited in the embodiment of the present invention.

It can be understood that the level of the input signal of the target chip is not a uniform standard, and in order to make the application range of the device wider, the added level conversion unit can convert the level of the output timing signal into a level adapted to the target chip, thereby expanding the debugging range of the chip.

In practical implementation, the apparatus may further include: a command setting unit; and the command setting unit is used for setting a corresponding debugging command for the target chip. It should be noted that, by customizing the debug command, the corresponding debug command can be set according to the actual service requirement, so as to complete the debugging of different chips.

Illustratively, the debug command includes: a command portion and a data portion; the command part comprises N command bytes, the data part comprises M data bytes, and N and M are positive integers; the command part is used for instructing the target chip to execute debugging operation, and the data part comprises data input to the target chip.

Illustratively, each command byte in the command portion includes: the command code located at the lower four bits and the command code parameter located at the upper four bits, or the command code located at the lower four bits and an arbitrary value located at the upper four bits; the command code parameter refers to an execution parameter corresponding to a command code located in low or middle bits of the same byte, and the execution parameter is used for specifically indicating a debugging operation executed by the target chip.

Illustratively, the debug command may consist of 1 command byte and M data bytes, M being an integer from 0 to 7, and the format of one byte in the customized debug command is as follows:

7	6	5	4	3	2	1	0
								P	P	P	P	C	C	C	C

wherein CCCC is a command code, PPPP is a command code parameter corresponding to the command code in the byte, and if there is no parameter, it is an arbitrary value, for example: any value may be 0000 or 1111.

Illustratively, according to the command format, the following three JTAG debugging commands are customized, so that a simple JTAG debugging function can be completed, and during actual application, the debugging commands can be extended according to business needs.

(1) Setting the state of a target chip TAP controller

Command byte(s):

S

0

1

wherein, the command code: 0001B;

command parameters: the SSSS value range is 0-15, which respectively corresponds to the states of 16 TAP controllers, and the SSSS value range is represented by binary: 0000B-1111B.

(2) Setting State Soft reset of target chip TAP controller

Command byte(s):

X

0

1

wherein, the command code: 0010B;

command parameters: XXXXXX can be ignored as arbitrary values.

(3) Outputting x bit data and reading in x bit data

Command byte(s):

X

T

0

1

data bytes:

D

wherein, the command code: 0011B;

command parameters: t represents the electric level of TMS after the last data bit is output, 0 represents low electric level 1 represents high electric level, T is also used for identifying whether the data output is ended after the last data bit is output, when T is 0, the data output is continued, and when T is 1, the data output is ended;

command parameters: XXX ranges from 0 to 7 and is used to indicate the output of data bytes. For example: when XXX is 3 (i.e., XXX is 0011B), it represents the data of the 0-3 bits in the output data byte.

Data command: DDDDDDDD represents the data that needs to be output from TDI.

In the embodiment of the invention, the data is decimal data without special marks, the data with 0x as the head is hexadecimal data, and the data with B as the tail is binary data.

In practical implementation, the function of the command setting unit may also be implemented by the command acquiring unit.

In another optional embodiment, the command setting unit may also be located in the upper computer, and the command format is preset by the upper computer, and the debugging command of the target chip is customized according to the set command format.

In practical applications, the command acquiring Unit 101, the command Processing Unit 102 and the command setting Unit can be implemented by a Central Processing Unit (CPU), a microprocessor Unit (MPU), a Digital Signal Processor (DSP), a Complex Programmable Logic Device (CPLD), etc.

In the embodiment of the present invention, the chip debugging apparatus includes: a command acquisition unit and a command processing unit; the command acquisition unit is used for acquiring the encrypted debugging command; decrypting the encrypted debugging command to obtain a debugging command, wherein the debugging command is used for indicating the debugging operation of the target chip; the command acquisition unit is also used for sending the debugging command to the command processing unit; the command processing unit is used for receiving the debugging command and converting the debugging command into a corresponding time sequence signal; and the command processing unit is also used for sending the time sequence signal to the target chip so that the target chip executes debugging operation according to the time sequence signal. By adopting the technical scheme, the two different processing units can be used for respectively realizing the acquisition and conversion of the debugging command, and compared with the single processing unit, the acquisition speed and the conversion speed of the debugging command are improved, so that the debugging speed of the chip is improved.

Example two

To further illustrate the object of the present invention, the following description is given on the basis of the first embodiment of the present invention.

Fig. 2 is a schematic diagram of a second component structure of the chip debugging apparatus in the embodiment of the present invention, and as shown in fig. 2, the chip debugging apparatus 20 includes: ARM201, FPGA202, level shift chip 203 and bus 204.

The ARM201 is used for receiving an encrypted debugging command sent by the upper computer, and after the debugging command is decrypted, the debugging command is written into the FPGA202 through the bus 204. Illustratively, the bus 204 may be a 32-bit AXI bus, and the 32-bit AXI bus may implement high-speed transmission of debug commands between the ARM201 and the FPGA 202.

Before the chip debugging is started, the ARM201 is further configured to set working parameters of the FPGA202, where the working parameters at least include a working frequency of the FPGA and a command output frequency. The ARM201 is specifically configured to receive parameter setting information sent by the upper computer, and set working parameters such as a working frequency and a command output frequency of the FPGA202 through the bus 204.

The FPGA202 is configured to convert the debug command into a timing signal, and send the timing signal to the target chip 21.

The FPGA202 is specifically configured to convert the debug command into a timing signal including TCK, TMS, and TDI, send the timing signal to the target chip 21 through the level shift chip 203, and receive and cache the debug result sent by the target chip 21 through TDO.

Specifically, after receiving the debug command, the FPGA202 parses the command byte, and debugs the target chip according to the command code of the lower four bits and the command code of the upper four bits in the command byte (or the command code parameter may not exist).

The level conversion chip 203 is configured to convert the levels of the timing signals TCK, TMS, and TDI into levels adapted to the target chip, send the converted timing signals to the target chip 21, convert the level of the debugging result sent by the target chip 21 through TDO into a level adapted to the FPGA202, and send the converted debugging result to the FPGA 202. Illustratively, the level shift chip 203 may adapt the chip debugging apparatus to a target chip with an operating voltage of 1.5v-3.3 v.

The ARM201 is also used for reading a debugging result from the FPGA202 and uploading the debugging result to an upper computer.

In the embodiment of the invention, the chip is debugged by utilizing the debugging command with high compression rate generated by the ARM and combining the rapid data processing advantage of the FPGA, the processing speed is greatly improved compared with the traditional chip debugging by utilizing a single processor, and the ARM + FPGA has simple structure and lower cost.

EXAMPLE III

In order to further embody the purpose of the present invention, on the basis of the first embodiment and the second embodiment of the present invention, JTAG debugging on a target chip by using the chip debugging apparatus provided in the embodiment of the present invention is further illustrated.

In practical implementation, the target chip includes a JTAG module for implementing JTAG debugging of the target chip, and as long as the JTAG module of the target chip is established in compliance with IEEE1149.1 standard, the apparatus can communicate with the target chip and complete JTAG debugging of the target chip.

Fig. 3 is a schematic structural diagram of a JTAG module in a target chip according to an embodiment of the present invention, and as shown in fig. 3, the JTAG module includes: TAP controller 311, data register DR312 and instruction register IR313, wherein the data register DR312 further includes: a 0# bypass register, a 1# data scan chain, and a 2# address scan chain. Since the JTAG module is built in conformity with the IEEE1149.1 standard, the functions and operation of each part are not described in detail herein.

Fig. 4 is a schematic operation flow diagram of a TAP controller in a target chip according to an embodiment of the present invention, and as shown in fig. 4, the TAP controller includes 16 states, which are respectively: state 0: Test-Logic Reset, state 1: run Test/Idle, State 2: Select-DR Scan, state 3: Capture-DR, state 4: Shift-DR, State 5: exit1-DR, state 6: Pause-DR, state 7: exit2-DR, state 8: Update-DR, state 9: Select-IR Scan, state 10: Capture-IR, state 11: Shift-IR, State 12: exit1-IR, State 13: Pause-IR, state 14: exit2-IR and status 15: Update-IR. The debugging operation of the target chip can be realized by controlling the TAP controller to be switched in different states.

In fig. 4, transition of the state of the TAP controller is indicated by TMS, and a semicircular arrow in the figure indicates that the TAP controller remains in this state when TMS is 0 or 1; the straight or dashed arrow in the figure indicates that when TMS is 0 or 1, the TAP controller transitions from the current state to the state indicated by the arrow. For example: in state 0: Test-Logic Reset, when TMS is 1, the TAP controller remains in state 0; when TMS is 0, the TAP controller transitions from state 0 to state 1. In state 2: Select-DR Scan, when TMS ═ 1, the TAP controller transitions from state 2 to state 9; when TMS is 0, the TAP controller transitions from state 2 to state 3.

In practical implementation, the access procedure of the TAP controller to the instruction register in the JTAG module is as follows:

1. the system is powered on, and the TAP controller enters a state 0: Test-Logic Reset;

2. the TAP controller sequentially passes through: run Test/Idle, Select-DR Scan, Select-IR Scan, Capture-IR, Shift-IR, Exit1-IR, Update-IR, and finally return to State 1: run Test/Idle state.

The access flow of the TAP controller to the data register in the JTAG module is as follows:

1. the currently accessible data register is determined by the current instruction in the instruction register;

2. in state 1: with Run Test/Idle as a starting point, the TAP controller sequentially passes through: run Test/Idle, Select-DR Scan, Capture-DR, Shift-DR, Exit1-DR, Update-DR, finally return to State 1: run Test/Idle.

Fig. 5 is a schematic diagram of a third component structure of the chip debugging apparatus in the embodiment of the present invention, and as shown in fig. 5, the chip debugging apparatus 50 includes: an ARM501, an FPGA502, and a level conversion unit 503, wherein the ARM501 is connected to the FPGA502 through an AXI bus, wherein,

the FPGA502 can include: an AXI bus matrix subunit 502a, a control subunit 502b, a command cache subunit 502c, a result cache subunit 502d, a command processing subunit 502e, and a JTAG interface 502 f.

The ARM501 is communicated with an upper computer and is used for acquiring an encrypted JTAG debugging command issued by the upper computer; the ARM501 is connected with an AXI bus matrix subunit 502a through an AXI bus, one end of the control subunit 502b, one end of the command cache subunit 502c and one end of the result cache subunit 502d are connected with the AXI bus matrix subunit 502a respectively, and the other end of the control subunit, the command cache subunit 502c and the result cache subunit 502d are connected with the command processing subunit 502e respectively; the command processing subunit 502e is connected to a JTAG interface 502f through a JTAG bus, and four pins TCK, TMS, TDI, and TDO of the JTAG interface 502f are connected to the level conversion unit 503, respectively; the level shift unit 503 transmits the TCK, TMS, TDI signals received from the JTAG interface 502f to the TAP controller 511 of the target chip 51, respectively, and receives the debug result TDO signal transmitted from the TAP controller 511.

Specifically, ARM501 sends the decrypted JTAG debug command to AXI bus matrix subunit 502a through the AXI bus;

in actual implementation, the specific implementation steps of the chip debugging apparatus in performing JTAG debugging on the target chip may include the following:

step 1: ARM501 receives the encrypted JTAG debug command sent by the upper computer and sends all the decrypted JTAG debug commands to FPGA502 through the AXI bus.

Step 2: an AXI bus matrix subunit 502a in FPGA502 receives all JTAG debug commands sent by ARM 501.

And step 3: detecting whether the control subunit 502b is idle, if so, caching a part of debugging commands in the AXI bus matrix subunit 502a into the command cache subunit 502c, and executing step 4; if not, the step 3 is continuously executed to wait for the control subunit 502b to be idle and then read the debug command.

And 4, step 4: the control subunit 502b triggers the command processing subunit 502e to operate, so that the command processing subunit 502e reads the debug command from the command buffer subunit 502 c.

And 5: the command processing subunit 502e converts each JTAG debug command into a JTAG timing signal, and sends the JTAG timing signal to the target chip 51 through the JTAG interface 502f, wherein the command processing subunit 502e communicates with the JTAG interface through the JTAG bus.

Step 6: the level shift unit 503 receives the debug result sent from the TDO pin by the TAP controller 511, and sends the debug result to the command processing subunit 502e through the JTAG bus, and the command processing subunit 502e buffers the debug result in the result buffer subunit 502 d.

And 7: the ARM501 detects whether the control subunit 502b is idle, and if so, reads a debugging result from the result cache subunit 502d and sends the debugging result to an upper computer; if not, the step 7 is continuously executed to wait for the control subunit 502b to be idle and then read the debugging result.

TABLE 1

Byte orderNumber (C)	JTAG debug command	Description of the invention
			1	00000010B	TAP state machine reset
2	10110001B	Setting TAP to State 11: Shift-IR
			3	00110011B	Output 2 bit data
4	00000010B	Binary data output
			5	01000001B	Setting TAP to state 4: Shift-DR
6	11100011B	Output 8 bit data
			7	00000000B	Binary data output
8	11100011B	Output 8 bit data
			9	00010000B	Binary data output
10	11100011B	Output 8 bit data
			11	00000000B	Binary data output
12	11110011B	Output 8 bit data
			13	00000000B	Binary data output
14	10110001B	Setting TAP to State 11: Shift-IR
			15	00110011B	Output 2 bit data
16	00000001B	Binary data output
			17	01000001B	Setting TAP to state 4: Shift-DR
18	11100011B	Output 8 bit data
			19	01111000B	Binary data output
20	11100011B	Output 8 bit data
			21	01010110B	Binary data output
22	11100011B	Output 8 bit data
			23	00110100B	Binary data output
24	11110011B	Output 8 bit data
			25	00010010B	Binary data output

In the third embodiment, taking the example of writing one byte of data into the target chip as a further example, for example, writing data 0x12345678 into the destination address 0x00001000 of the target chip 51, the binary formats of the destination address and the write data are:

destination address: 0x00001000 ═ 00000000000000000001000000000000B

Writing data: 0x12345678 ═ 00010010001101000101011001111000B

Defining the JTAG debug command corresponding to the debugging process according to the format of the debug command defined in the first embodiment, to obtain 25 JTAG debug commands, where a specific JTAG debug command is shown in table 1.

After receiving the JTAG debug command, the command processing subunit 502e sequentially reads the JTAG debug command from the command buffer subunit 502c according to the byte sequence numbers in table 1, and operates the TMS and TDI under the drive of the TCK, or stores the debug result in the TDO into the result buffer subunit 502d under the drive of the TCK, so as to implement the command interaction with the TAP controller 511 of the target chip 51 and execute the debug operation on the target chip 51.

With reference to the JTAG module structure shown in fig. 3 and the operation flow shown in fig. 4, a processing procedure of each debug command in the embodiment of the present invention is briefly described, and a specific command processing procedure is as follows:

byte 1: after determining that the low four-bit command code of the command byte is a reset command, the command processing subunit 502e continuously outputs 5 TMS ═ 1 signals to the TAP controller 511 through the JTAG interface 502f, and as can be seen from fig. 4, no matter which state the TAP is in, the TAP controller returns to state 0 after receiving the 5 continuous TMS ═ 1 signals: Test-Logic Reset, then output a TMS of 0, TAP switches to state 1: RunTest/Idle, TMS always outputs 0 if there are no other operations, TAP remains in state 1: run Test/Idle, ready for other operations.

Byte 2: after determining that the command code 0001B of the byte is the set TAP state command, the command processing subunit 502e further parses the command code parameter 1011B into a state 11: Shift-IR and determines that the command has no data bytes, then from the TMS output 1100B, the TAP state machine will switch from state 1 to state 11, entering the instruction register IR Shift state, according to the operational flow of fig. 4.

Byte 3: the command processing subunit 502e analyzes the command code 0011B for data output and read-in, the analyzing parameter T is 1, the TMS is high level after data output is completed, the parameter CCC takes a value of 1, i.e. 0-1 bits of the data byte need to be output, so the FPGA reads 0-1 bits of the 4 th byte and outputs the 0-1 bits from the TDI to the IR register; according to the principle of a TAP state machine, data of two bits are read into the FPGA from the TDO (no matter whether the two bit data are needed or not), the FPGA returns to the ARM after receiving the data, the ARM side software judges whether the data of the TDO are needed or not according to functions, and if the data are not needed, the data are directly ignored; and if necessary, uploading the data to an upper computer.

After data output is finished, the TMS output parameter T is 1, and the TAP state machine is from state 11: Shift-IR switches to State 12: Exit-IR, ending output; TMS outputs 10B again, TAP switches to state 15: Update-IR, finally back to State 1: RunTest/Idle, at Update-IR, data 2 output to instruction register IR will be in effect, indicating access to the 2# address scan chain in data register DR; the data scan selection in fig. 3 interfaces the 2# address scan chain with the data register DR so that the next operation on the data register is the operation on the 2# address scan chain.

Byte 4: which is a data byte, has been used at the time of the 3 rd byte processing.

The purpose of the above processing of the 2 nd byte to the 4 th byte is to realize the selection of the 2# address scan chain.

Byte 5: parsing command code 0001B to set TAP state, further parsing command code parameter 0100B to 4, according to the operation flow of fig. 4, TMS output 1100B is from state 1: run Test/Idle switches to State 4: Shift-DR.

Byte 6: the analysis command code 0011B is data output and read-in, the TMS is low level after the data output is finished when the analysis parameter T is 0, the parameter CCC is 7, namely 0-7 bits of the data byte need to be output, so that the FPGA reads the next 0-7 bits of the byte and outputs the next 0-7 bits from the TDI to the DR register, namely outputs the next 0-7 bits to the 2# address scan chain, meanwhile, 8 bits of the 2# address scan chain are read in from the TDO, the FPGA returns read-in data to the ARM, and the data processing is determined by software. After 8 bits output, the TMS output parameter T is 0, and the TAP state is kept at state 4: Shift-DR, continues to prepare the output data from TDI.

Byte 7: is a data byte, has been processed in byte 6.

Bytes 8, 9, 10, 11, 12, 13: all the bytes are data output bytes, the processing of the 6 th byte and the 7 th byte can be referred to, the only difference is that T in a 12 th byte command parameter is 1, TMS output 1 is identified after the command is executed, data output is ended, and TAP is switched to a state 5: exit1-DR, so far destination address 0x00001000 has been fully output into data register DR, following TMS output 10B, TAP switches to state 8: Update-DR, finally back to State 1: run Test/Idle. At Update-DR, the data in the 2# address scan chain will be updated to the address bus, which is located to address 0x00001000 of the target chip.

The purpose of the above processing of the 5 th byte to the 13 th byte is to output a destination address into the 2# address scan chain, and locate the address 0x00001000 of the target chip.

14 th, 15 th, 16 th byte: the processing mode is similar to bytes 2, 3 and 4, except that the 16 th byte data output is 00000001B, which indicates that the data output to the instruction register IR is 1, after the operation is finished, the 1# data scan chain is connected with the data register DR, and the operation on the data register is the operation on the data scan chain.

17 th byte: as with byte 5, setting the TAP state to state 4: Shift-DR

18 th to 25 th bytes: the operation is the same as bytes 6-13, except that the data byte is output, here 0x12345678 is output to the 1# data scan chain in the data register DR, at Update-DR, the data 0x12345678 in the 1# data scan chain is updated to the data bus, and at this time, the address bus is in the memory cell of 0x00001000, completing the data writing.

The above is an example of the flow of writing data 0x12345678 to address 0x00001000, and other operations are similar to the flow.

Through the exemplary debugging command processing process, the corresponding debugging command can be set according to the actual service requirement, and different debugging operations are completed.

Example four

Based on the same inventive concept, an embodiment of the present invention further provides a method for debugging a chip, fig. 6 is a schematic flow chart of the method for debugging a chip in the embodiment of the present invention, and as shown in fig. 6, the method includes:

step 601: and acquiring the encrypted debugging command.

In practical implementation, before obtaining the encrypted debug command, the method further includes: setting a corresponding debugging command for a target chip;

exemplary debug commands may include: a command portion and a data portion; the command part comprises N command bytes, the data part comprises M data bytes, and N and M are positive integers; the command part is used for instructing the target chip to execute debugging operation, and the data part comprises data input to the target chip.

Specifically, each command byte in the command section includes: the command code located at the lower four bits and the command code parameter located at the upper four bits, or the command code located at the lower four bits and an arbitrary value located at the upper four bits; the command code parameter refers to an execution parameter corresponding to a command code of lower four bits located in the same byte, and the execution parameter is used for specifically instructing a target chip to execute a debugging operation.

Step 602: and decrypting the encrypted debugging command to obtain the debugging command.

Here, the debug command is used to instruct a debug operation on the target chip.

Step 603: the debug command is converted into a corresponding timing signal.

Illustratively, when the debug command is a JTAG debug command, the timing sequence includes: a test clock signal, a test mode select signal, a test data input signal and a test data output signal; correspondingly, converting the JTAG debugging command into a JTAG time sequence signal comprising a test clock signal, a test mode selection signal and a test data input signal;

step 604: and sending the time sequence signal to a target chip, so that the target chip executes debugging operation according to the time sequence signal.

In actual implementation, the level of the timing signal is converted into a level matched with a target chip; and outputting the time sequence signal after the level conversion to a target chip.

Illustratively, when the debug command is a JTAG debug command, after the timing signal is transmitted to the target chip, the method further includes: and receiving a test data output signal sent by the target chip.

For example, the ARM may be controlled to obtain the debug command; and controlling the ARM to decrypt the encrypted debugging command to obtain the debugging command.

For example, the FPGA may be controlled to convert the debug command into a timing signal; and controlling the FPGA to send the time sequence signal to the target chip.

EXAMPLE five

Based on the same inventive concept, embodiments of the present invention further provide a computer-readable storage medium, such as a memory including a computer program, which is executable by a processor in a chip commissioning apparatus to perform the method steps in one or more of the foregoing embodiments.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks and/or flowchart block or blocks.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A chip debug apparatus, comprising: a command acquisition unit and a command processing unit; wherein,

2. The apparatus of claim 1, wherein the command fetch unit is an advanced reduced instruction set processor (ARM) and the command processing unit is a Field Programmable Gate Array (FPGA).

3. The apparatus of claim 1, wherein the debug command is a Joint Test Action Group (JTAG) debug command, and wherein the timing comprises: a test clock signal, a test mode select signal, a test data input signal and a test data output signal;

4. The apparatus of claim 1, further comprising: a level conversion unit;

5. The apparatus of claim 1, further comprising: a command setting unit;

6. The apparatus of claim 5, wherein each command byte in the command portion comprises: the command code located at the lower four bits and the command code parameter located at the upper four bits, or the command code located at the lower four bits and an arbitrary value located at the upper four bits;

7. A method for debugging a chip, the method comprising:

acquiring an encrypted debugging command;

converting the debugging command into a corresponding time sequence signal;

8. The method of claim 7, wherein obtaining the encrypted debug command comprises: controlling an advanced reduced instruction set processor ARM to acquire a debugging command;

correspondingly, the sending the timing signal to the target chip includes:

and controlling the FPGA to send the timing signal to the target chip.

9. The method of claim 7, wherein the debug command is a Joint Test Action Group (JTAG) debug command; the timing sequence includes: a test clock signal, a test mode select signal, a test data input signal and a test data output signal;

10. The method of claim 7, wherein sending the timing signal to the target chip comprises:

11. The method of claim 7, wherein prior to the obtaining the encrypted debug command, the method further comprises:

12. The method of claim 11,

each command byte in the command portion includes: the command code located at the lower four bits and the command code parameter located at the upper four bits, or the command code located at the lower four bits and an arbitrary value located at the upper four bits;

13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 7 to 12.