CN112486752A - Processor tracking system, method, storage medium and terminal - Google Patents
Processor tracking system, method, storage medium and terminal Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Abstract
The invention provides a processor tracking system, a method, a storage medium and a terminal, wherein the tracking system comprises: the JTAG interface module is used for being in communication connection with the control module and analyzing JTAG instructions; a processor module; the tracking logic module is embedded inside the processor module and is in communication connection with the processor module; the tracking cache module is in communication connection with the tracking logic module; the JTAG interface module is respectively in communication connection with the tracking logic module and the tracking cache module through a system bus, the tracking logic module is used for packaging standard tracking data in the processor module into a tracking data packet and outputting the tracking data packet to the tracking cache module, the tracking cache module is used for caching the tracking data packet, caching and tracking of processor data are realized through a conventional JTAG interface on a chip, debugging efficiency of the processor is improved, and meanwhile cost of a processor tracking scheme is reduced.
Description
Technical Field
The present invention relates to the field of processor debugging technologies, and in particular, to a processor tracing system, a processor tracing method, a storage medium, and a terminal.
Background
RISC-V is an open source Instruction Set Architecture (ISA) based on Reduced Instruction Set (RISC) principles. In contrast to most instruction sets, the RISC-V instruction set is free to serve any purpose, allowing anyone to design, manufacture and market RISC-V chips and software. While this is not the first set of open source instructions, it is of great significance because its design makes it suitable for modern computing devices (e.g., warehouse-scale cloud computers, high-end mobile phones, and tiny embedded system systems). The instruction set also has a lot of supporting software, which addresses the common weaknesses of new instruction sets. The RISC-V instruction set is designed in consideration of the real-world situation of small size, high speed, and low power consumption, but no over-design is made for a specific micro-architecture. Compared with other relatively mature architectures such as X86 and ARM on the market, the RISC-V instruction set architecture processor has obvious advantages in the aspects of cost and power consumption, and is very suitable for designing an autonomous controllable processor in China due to the open source characteristic.
The debugging and tracing scheme of the processor is an essential part for program debugging and problem location. With the gradual improvement of the performance of the embedded system processor, the operation speed is faster and faster, the processed data volume is larger and larger, and the traditional debugging method such as a ROM resident monitoring program and a serial port debugging tool can not meet the requirements.
At present, the mainstream processors (including ARM, RISC-V, MIPS and the like) all adopt a kernel debugging channel based on JTAG, have typical ICE functions, are connected with a host computer through a JTAG port based on a system chip containing a debugging module, and complete debugging by supporting normal breakpoints, observation points, processor and system state access through configuration. In order to track the code in real time, for example, an Embedded Trace Macrocell (ARM) is also provided, so that the debugging of the application program is more comprehensive. Compared with the traditional debugging methods such as breakpoint and single step, the Trace (Trace) function can record the running track of the whole section of code of the program, and the problem positioning capability of processor debugging is greatly enhanced. The RISC-V instruction set architecture has already defined the instruction/data packet standard of the program tracking at present (hardware is through packing and sending the program information according to the standard, display the program movement track according to the standard unpacking after transmitting to the upper computer), but the data path of the upper computer of the tracking instruction/data packet is not defined in the whole scheme, the RISC-V processor is in urgent need of a general, easy-to-implement complete tracking scheme at present.
Patent No. CN10795350A discloses a trace debugging method and system based on ethernet interface, which is the most similar scheme to the present invention. In the patent, the upper computer and the processor communicate through an Ethernet interface, namely, the upper computer informs the processor to track programs/Data through the Ethernet, and the tracking and packaging Data (Trace Data) is transmitted back to the upper computer through the Ethernet interface.
However, the scheme depends on ethernet communication and data transmission, and the application range is limited greatly, because only a small part of chips have ethernet interfaces, if the chips do not have ethernet interfaces, the scheme cannot be realized.
Therefore, there is a need to provide a novel processor tracing system, method, storage medium and terminal to solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a processor tracking system, a processor tracking method, a storage medium and a terminal, which realize caching and tracking of processor data through a conventional JTAG interface on a chip and improve the debugging efficiency of a processor.
To achieve the above object, the processor tracking system of the present invention includes:
the JTAG interface module is used for being in communication connection with the control module and analyzing JTAG instructions;
a processor module;
a trace logic module embedded within the processor module and communicatively coupled to the processor module;
the tracking cache module is in communication connection with the tracking logic module;
the JTAG interface module is respectively in communication connection with the tracking logic module and the tracking cache module through a system bus, the tracking logic module is used for packaging standard tracking data in the processor module into tracking data packets and outputting the tracking data packets to the tracking cache module, and the tracking cache module is used for caching the tracking data packets.
The invention has the beneficial effects that: the invention adopts JTAG interface modules of each chip to realize complete RISC-V processor tracking, thus the universality of the whole tracking processing scheme is stronger, meanwhile, on-chip cache of the chip is adopted to realize cache and data transmission of processor tracking data, no additional high-speed interface and interface receiving equipment in the chip are needed, and the cost of the whole tracking scheme is effectively reduced while the processor data tracking is realized.
Further, the trace logic module processes trace data within the processor module into the standard trace data via a trace specification, the trace specification defined by the processor module. The beneficial effects are that: the tracking data in the processor module is processed into standard tracking data through the tracking specification, so that the tracking data in the whole system has uniform standard specification, the subsequent data tracking efficiency is improved, the tracking specification can be defined through the processor module, and the use requirements of different data formats can be met.
Furthermore, the trace cache module is further communicatively connected with a judging unit and a requesting unit, the judging unit is configured to judge whether the trace cache module ends data caching, an output end of the requesting unit is communicatively connected with the trace logic module, and the requesting unit is configured to send a stop request. The beneficial effects are that: the state of the data cache in the tracking cache module is judged through the judging unit to determine whether the data cache is in a full state, and when the request unit determines that the tracking cache module is in the full state, a processor stop request is sent to the tracking logic module in time, so that the processor module stops working, and the whole data tracking cache process is stably carried out.
Further, the trace cache module includes an annular cache structure, when the control module actively turns off the trace enable or the annular cache structure encounters a breakpoint event, the determining unit determines that the trace cache module ends data caching, and the requesting unit sends a stop request to the processor module. The beneficial effects are that: the annular cache structure can cache a large amount of tracking data at the same time, not only can directly cache the latest section of tracking data, but also can stop caching when the annular cache structure starts a new circle of cache, thereby realizing the caching of each circle of tracking data and the caching processing of a plurality of sections of tracking data.
Further, the trace cache module further includes a memory cache structure, when the amount of cache data in the memory cache structure exceeds a set threshold, the determining unit determines that the trace cache module ends data caching, and the requesting unit sends a stop request to the processor module. The beneficial effects are that: the trace data is cached through a memory cache structure with a fixed storage space, so that the trace data with a fixed capacity can be cached every time, and different processor data tracking requirements are met.
Further, the control module further includes a switching unit, and the switching unit is in communication connection with the trace cache module through the system bus to switch and select any one of the ring cache structure and the memory cache structure to perform cache processing on the trace data packet. The beneficial effects are that: the free switching between the annular cache structure and the memory cache structure is realized through the switching unit, so that the selection requirements of different tracking schemes are realized, different cache modes are selected, and different use requirements are met.
Further, the JTAG interface module further includes a translation unit, and the translation unit is configured to translate an instruction from the control module into a register access operation instruction or a memory access operation instruction on the system bus. The beneficial effects are that: the translation unit translates the instruction of the control module so as to realize the communication between the control module and the whole system through the system bus.
Further, the control module comprises at least one of an upper computer and an embedded system.
The invention provides a processor tracking method, which comprises the following steps:
s1, the control module generates a configuration instruction, the configuration instruction is converted into register access on a system bus through the JTAG interface module, and the tracking logic module is configured;
s2, the control module generates a start instruction and starts the tracking function of the tracking logic module through the JTAG interface module and the system bus;
s3, the tracking logic module packs the tracking data into a tracking data packet and outputs the tracking data packet to the tracking cache module;
s4, the tracking cache module performs tracking cache processing on the tracking data packet until stopping;
and S5, the control module reads all data in the tracking cache module through the system bus and displays the tracking result.
The method has the beneficial effects that: the whole tracking scheme adopts a common JTAG interface to realize processor tracking, has stronger universality, simultaneously adopts the JTAG interface and on-chip cache to realize cache and transmission of tracking data of the processor, does not need an additional high-speed interface and a high-speed interface receiving device in the processor, and greatly reduces the use cost of the tracking scheme of the processor.
Further, the process of step S4 includes:
s41, the control module generates a switching instruction through a switching unit, and switches and selects any one of the ring cache structure and the memory cache structure in the tracking cache module for caching through a system bus;
s42, the tracking cache module caches the tracking data packet according to the selected cache structure;
s43, after the judgment unit judges that the cache structure in the tracking cache module finishes data caching, a stop request is generated by the request unit and transmitted to the processor module, and the processor module is stopped. The beneficial effects are that: according to the use requirement, the switching unit generates a switching instruction to select an annular cache structure or a memory cache structure as a cache structure to cache the trace data, so that the trace cache module realizes trace caching of the trace data.
Further, when the switching unit generates the switching instruction to select the annular cache structure, the trace cache module caches a trace data packet through the annular cache structure, when the control module actively turns off trace enable or the annular cache structure encounters a breakpoint event, the judgment unit judges that the annular cache structure ends data caching, and the request unit generates a stop request, transmits the stop request to the processor module, and stops the processor module. The beneficial effects are that: when the tracking data is cached through the annular cache structure, whether the annular cache structure is in a full state or not is judged according to whether the annular cache structure starts a new circle of cache, the request unit generates a stop request when the annular cache structure is in the full state, so that the processor temporarily stops working, the tracking process of one period is completed after the control module reads the cache data and displays the cache result, and the cache tracking work of the next period is started again.
Further, when the switching unit generates the switching instruction to select the memory cache structure, the trace cache module caches the trace data packet through the memory cache structure, when the data cache inside the memory cache structure reaches a set threshold, the judging unit judges that the memory cache structure ends the data cache, and the requesting unit generates a stop request and transmits the stop request to the processor module to stop the processor module. The beneficial effects are that: when the memory cache structure is selected, because the memory cache structure has a fixed storage space, when the data cache in the memory cache structure reaches a set threshold value, the memory cache structure is judged to be in a full state, the request unit generates a stop request to enable the processor to stop working temporarily, and after the control module finishes reading the cache data and displays the cache result, the next cycle of cache tracking work is started again.
Further, the configuration instruction is determined according to a standard specification, and the standard specification is a specification of an open source instruction set architecture.
Further, the tracing method further comprises that after the control module finishes reading all the cache data in the trace cache module, the control module generates a control instruction to restart the processor module to transmit new trace data to the trace logic module.
The invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the method described above.
The invention further provides a terminal, which comprises a processor and a memory;
the processor is configured to execute the computer program stored in the memory to cause the terminal to perform the above-mentioned method.
Drawings
FIG. 1 is a schematic diagram of the structure of the tracking system according to an embodiment of the present invention;
FIG. 2 is a schematic overall flow chart of a tracking method according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating step S4 of the tracking method according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a processor tracking system, as shown in fig. 1, including:
the JTAG interface module 1 is used for being in communication connection with the control module 6 and analyzing JTAG instructions;
a processor module 2;
the tracking logic module 3 is embedded in the processor module 2, and is in communication connection with the processor module 2;
the tracking cache module 4 is in communication connection with the tracking logic module 3;
the JTAG interface module 1 is in communication connection with the trace logic module 3 and the trace cache module 4 through a system bus 5, respectively, where the trace logic module 3 is configured to package standard trace data in the processor module 2 into a trace data packet and output the trace data packet to the trace cache module 4, the trace cache module 4 is configured to cache the trace data packet, the JTAG interface module 1 further includes a translation unit 11, and the translation unit 11 is configured to translate an instruction from the control module 6 into a register access operation instruction or a storage access operation instruction on the system bus 5.
Wherein, JTAG (Joint Test Action Group) is an international standard Test protocol (IEEE 1149.1 compliant), and is mainly used for chip internal Test. Most advanced devices support JTAG protocols, such as DSP, FPGA devices and the like, and the standard JTAG interface is a 4-wire interface: TMS, TCK, TDI, TDO, mode select, clock, data input and data output lines, respectively.
In the tracking system, the JTAG interface module 1 in each chip is used as an interface to realize processor tracking, the normal operation of a tracking scheme is ensured, meanwhile, the universality of the whole system is greatly improved, no special interface is required to be connected independently, and the limitation on the use condition is greatly reduced.
When in use, the JTAG interface module 1 is responsible for analyzing a JTAG instruction from the control module 6, translating the JTAG instruction into a register access operation instruction or a storage access operation instruction on an APB bus in a chip through the translation unit 11, transmitting the instruction of the control module 6 to the trace cache module 4 and the trace logic module 3 through the system bus 5 after the instruction is translated into the register access operation instruction or the storage access operation instruction, after the configuration of the whole system is completed, the control module 6 generates a start instruction, the whole system starts to work, standard trace data in the processor module 2 are packaged into trace data packets through the trace logic module 3 and are transmitted to the trace cache module 4 for trace cache, the trace data are cached in the trace cache module 4, and after the control module 6 judges that the cache in the trace cache module 4 is finished, the control module 6 reads the data packet inside the trace cache module 4 through the JTAG interface module 1 and the system bus 5 and displays the final trace result, thereby completing the trace process of the processor data.
In some embodiments, the trace logic module 3 processes the trace data in the processor module 2 into the standard trace data through a trace specification, the trace specification being defined by the processor module 2, and since the trace data is processed into the standard trace data through the trace specification, the trace data in the entire processor module 2 has a uniform specification standard, which is more efficient in subsequent data trace processing and caching, and effectively reduces the occurrence of problems, and the trace specification is determined according to the processor module 2, and different trace specifications are selected according to different processor modules 2 to meet different use requirements.
In some embodiments, the trace cache module 4 is further communicatively connected with a determining unit 41 and a requesting unit 42, the determining unit 41 is configured to determine whether the data cache in the trace cache module 4 is in a full state, the requesting unit 42 is configured to issue a processor stop request, and an output of the requesting unit 42 is communicatively connected with the trace logic module 3.
In order to determine whether the trace data in the trace cache module 4 is cached or not stopped or ended, the determining unit 41 determines the data cache in the trace cache module 4 to determine whether the data cache in the trace cache module 4 is ended, and when the data cache in the trace cache module 4 is ended, the requesting unit 42 issues a stop request to temporarily stop the processor module 2, and the trace logic module 3 stops outputting the trace data packet to the trace cache module 4.
In some embodiments, the trace cache module 4 includes a ring cache structure 43, when the control module 1 turns off trace enable actively or the ring cache structure 43 encounters a breakpoint event, the determining unit 41 determines that the trace cache module ends data caching, and the requesting unit 42 issues a stop request to the processor module 2.
In some embodiments, the trace cache module 4 further includes a memory cache structure 44, when the amount of cached data in the memory cache structure 44 exceeds a set threshold, the determining unit 41 determines that the trace cache module 4 ends data caching, and the requesting unit 42 issues a stop request to the processor module 2.
The trace data packet is cached through two different types of caching modes, namely an annular caching structure 43 and a memory caching structure 44, different caching structures are selected when the trace data packet is used specifically to meet different caching requirements, meanwhile, the judging unit 41 judges the annular caching structure 43 and the memory caching structure 44 respectively, and when the judging unit 41 judges that the annular caching structure 43 and the memory caching structure 44 are in a full state, the requesting unit 42 sends a stop request to the trace logic module 3, so that the processor module 2 stops working to stop outputting trace data.
It should be noted that the ring buffer structure 43 and the memory buffer structure 44 adopt two different buffer structures, and the criteria for determining whether to end the buffering are different, and the ring buffer structure 43 or the memory buffer structure 44 is selected according to the type of the buffered data that is actually required to be selected.
Further, when the trace cache module 4 selects the ring cache structure 43 to perform trace data caching, due to the form of ring cache, the last segment of trace data may be stored circularly, or when the control module 2 actively turns off trace enable or the ring cache structure 43 encounters a breakpoint event, it may be determined that the ring cache structure 43 is in a state of ending data caching, at this time, the request unit 42 sends a stop request to the trace logic module 3, so that the processor module 2 stops working to stop outputting trace data, and at the same time, the control module 6 reads the cache data inside the trace cache module 4 through the JTAG module and the system bus 5 to obtain a final trace result.
Furthermore, when the trace cache module 4 selects the memory cache structure 44 to perform the trace data loop, since the memory cache structure 44 has a fixed capacity, that is, only a certain amount of trace data can be cached each time, and when the cache data in the memory cache structure 44 exceeds the set threshold, the determining unit 41 determines that the memory cache structure 44 ends the data caching, and the requesting unit 42 sends a stop request to the trace logic module 3, so that the processor module 2 stops working to stop outputting the trace data, and meanwhile, the control module 6 reads the cache data in the trace cache module 4 through the JTAG module and the system bus 5 to obtain a final trace result.
In some embodiments, the control module 6 further includes a switching unit 61, where the switching unit 61 is communicatively connected to the trace cache module 4 through the system bus 5 to switch and select any one of the ring cache structure 43 and the memory cache structure 44 to perform cache processing on the trace data packet.
In some embodiments, the control module 6 includes at least one of an upper computer and an embedded system.
The invention also provides a processor tracking method, as shown in fig. 2, including the following steps:
s1, the control module generates a configuration instruction, and the configuration instruction is converted into register access on the system bus through the JTAG interface module to configure the tracking logic module.
It should be noted that, because the configuration parameters of different processor core chips are different, after the processor and the chip which need to perform data tracking are determined, the control module 6 configures the tracking logic module 3 according to the standard specification of RISC-V, so that the tracking logic module 3 meets the use requirement.
And S2, the control module generates a starting instruction and starts the tracking function of the tracking logic module through the JTAG interface module and the system bus.
After the entire trace logic module 3 has been configured, the control module 6 generates and transmits control instructions to the trace logic module 3 via the JTAG interface module 1 and the system bus 5 to enable the trace function.
And S3, the tracking logic module packs the tracking data into a tracking data packet and outputs the tracking data packet to the tracking cache module.
It should be noted that, the trace logic module 3 packs the trace data into a trace data packet and transmits the trace data packet to the trace cache module 4 for trace data caching, and the packed trace data generally adopts trace data with a fixed standard specification, that is, the trace data is subjected to a standard specification, so as to obtain standard trace data, so as to ensure that the trace data output from the processor module 2 has a uniform specification, and improve data transmission efficiency.
And S4, the tracking caching module carries out tracking caching processing on the tracking data packet until stopping.
In some embodiments, as shown in fig. 3, the process of step S3 includes:
s41, the control module generates a switching instruction through a switching unit, and switches and selects any one of the ring cache structure and the memory cache structure in the tracking cache module for caching through a system bus;
s42, the tracking cache module caches the tracking data packet according to the selected cache structure;
s43, after the judgment unit judges that the cache structure in the tracking cache module finishes data caching, a stop request is generated by the request unit and transmitted to the processor module, and the processor module is stopped.
Further, when the switching unit 61 selects the ring-shaped cache structure 43 as the cache structure, due to the adoption of the form of the ring-shaped cache, when the ring-shaped cache structure 43 caches trace data, the ring-shaped cache structure 43 may store the trace data for a period of time in a circulating manner, or when the control module 2 actively turns off the trace enable or the ring-shaped cache structure 43 encounters a breakpoint event, for example, when the ring-shaped cache structure 43 starts to cache a new round of trace data, it is determined that data caching needs to be ended inside the ring-shaped cache structure 43, and at this time, the request unit 42 sends a stop request, and the processor module 2 temporarily stops working through the trace logic module 3.
Further, when the switching unit 61 selects the memory buffer structure 44 as the buffer structure, since the storage capacity of the memory buffer structure 44 is fixed, when the trace data transmitted by the trace logic module 3 reaches a certain amount, the internal of the memory buffer structure 44 approaches the set threshold, at this time, the determining unit 1 determines that the trace buffer module 4 needs to stop the data buffering, and then the requesting unit 42 generates the stop request, so that the processor module 2 stops outputting the trace data.
And S5, the control module reads all data in the tracking cache module through the system bus and displays the tracking result.
In some embodiments, when the switching unit 61 generates the switching instruction to select the ring cache structure 43, the trace cache module 4 caches trace data packets through the ring cache structure 43, when the control module 2 actively turns off trace enable or the ring cache structure 43 encounters a breakpoint event, for example, when the ring cache structure 43 starts caching a new round of trace data, the determining unit 41 determines that the ring cache structure 43 needs to end data caching, and the requesting unit 42 generates and transmits a stop request to the processor module 2 to stop the processor module 2.
In some embodiments, when the switch unit 61 generates the switch instruction to select the memory cache structure 44, the trace cache module 4 caches the trace data packet through the memory cache structure 44, when the data cache inside the memory cache structure 44 reaches a set threshold, the determining unit 41 determines that the memory cache structure 43 is in a full state, the requesting unit 42 generates a stop request and transmits the stop request to the processor module 2, and the processor module 2 is stopped.
It should be noted that the setting threshold of the memory cache structure 44 is set by the control module 6, and may be completely the same as the storage capacity of the memory cache structure 44, or slightly smaller than the storage capacity of the memory cache structure 44, and is selected according to specific situations.
In some embodiments, the configuration instructions are determined according to a standard specification, which is a specification of the open source instruction set architecture, RISC-V.
In some embodiments, the tracking method further includes that after the control module 6 finishes reading all the cache data in the tracking cache module 4, the control module 6 generates a control instruction to restart the processor module 2 to transmit new tracking data to the tracking logic module 3, after the control module 6 finishes reading the cache data in the tracking cache module 4, the control module 6 obtains a tracking result and displays the tracking result, and then the control module 6 generates a control instruction to restart the processor module 2, so that the processor module 2 outputs the tracking data to the tracking logic module 3 again, and the tracking logic module 3 packs and outputs the tracking data to the tracking cache module 4 to continue tracking data caching.
Preferably, the control module 6 in this embodiment adopts an upper computer, and the upper computer reads out the trace data cached in the trace cache module 4 through the JTAG interface module 1 and the system bus 5 and analyzes and displays the trace result.
Further, the control module 6 further includes any one of a computer, a CPU, and a controller, and is selected according to actual conditions, and the selection and use of the control module is not particularly limited in the present invention.
The invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the method described above.
The invention further provides a terminal, which comprises a processor and a memory;
the processor is configured to execute the computer program stored in the memory to cause the terminal to perform the above-mentioned method.
The memory is for storing a computer program.
Preferably, the memory comprises: various media that can store program codes, such as ROM, RAM, magnetic disk, U-disk, memory card, or optical disk.
The processor is connected with the memory and is used for executing the computer program stored in the memory so as to enable the terminal to execute the method.
Preferably, the Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware component.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (16)
1. A processor tracking system, comprising:
the JTAG interface module is used for being in communication connection with the control module and analyzing JTAG instructions;
a processor module;
a trace logic module embedded within the processor module and communicatively coupled to the processor module;
the tracking cache module is in communication connection with the tracking logic module;
the JTAG interface module is respectively in communication connection with the tracking logic module and the tracking cache module through a system bus, the tracking logic module is used for packaging standard tracking data in the processor module into tracking data packets and outputting the tracking data packets to the tracking cache module, and the tracking cache module is used for caching the tracking data packets.
2. The processor tracking system of claim 1, wherein the tracking logic module processes the tracking data within the processor module into the standard tracking data via a tracking specification, the tracking specification defined by the processor module.
3. The processor tracing system according to claim 1, wherein the trace cache module is communicatively connected with a determining unit and a requesting unit, the determining unit is configured to determine whether the trace cache module ends data caching, an output of the requesting unit is communicatively connected with the trace logic module, and the requesting unit is configured to issue a stop request.
4. The processor tracing system according to claim 3, wherein the trace cache module comprises a ring cache structure, when the control module actively turns off trace enable or the ring cache structure encounters a breakpoint event, the determining unit determines that the trace cache module ends data caching, and the requesting unit issues a stop request to the processor module.
5. The processor tracking system according to claim 3 or 4, wherein the tracking cache module further comprises a memory cache structure, when the amount of cache data in the memory cache structure exceeds a set threshold, the determining unit determines that the tracking cache module ends data caching, and the requesting unit sends a stop request to the processor module.
6. The processor tracking system according to claim 4, wherein the control module further comprises a switching unit, the switching unit is communicatively connected to the tracking buffer module through the system bus to switch and select any one of a ring buffer structure and a memory buffer structure to perform the buffer processing on the tracking data packet.
7. The processor tracking system of claim 1, wherein the JTAG interface module further comprises a translation unit to translate instructions from the control module into register access operation instructions or memory access operation instructions on the system bus.
8. The processor tracking system of claim 1, wherein the control module comprises at least one of an upper computer and an embedded system.
9. A processor tracking method, comprising the steps of:
s1, the control module generates a configuration instruction, the configuration instruction is converted into register access on a system bus through the JTAG interface module, and the tracking logic module is configured;
s2, the control module generates a start instruction and starts the tracking function of the tracking logic module through the JTAG interface module and the system bus;
s3, the tracking logic module packs the tracking data into a tracking data packet and outputs the tracking data packet to the tracking cache module;
s4, the tracking cache module performs tracking cache processing on the tracking data packet until stopping;
and S5, the control module reads all data in the tracking cache module through the system bus and displays the tracking result.
10. The processor tracing method according to claim 9, wherein the process of step S4 comprises:
s41, the control module generates a switching instruction through a switching unit, and switches and selects any one of the ring cache structure and the memory cache structure in the tracking cache module for caching through a system bus;
s42, the tracking cache module caches the tracking data packet according to the selected cache structure;
s43, after the judgment unit judges that the cache structure in the tracking cache module finishes data caching, a stop request is generated by the request unit and transmitted to the processor module, and the processor module is stopped.
11. The processor tracing method according to claim 10, wherein when the switching unit generates the switching instruction to select the ring cache structure, the trace cache module caches trace data packets through the ring cache structure, when the control module actively turns off trace enable or the ring cache structure encounters a breakpoint event, the determining unit determines that the ring cache structure ends data caching, and the requesting unit generates a stop request and transmits the stop request to the processor module to stop the processor module.
12. The processor tracing method according to claim 10, wherein when the switch unit generates the switch instruction to select the memory cache structure, the trace cache module caches the trace data packet through the memory cache structure, when a data cache inside the memory cache structure reaches a set threshold, the determination unit determines that the memory cache structure ends the data cache, and the request unit generates a stop request and transmits the stop request to the processor module to stop the processor module.
13. The processor tracing method of claim 9, wherein said configuration instructions are determined according to a standard specification, said standard specification being a specification of an open source instruction set architecture.
14. The processor tracing method of claim 9, wherein the tracing method further comprises after the control module reads all the cache data in the trace cache module, the control module generating a control instruction to restart the processor module to transmit new trace data to the trace logic module.
15. A storage medium on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 9 to 14.
16. A terminal comprising a processor and a memory;
the processor is configured to execute the computer program stored by the memory to cause the terminal to perform the method according to any one of claims 9 to 14.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1851668A (en) * | 2006-06-01 | 2006-10-25 | 北京天碁科技有限公司 | Sheet system chip, sheet system chip tracking debug system and method |
| CN101154184A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | JTAG debugging method for microcontroller |
| CN101187895A (en) * | 2006-11-17 | 2008-05-28 | 中兴通讯股份有限公司 | Single board control method |
| CN101751327A (en) * | 2008-12-04 | 2010-06-23 | 北京中电华大电子设计有限责任公司 | Method for tracing embedded processor debugging |
| CN102880568A (en) * | 2012-09-18 | 2013-01-16 | 杭州中天微系统有限公司 | State tracking device for multi-core processor |
| JP2013015985A (en) * | 2011-07-03 | 2013-01-24 | Masao Kaizuka | Soc device capable of execution trace dumping of all processor cores of multi-core processor |
| CN103262425A (en) * | 2010-12-17 | 2013-08-21 | 华为技术有限公司 | System and method for contention-free memory access |
| CN104461931A (en) * | 2014-08-18 | 2015-03-25 | 记忆科技(深圳)有限公司 | Method for output processing of trace logs of multi-kernel storage device and multi-kernel environment |
| CN104461796A (en) * | 2013-09-17 | 2015-03-25 | 上海华虹集成电路有限责任公司 | JTAG (joint test action group) debugging module and method for embedded 8051CPU (central processing unit) |
| CN107783874A (en) * | 2016-08-26 | 2018-03-09 | 华为技术有限公司 | JTAG debugging apparatus and JTAG adjustment methods |
| CN109426594A (en) * | 2017-08-25 | 2019-03-05 | 深圳市中兴微电子技术有限公司 | A kind of chip debugging apparatus, method and computer readable storage medium |
| CN111832016A (en) * | 2019-04-16 | 2020-10-27 | 奥传索克技术有限公司 | Tracing instruction execution |
-
2020
- 2020-12-18 CN CN202011510094.9A patent/CN112486752A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1851668A (en) * | 2006-06-01 | 2006-10-25 | 北京天碁科技有限公司 | Sheet system chip, sheet system chip tracking debug system and method |
| CN101154184A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | JTAG debugging method for microcontroller |
| CN101187895A (en) * | 2006-11-17 | 2008-05-28 | 中兴通讯股份有限公司 | Single board control method |
| CN101751327A (en) * | 2008-12-04 | 2010-06-23 | 北京中电华大电子设计有限责任公司 | Method for tracing embedded processor debugging |
| CN103262425A (en) * | 2010-12-17 | 2013-08-21 | 华为技术有限公司 | System and method for contention-free memory access |
| JP2013015985A (en) * | 2011-07-03 | 2013-01-24 | Masao Kaizuka | Soc device capable of execution trace dumping of all processor cores of multi-core processor |
| CN102880568A (en) * | 2012-09-18 | 2013-01-16 | 杭州中天微系统有限公司 | State tracking device for multi-core processor |
| CN104461796A (en) * | 2013-09-17 | 2015-03-25 | 上海华虹集成电路有限责任公司 | JTAG (joint test action group) debugging module and method for embedded 8051CPU (central processing unit) |
| CN104461931A (en) * | 2014-08-18 | 2015-03-25 | 记忆科技(深圳)有限公司 | Method for output processing of trace logs of multi-kernel storage device and multi-kernel environment |
| CN107783874A (en) * | 2016-08-26 | 2018-03-09 | 华为技术有限公司 | JTAG debugging apparatus and JTAG adjustment methods |
| CN109426594A (en) * | 2017-08-25 | 2019-03-05 | 深圳市中兴微电子技术有限公司 | A kind of chip debugging apparatus, method and computer readable storage medium |
| CN111832016A (en) * | 2019-04-16 | 2020-10-27 | 奥传索克技术有限公司 | Tracing instruction execution |
Non-Patent Citations (2)
| Title |
|---|
| 姚霁: "一种基于JTAG的片内调试系统设计", 《现代电子技术》 * |
| 苏嘉玮，关宁，刘强，孙国飞，王欢: "基于RISC_V微处理器的软硬件调试方法研究与实现", 《航天标准化》 * |
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