CN104317747A - Data caching and sending device and method of network receiver - Google Patents
Data caching and sending device and method of network receiver Download PDFInfo
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- CN104317747A CN104317747A CN201410525557.7A CN201410525557A CN104317747A CN 104317747 A CN104317747 A CN 104317747A CN 201410525557 A CN201410525557 A CN 201410525557A CN 104317747 A CN104317747 A CN 104317747A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
A data caching and sending device of a network receiver comprises a cache module formed by an FPGA (field programmable gate array) and a DDR3 storage, and a TCP (transmission control protocol) communication module formed by an on-chip system and in-machine software; the FPGA is connected with the DDR3 storage by an interface circuit and is connected with the on-chip system by an external system bus; the on-chip system is provided with an Ethernet interface and can send data to a network. The FPGA chip of the receiver is connected with the DDR3 storage in a hanging mode, the data can be directly written into the DDR3 storage by the FPGA after being subjected to medium frequency treatment, so the receiver can collect at high speed continuously. The FPGA provides an FIFO (first in first out) interface for the on-chip system to support asynchronous data transfer, a data channel in the TCP communication module is specially adopted for data transmission, and the aim that the data flow is not interrupted in the whole transmission process is ensured.
Description
Technical field
The invention belongs to radio monitoring field, especially a kind of data buffer storage of grid receiver and the method for work of dispensing device and this device.
Background technology
Gridding has been an important development direction of radio monitoring, and the receiver of gridding is no longer isolated list station setting, but as a sensor, for monitoring system provides the ability of frequency spectrum perception.Each receiver is interconnected by network, measured data be all sent to far-end server compare merge and process.Because gridding needs to lay a large amount of receivers in monitored area, therefore receiver must be miniaturization, low cost and easily installation, and table set is not taken into account.In addition, compared to traditional receiver, gridding emphasizes that receiver is to the local cache of data and network capacity more.In the radio monitoring system of gridding, the data that receiver gathers need to be sent to long-range workstation and process.Under the network bandwidth limited at present, when high speed acquisition, data often can not be transmitted in time, thus need receiver data cached.If use the internal memory that receiver built-in type system carries, its writing speed and capacity all do not reach requirement.In data transmission, require grid receiver send data time can not interrupt data stream, guarantee data stream arrive distance host time and acquired original time be consistent.
The receiver of current miniaturization, its numerical portion adopts the framework of FPGA+ARM, carries out data transmission between the two by the external system bus of ARM.To FPGA programming realization Digital IF Processing, often process frame data, FPGA sends interrupt request notice CPU and data is read away.Data, in interruption routine, copy to internal memory from FPGA by CPU, and then control FPGA starts the collection of next frame, and the Frame copied in internal memory carries out follow-up process by other modules.
When program control, the mutual application layer protocol based on remote procedure call (RPC) of distance host and receiver.In this mode, the response program control command that receiver is passive.When needing the image data obtaining receiver, distance host sends a query statement to receiver, instruction is construed to a process of far call receiver by RPC agreement, and receiver sends measurement result in the process, and distance host can continue to perform next step operation.
Summary of the invention
Object of the present invention is exactly the caching function lacking high-speed high capacity for existing grid receiver, high speed acquisition cannot be realized, FPGA want waiting for CPU run through data after just can carry out subsequent treatment, the discontinuous deficiency of data acquisition, proposes a kind of data buffer storage of grid receiver and dispensing device and method.
The present invention adopts following technical scheme:
A kind of data buffer storage of grid receiver and dispensing device, comprise data cache module and TCP communication module, described cache module comprises FPGA and DDR3 storer, described FPGA is connected with DDR3 storer by interface circuit, and be connected with the SOC (system on a chip) in TCP communication module by external system bus, described TCP communication module is made up of SOC (system on a chip) and software in machine, and described SOC (system on a chip) is provided with Ethernet interface.
Preferably, described interface circuit is made up of control line, data path and clock line.
Preferably, described FPGA is provided with the fifo interface reading DDR3 memory data for described SOC (system on a chip).
Preferably, described TCP communication module comprises administrative unit, control channel and data channel three part.
Preferably, the administrative unit of described TCP communication module comprises audiomonitor, message response device, channel map and passage factory.
Preferably, the control channel of described TCP communication module comprises instruction separation vessel and accurate data channel chained list.
Preferably, the data channel of described TCP communication module comprises a transmission agency.
A kind of data buffer storage of grid receiver and sending method, adopt the asynchronous read and write of DDR3 storer, drive the hardware control interface as the moving data of software in machine by the stream of FPGA, adopt TCP communication module to carry out data transmission, data buffer storage and process of transmitting mainly comprise three phases:
Buffer memory, the data that grid receiver receives are write in DDR3 storer by FPGA carries out buffer memory, and utilizes the free time of interface bus that data are transported to fifo interface by FPGA;
Move, in described software in machine, have a frequency spectrum data to move thread and specially Frame is moved, these thread execution following steps:
Step one, judges whether sweep parameter list is empty, for sky continues to perform step one with regard to dormancy 50 milliseconds, otherwise takes out list head node;
Step 2, counts according to the fast fourier transform in node parameter information on process heap, creates the buffer zone of corresponding size;
Step 3, with this buffer zone address and size for parameter, by the data-moving function that DeviceIoControl () function call stream drives, by the latter data-moving in FPGA FIFO in buffer zone, wherein the DeviceIoControl () api function that is operating system;
Step 4, carries out Logarithm conversion and compensating for frequency response to measurement data, and makes the head of this frame, and head comprises frequency, fast fourier transform is counted, timestamp information;
Step 5, with the socket handle of the data channel associated at present for parameter, is sent to TCP communication module the data block packing of two in step 3;
Step 6, if TCP communication module receives, then performs step one, otherwise continues to attempt step 5;
Transmission, the transmission of data is realized by the TCP communication module of receiver, and the transmitting procedure of data comprises the following steps:
Step a, request for data connects, distance host is for receiving data, first the control channel by having set up sends " port " instruction to receiver, this instruction proposes the application of setting up data cube computation to receiver, contain the tcp port number that distance host connects for this data channel in command frame, after receiver receives this instruction, through instruction separation, instructions parse and distribution, finally self be responsible for response by TCP communication module.In response process, first TCP communication module entrusts passage factory to create out a data channel example do not connected, and this passage is added to the accurate data channel chained list of control channel, then sends response by control channel to distance host;
Step b, connects, and distance host, after receiving response, just initiates connection request with port numbers when applying for connection to receiver; After receiver receives request, find the accurate data channel consistent with this connection request port numbers, for this accurate data channel connects;
Step c, send, the internal module of receiver always sends data by data channel to distance host.During transmission, internal module with the socket handle of data channel, data block be cited as parameter, to TCP communication module propose send request, by TCP communication module in charge, data block is sent to network.
The detailed process sent is controlled by TCP communication module, first TCP communication module is searched channel map according to socket handle and is found corresponding data channel, then just data channel is given the transmission task delegation of data block, data channel is after judging that channel status is normal, just transmission task delegation is acted on behalf of to transmission, send the real details that agency achieves transmission;
Send the buffer circle that agency has a 64k byte, buffer circle is abstracted into end to end, adopts critical section protection, can multi-thread access.Under normal circumstances, write data run, in the context of data acquisition thread, sends data run in the context of main thread.Data first-in first-out in buffering, the space reusable edible of buffering;
Data block in collecting thread send request on commission give send agency after, send agency first the size of data block compared with the free space of loop buffer.If free space cannot hold this data block, just refuse this request; Otherwise just data block is added to the afterbody of data in buffering, upgrade data trailer mark, and deliver a data transmission message to window.
This message, through the distribution of main thread, finally can be received by data channel.After data channel Preliminary Analysis message parameter, entrust and send agency's continuation response message.Sending agency can data in three iteration in transmission loop buffer as much as possible, if loop buffer is empty or send and blocked in an iterative process, all can drop by the wayside.After iteration completes, if loop buffer still has data not send, then deliver data to window and send message, send when waiting until next response message.
The present invention has following beneficial effect:
1, in cache module, mount DDR3 storer, data directly can write DDR3 storer by FPGA after intermediate frequency process, make receiver can high speed acquisition.
2, the read-write of FPGA Time-sharing control DDR3 storer, provide fifo interface for CPU accesses DDR3 storer, CPU can not cause the interruption of data acquisition when reading data.
3, adopt special TCP tunnel data, data stream and control flow check be separated, data stream can high-speed and continuous be sent to distance host.
4, the composition structure of grid receiver TCP communication module, is divided into administrative unit, control channel and data channel three part, and receiver can be simultaneously mutual with multiple distance host, and dissimilar measurement data is by multiple data channel transmitted in parallel.
5, by sending the mode of agency, outwardly shield on the one hand the complicacy that data send, on the other hand buffer circle design and to ensure that data send by the process of transmitting of message-driven efficient.
Accompanying drawing explanation
Fig. 1 is grid receiver internal frame diagram;
Fig. 2 is the coupling part block diagram of DDR3 storer and FPGA;
Fig. 3 is the TCP communication modular structure block diagram of receiver.
Embodiment
Below in conjunction with the drawings and specific embodiments, the specific embodiment of the present invention is described further:
Specific term is introduced:
FPGA: field programmable gate array, DDR3: third generation double data rate Synchronous Dynamic Random Access Memory, FIFO: First Input First Output, TCP: transmission control protocol.
As shown in Figure 1, a kind of data buffer storage of grid receiver and dispensing device, comprise data cache module and TCP communication module, cache module comprises FPGA and DDR3 storer, described FPGA is connected with DDR3 storer by interface circuit, and is connected with the SOC (system on a chip) in TCP communication module by external system bus, and described TCP communication module is made up of SOC (system on a chip) and software in machine, described SOC (system on a chip) is provided with Ethernet interface, data can be sent to network.Described FPGA is connected with DDR3 storer by interface circuit, the memory capacity of DDR3 storer is 4GB in the present invention, SOC (system on a chip) realizes communicating by TCP communication module with distance host, the CPU of SOC (system on a chip) adopts the processor of ARM Cortex-A8 core, dominant frequency 800MHz, have 100,000,000 LAN network interfaces, external system bus has the data line of 16 and the address wire of 24, clock frequency 133MHz.Receiver adopts Window Embedded Compact 7 embedded OS.
As shown in Figure 2, the interface circuit of described connection FPGA and DDR3 storer is made up of control line, data path and clock line.
Described FPGA is provided with the fifo interface reading DDR3 memory data for described SOC (system on a chip), FPGA inside generates IP kernel by Xilinx FPGA memory interface maker, IP kernel comprises Physical layer, controller and user interface layer, and Physical layer is directly connected with DDR3 storer.User interface layer for receive user control interface and send over write address, write data and read address.Controller is the core of whole IP kernel, is responsible for the order that process user interface layer sends, produces the order such as activation, reading and writing, precharge, self-refresh of meeting consumers' demand.On the basis of this IP kernel, the design of FPGA control DDR3 memory portion is simplified greatly, and programming personnel only needs to carry out read-write operation according to the timing requirements of IP kernel user operation end.Because DDR3 storer can not be read not only but also write simultaneously, FPGA needs to adopt timesharing strategy, and read-write operation is separated.FPGA inside adopts line production, while generation next frame I/Q data, quick Fourier transformation computation and the write operation of DDR3 storer are carried out to previous frame, according to the requirement of seamless collection, the time of computing and write is bound to be less than rise time of I/Q data frame, within this mistiming, the interface bus of DDR3 storer is idle, and thus FPGA can utilize this mistiming the data in DDR3 storer to be transported in FIFO.
As shown in Figure 3, described TCP communication module comprises administrative unit, control channel and data channel three part.
The administrative unit of described TCP communication module comprises audiomonitor, message response device, channel map and passage factory, wherein the connection request of listener process 8080 port, if allow to connect, just utilizes passage factory to create passage object.Message response device be used for response to network event, when window can notify TCP communication module after receiving network event messages, then by message response device message distribution to correspondence passage; The corresponding relation of channel map recording channel socket handle and passage object, each control channel of having set up and data channel all record in the table, can find rapidly its passage object by socket handle.Passage factory is responsible for the example creating control channel and data channel.
The control channel of described TCP communication module comprises instruction separation vessel and accurate data channel chained list.Instruction separation vessel processes the data stream receiving buffering, data stream is divided into command frame one by one, is then sent to the response of each internal module of receiver by the instruction distribution module of receiver.Control channel also comprises an accurate data channel chained list, preserves those and is under the jurisdiction of this control channel, but the data channel not yet really connected.
The data channel of described TCP communication module comprises one and sends agency, and this agency, after accepting the data of receiver internal module for transmission, is drive with windows messaging, asynchronously data is sent to distance host.
A kind of data buffer storage of grid receiver and sending method, adopt the asynchronous read and write of DDR3 storer, drive the hardware control interface as the moving data of software in machine by the stream of FPGA, adopt TCP communication module to carry out data transmission, data buffer storage and process of transmitting mainly comprise three phases:
Buffer memory, the data that grid receiver receives are write in DDR3 storer by FPGA carries out buffer memory, and utilizes the free time of interface bus that data are transported to fifo interface by FPGA;
Move, in described software in machine, have a frequency spectrum data to move thread and specially Frame is moved, these thread execution following steps:
Step one, judges whether sweep parameter list is empty, for sky continues to perform step one with regard to dormancy 50 milliseconds, otherwise takes out list head node;
Step 2, counts according to the fast fourier transform in node parameter information on process heap, creates the buffer zone of corresponding size;
Step 3, with this buffer zone address and size for parameter, by the data-moving function that DeviceIoControl () function call stream drives, by the latter data-moving in FPGA FIFO in buffer zone, wherein the DeviceIoControl () api function that is operating system;
Step 4, carries out Logarithm conversion and compensating for frequency response to measurement data, and makes the head of this frame, and head comprises frequency, fast fourier transform is counted, timestamp information;
Step 5, with the socket handle of the data channel associated at present for parameter, is sent to TCP communication module the data block packing of two in step 3;
Step 6, if TCP communication module receives, then performs step one, otherwise continues to attempt step 5;
Transmission, the transmission of data is realized by the TCP communication module of receiver, and the transmitting procedure of data comprises the following steps:
Step a, request for data connects, distance host is for receiving data, first the control channel by having set up sends " port " instruction to receiver, this instruction proposes the application of setting up data cube computation to receiver, contain the tcp port number that distance host connects for this data channel in command frame;
Step b, connects, and distance host, after receiving response, just initiates connection request with port numbers when applying for connection to receiver; After receiver receives request, find the accurate data channel consistent with this connection request port numbers, for this accurate data channel connects.
Step c, send, the internal module of receiver always sends data by data channel to distance host.During transmission, internal module with the socket handle of data channel, data block be cited as parameter, to TCP communication module propose send request, by TCP communication module in charge, data block is sent to network.
The detailed process sent is controlled by TCP communication module, first TCP communication module is searched channel map according to socket handle and is found corresponding data channel, then just data channel is given the transmission task delegation of data block, data channel is after judging that channel status is normal, just transmission task delegation is acted on behalf of to transmission, send the real details that agency achieves transmission.
Send the buffer circle that agency has a 64k byte, buffer circle is abstracted into end to end, adopts critical section protection, can multi-thread access.Under normal circumstances, write data run, in the context of data acquisition thread, sends data run in the context of main thread.Data first-in first-out in buffering, the space reusable edible of buffering.
Data block in collecting thread send request on commission give send agency after, send agency first the size of data block compared with the free space of loop buffer.If free space cannot hold this data block, just refuse this request; Otherwise just data block is added to the afterbody of data in buffering, upgrade data trailer mark, and deliver a data transmission message to window.
This message, through the distribution of main thread, finally can be received by data channel.After data channel Preliminary Analysis message parameter, entrust and send agency's continuation response message.Sending agency can data in three iteration in transmission loop buffer as much as possible, if loop buffer is empty or send and blocked in an iterative process, all can drop by the wayside.After iteration completes, if loop buffer still has data not send, then deliver data to window and send message, send when waiting until next response message.
Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited in above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement also should belong to protection scope of the present invention.
Claims (8)
1. the data buffer storage of a grid receiver and dispensing device, comprise data cache module and TCP communication module, it is characterized in that, described cache module comprises FPGA and DDR3 storer, described FPGA is connected with DDR3 storer by interface circuit, and be connected with the SOC (system on a chip) in TCP communication module by external system bus, described TCP communication module is made up of SOC (system on a chip) and software in machine, and described SOC (system on a chip) is provided with Ethernet interface.
2. the data buffer storage of a kind of grid receiver as claimed in claim 1 and dispensing device, it is characterized in that, described interface circuit is made up of control line, data path and clock line.
3. the data buffer storage of a kind of grid receiver as claimed in claim 1 and dispensing device, is characterized in that, described FPGA is provided with the fifo interface reading DDR3 memory data for described SOC (system on a chip).
4. the data buffer storage of a kind of grid receiver as claimed in claim 1 and dispensing device, is characterized in that, described TCP communication module comprises administrative unit, control channel and data channel three part.
5. the data buffer storage of a kind of grid receiver as claimed in claim 4 and dispensing device, it is characterized in that, the administrative unit of described TCP communication module comprises audiomonitor, message response device, channel map and passage factory.
6. the data buffer storage of a kind of grid receiver as claimed in claim 4 and dispensing device, it is characterized in that, the control channel of described TCP communication module comprises instruction separation vessel and accurate data channel chained list.
7. the data buffer storage of a kind of grid receiver as claimed in claim 4 and dispensing device, is characterized in that, the data channel of described TCP communication module comprises one and sends agency.
8. the data buffer storage of a grid receiver and sending method, adopt the asynchronous read and write of DDR3 storer, the hardware control interface as the moving data of software in machine is driven by the stream of FPGA, TCP communication module is adopted to carry out data transmission, it is characterized in that, data buffer storage and process of transmitting mainly comprise three phases:
Buffer memory, the data that grid receiver receives are write in DDR3 storer by FPGA carries out buffer memory, and utilizes the free time of interface bus that data are transported to fifo interface by FPGA;
Move, in described software in machine, have a frequency spectrum data to move thread and specially Frame is moved, these thread execution following steps:
Step one, judges whether sweep parameter list is empty, for sky continues to perform step one with regard to dormancy 50 milliseconds, otherwise takes out list head node;
Step 2, counts according to the fast fourier transform in node parameter information on process heap, creates the buffer zone of corresponding size;
Step 3, with this buffer zone address and size for parameter, the data-moving function driven by the system API Calls stream of DeviceIoControl (), by the latter data-moving in FPGA FIFO in buffer zone;
Step 4, carries out Logarithm conversion and compensating for frequency response to measurement data, and makes the head of this frame, and head comprises frequency, fast fourier transform is counted, timestamp information;
Step 5, with the socket handle of the data channel associated at present for parameter, is sent to TCP communication module the data block packing of two in step 3;
Step 6, if TCP communication module receives, then performs step one, otherwise continues to attempt step 5;
Transmission, the transmission of data is realized by the TCP communication module of receiver, and the transmitting procedure of data comprises the following steps:
Step a, request for data connects, distance host is for receiving data, first the control channel by having set up sends " port " instruction to receiver, this instruction proposes the application of setting up data cube computation to receiver, contain the tcp port number that distance host connects for this data channel in command frame;
Step b, connects, and distance host, after receiving response, just initiates connection request with port numbers when applying for connection to receiver; After receiver receives request, find the accurate data channel consistent with this connection request port numbers, for this accurate data channel connects;
Step c, send, the internal module of receiver always sends data by data channel to distance host.During transmission, internal module with the socket handle of data channel, data block be cited as parameter, to TCP communication module propose send request, by TCP communication module in charge, data block is sent to network.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603172A (en) * | 2016-11-24 | 2017-04-26 | 中国电子科技集团公司第四十研究所 | Time stamp data time sharing reading-writing method applied to radio monitoring receiver |
| CN106788919A (en) * | 2016-11-24 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | Self adaptation cut position I/Q data real-time monitoring implementation method in a kind of gridding receiver |
| CN109547355A (en) * | 2018-10-17 | 2019-03-29 | 中国电子科技集团公司第四十研究所 | A kind of storing and resolving device and method based on ten thousand mbit ethernet mouth receivers |
| CN113434455A (en) * | 2021-06-22 | 2021-09-24 | 中国电子科技集团公司第十四研究所 | Optical fiber interface data cache management method based on FPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102401871A (en) * | 2011-11-29 | 2012-04-04 | 安徽继远电网技术有限责任公司 | Failure message integrated device based on FPGA and ARM hardware platform |
| CN103218323A (en) * | 2013-03-25 | 2013-07-24 | 广东工业大学 | High-speed data acquisition and transmission device |
| CN103324124A (en) * | 2013-06-28 | 2013-09-25 | 上海宽岱电讯科技发展有限公司 | Data collecting system |
-
2014
- 2014-10-09 CN CN201410525557.7A patent/CN104317747B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102401871A (en) * | 2011-11-29 | 2012-04-04 | 安徽继远电网技术有限责任公司 | Failure message integrated device based on FPGA and ARM hardware platform |
| CN103218323A (en) * | 2013-03-25 | 2013-07-24 | 广东工业大学 | High-speed data acquisition and transmission device |
| CN103324124A (en) * | 2013-06-28 | 2013-09-25 | 上海宽岱电讯科技发展有限公司 | Data collecting system |
Non-Patent Citations (1)
| Title |
|---|
| 钟观水: "基于FPGA的高速数据采集系统设计", 《中国优秀硕士学位论文全文数据库信息科技辑（月刊）》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106603172A (en) * | 2016-11-24 | 2017-04-26 | 中国电子科技集团公司第四十研究所 | Time stamp data time sharing reading-writing method applied to radio monitoring receiver |
| CN106788919A (en) * | 2016-11-24 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | Self adaptation cut position I/Q data real-time monitoring implementation method in a kind of gridding receiver |
| CN109547355A (en) * | 2018-10-17 | 2019-03-29 | 中国电子科技集团公司第四十研究所 | A kind of storing and resolving device and method based on ten thousand mbit ethernet mouth receivers |
| CN113434455A (en) * | 2021-06-22 | 2021-09-24 | 中国电子科技集团公司第十四研究所 | Optical fiber interface data cache management method based on FPGA |
| CN113434455B (en) * | 2021-06-22 | 2023-10-24 | 中国电子科技集团公司第十四研究所 | Optical fiber interface data cache management method based on FPGA |
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Effective date of registration: 20190225 Address after: 266555 Xiangjiang 98, Huangdao District, Qingdao City, Shandong Province Patentee after: China Electronics Technology Instrument and Meter Co., Ltd. Address before: 266555 No. 98 Xiangjiang Road, Qingdao economic and Technological Development Zone, Shandong Patentee before: The 41st Institute of CETC |
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Address after: 266555 Xiangjiang 98, Huangdao District, Qingdao City, Shandong Province Patentee after: CLP kesiyi Technology Co.,Ltd. Address before: 266555 Xiangjiang 98, Huangdao District, Qingdao City, Shandong Province Patentee before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |
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