CN104317747B - A kind of data buffer storage of grid receiver and dispensing device and method - Google Patents
A kind of data buffer storage of grid receiver and dispensing device and method Download PDFInfo
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- CN104317747B CN104317747B CN201410525557.7A CN201410525557A CN104317747B CN 104317747 B CN104317747 B CN 104317747B CN 201410525557 A CN201410525557 A CN 201410525557A CN 104317747 B CN104317747 B CN 104317747B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
A kind of data buffer storage of grid receiver and dispensing device, including the cache module being made up of FPGA and DDR3 memorizer, the TCP communication module of SOC(system on a chip) and the composition of software in machine.Wherein FPGA is connected with DDR3 memorizer by interface circuit, and is connected with SOC(system on a chip) by external system bus, and SOC(system on a chip) has Ethernet interface, can transmit data to network.The present invention is that the fpga chip of receiver mounts DDR3 memorizer, and data directly can write DDR3 memorizer so that receiver can be with continual high speed acquisition by FPGA after IF process.FPGA to SOC(system on a chip) provide fifo interface to support that asynchronous data is moved, in TCP communication module adopt data channel dedicated for data transmission it is ensured that data flow in whole transmission process all without interruption.
Description
Technical field
The invention belongs to radio monitoring field, especially a kind of data buffer storage of grid receiver and dispensing device and should
The method of work of device.
Background technology
Gridding has been an important development direction of radio monitoring, and the receiver of gridding is no longer isolated list station
Setting, but as a sensor, provide the ability of frequency spectrum perception for monitoring system.It is mutual that each receiver passes through network
Connection, measured data be all sent to far-end server compare fusion and process.Because gridding needs in monitoring section
Substantial amounts of receiver is laid, therefore receiver must be miniaturization, inexpensive and easy to install, and table set is not being examined in domain
The row of worry.Additionally, compared to traditional receiver, gridding more emphasizes receiver to the local cache of data and network transmission
Ability.In the radio monitoring system of gridding, data that receiver is gathered needs to be sent to long-range work station and carries out
Process.Under the network bandwidth limited at present, when high speed acquisition, data tends not to be transmitted in time, so that connecing
Receipts machine is data cached.Will if the internal memory being carried using receiver built-in type system, its writing speed and capacity are not all reached
Ask.In data transmission it is desirable to grid receiver can not interrupt data flow when sending data it is ensured that data flow reaches remotely
It is consistent when during main frame with acquired original.
The receiver of miniaturization at present, its numerical portion adopts the framework of FPGA+ARM, between the two by the outside of ARM
System bus carries out data transmission.To FPGA programming realization Digital IF Processing, frame data are often processed, FPGA sends interruption
Request notifies CPU to read to walk by data.CPU, in interruption routine, data is copied to internal memory from FPGA, then controls FPGA to open
The collection of dynamic next frame, the Frame copying in internal memory carries out follow-up process by other modules.
When program control, distance host is based on remote procedure call with interacting of receiver（RPC）Application layer protocol.At this
Under mode, the passive response program control command of receiver.When the gathered data needing to obtain receiver, distance host is to receiver
Send a query statement, RPC agreement is construed to a process of far call receiver by instructing, and receiver is in the process
Measurement result is sent, distance host can continue executing with next step operation.
Content of the invention
The purpose of the present invention is aiming at existing grid receiver and lacks the caching function of high-speed high capacity it is impossible to realize high
Speed collection, FPGA just can carry out subsequent treatment after want waiting for CPU to run through data, the discontinuous deficiency of data acquisition it is proposed that
A kind of data buffer storage of grid receiver and dispensing device and method.
The present invention adopts the following technical scheme that：
A kind of data buffer storage of grid receiver and dispensing device, including data cache module and TCP communication module, described
Data cache module includes FPGA and DDR3 memorizer, and described FPGA is connected with DDR3 memorizer by interface circuit, and passes through
External system bus are connected with the SOC(system on a chip) in TCP communication module, and described TCP communication module is by SOC(system on a chip) and software in machine
Composition, described SOC(system on a chip) is provided with Ethernet interface.
Preferably, described interface circuit is made up of control line, data path and clock line.
Preferably, described FPGA is provided with the fifo interface reading DDR3 memory data for described SOC(system on a chip).
Preferably, described TCP communication module includes administrative unit, control passage data passage three part.
Preferably, the administrative unit of described TCP communication module includes audiomonitor, message response device, channel map and leads to
Road factory.
Preferably, the control passage of described TCP communication module includes instructing separator and quasi- data channel chained list.
Preferably, the data channel of described TCP communication module includes a transmission agency.
A kind of data buffer storage of grid receiver and sending method, using the asynchronous read and write of DDR3 memorizer, by FPGA
Stream drive hardware control interface as the moving data of software in machine, data is activation is carried out using TCP communication module, data is slow
Deposit and mainly comprise three phases with transmission process：
Caching, the data that grid receiver receives enters row cache by FPGA write DDR3 memorizer, and is utilized by FPGA
Data is transported to fifo interface by the free time of interface bus；
Move, in described software in machine, have a frequency spectrum data to move thread and specially Frame is moved, this thread
Execution following steps：
Step one, judges whether sweep parameter list is empty, continues executing with step one for sky for 50 milliseconds with regard to dormancy, otherwise takes
Gauge outfit of falling out node；
Step 2, creates correspondingly sized on process heap according to the fast fourier transform points in node parameter information
Relief area；
Step 3, with this buffer zone address and size as parameter, is driven by DeviceIoControl () function call stream
Data-moving function, by data-moving function data-moving in FPGA FIFO in relief area, wherein
DeviceIoControl () is an api function of operating system；
Step 4, carries out Logarithm conversion and compensating for frequency response to measurement data, and makes the head of this Frame, and head includes
Frequency, fast fourier transform points, timestamp information；
Step 5, with the socket handle of the data channel of current association as parameter, moving relief area in step 3
Data and step 4 in Frame head packing be sent to TCP communication module；
Step 6, if TCP communication module receives, execution step one, otherwise continue to attempt to step 5；
Transmission, the transmission of data is realized by the TCP communication module of receiver, and the transmitting procedure of data comprises the following steps：
Step a, request for data connects, and distance host is intended to receiving data, and the control passage first passing through foundation is to reception
Machine sends " port " instruction, and this instruction proposes, to receiver, the application setting up data cube computation, contains long-range in command frame
Main frame be used for this data channel connect tcp port number, after receiver receives this instruction, through instruction separate, instruction parsing and
Distribution, finally itself is responsible for response by TCP communication module.In response process, TCP communication module entrusts passage factory to create first
Build out a data channel example being not connected with, and this passage is added to the quasi- data channel chained list of control passage, Ran Houtong
Cross control passage and send response to distance host；
Step b, sets up and connects, and, after receiving response, port numbers when just being connected with application are to receiver for distance host
Initiate connection request；After receiver receives request, find the quasi- data channel consistent with this connection request port numbers, for this quasi- number
Connect according to Path Setup；
Step c, sends, and the internal module of receiver sends data always by data channel to distance host.During transmission,
Internal module with the socket handle of data channel, data block be cited as parameter, propose to send request to TCP communication module,
It is responsible for sending data blocks to network by TCP communication module.
The detailed process sending is controlled by TCP communication module, and TCP communication module searches passage according to socket handle first
Mapping table finds corresponding data channel, then just gives data channel the transmission task delegation of data block, data channel exists
After judging that channel statuses are normal, just sending task delegation to sending agency, send the real details that agency achieves transmission；
Send agency and have the buffer circle of a 64k byte, buffer circle is abstracted into end to end, using facing
Battery limit (BL) is protected, can be with multi-thread access.Under normal circumstances, write data run, in the context of data acquisition thread, sends number
According to the context running on main thread.Data FIFO in buffering, the space reusable edible of buffering；
After data block transmission request in collecting thread is delegated to send agency, send agency first that data block is big
Little compared with the free space of loop buffer.If free space cannot accommodate this data block, just refuse this request；Otherwise
Data block is added to the afterbody of data in buffering, updates the data trailer label, and deliver a data to window and send message.
This message, through the distribution of main thread, is eventually received by data channel.Data channel Preliminary Analysis message is joined
After number, transmission agency is entrusted to proceed to respond to message.Send agency can as much as possible in three iteration send in loop buffer
Data, if loop buffer is empty in an iterative process or sends blocked, all can drop by the wayside.Complete in iteration
Afterwards, if loop buffer still has data not send, deliver a data to window and send message, remain next response message
When send.
The invention has the advantages that：
1st, mount DDR3 memorizer in cache module, data can be directly by FPGA write DDR3 storage after IF process
Device is so that receiver can be with high speed acquisition.
2nd, the read-write of FPGA Time-sharing control DDR3 memorizer, accessing DDR3 memorizer for CPU provides fifo interface, and CPU exists
The interruption of data acquisition is not resulted in when reading data.
3rd, adopt special TCP tunnel data, so that data flow is separated with controlling stream, data flow can be with high-speed and continuous
Be sent to distance host.
4th, the composition structure of grid receiver TCP communication module, is divided into administrative unit, three, control passage data passage
Point, receiver can be interacted with multiple distance hosts simultaneously, and different types of measurement data can be parallel by multiple data channel
Send.
5th, by way of sending and acting on behalf of, on the one hand outwardly shield the complexity of data is activation, on the other hand annular
The design of relief area and the efficient of data is activation be ensure that by the transmission process of message-driven.
Brief description
Fig. 1 is grid receiver internal frame diagram；
Fig. 2 is the coupling part block diagram of DDR3 memorizer and FPGA；
Fig. 3 is the TCP communication modular structure block diagram of receiver.
Specific embodiment
With specific embodiment, the specific embodiment of the present invention is described further below in conjunction with the accompanying drawings：
Specific term is introduced：
FPGA:Field programmable gate array, DDR3：Third generation double data rate Synchronous Dynamic Random Access Memory,
FIFO：First Input First Output, TCP：Transmission control protocol.
As shown in figure 1, a kind of data buffer storage of grid receiver and dispensing device, lead to including data cache module and TCP
Letter module, data cache module includes FPGA and DDR3 memorizer, and described FPGA is connected with DDR3 memorizer by interface circuit,
And be connected with the SOC(system on a chip) in TCP communication module by external system bus, described TCP communication module by SOC(system on a chip) and is stayed
Machine software forms, and described SOC(system on a chip) is provided with Ethernet interface, can transmit data to network.Described FPGA is by interface electricity
Road is connected with DDR3 memorizer, and the memory capacity of DDR3 memorizer is 4GB in the present invention, and SOC(system on a chip) is passed through with distance host
TCP communication module realizes communication, and the CPU of SOC(system on a chip) adopts the processor of ARM Cortex-A8 core, dominant frequency 800MHz, has
100000000 LAN network interfaces, external system bus have the data wire of 16 and the address wire of 24, clock frequency 133MHz.Receiver
Using Window Embedded Compact 7 embedded OS.
As shown in Fig. 2 the interface circuit of described connection FPGA and DDR3 memorizer is by control line, data path and clock line
Composition.
Described FPGA is provided with the fifo interface reading DDR3 memory data for described SOC(system on a chip), passes through inside FPGA
Xilinx FPGA memory interface maker generates IP kernel, and IP kernel comprises physical layer, controller and user interface layer, physical layer
Directly it is connected with DDR3 memorizer.Write address that user interface layer sends over for receive user control interface, write data
With reading address.Controller is the core of whole IP kernel, is responsible for processing the order that user interface layer sends, produces and meet user's request
Activation, reading and writing, precharge, the order such as self-refresh.On the basis of this IP kernel, FPGA controls setting of DDR3 memory portion
Meter is greatly simplified, and programming personnel only needs to be written and read operating according to the timing requirements at IP kernel user operation end.By
Can not read in DDR3 memorizer simultaneously not only but also write, FPGA needs, using timesharing strategy, read-write operation to be separated.Adopt inside FPGA
Line production, carries out quick Fourier transformation computation to previous frame while generating next frame I/Q data and DDR3 memorizer is write
Enter operation, according to the requirement of seamless collection, the time of computing and write is bound to less than the generation time of I/Q data frame, when this
Between in difference, the interface bus of DDR3 memorizer is idle, thus FPGA can be using this time difference by the number in DDR3 memorizer
According to being transported in FIFO.
As shown in figure 3, described TCP communication module includes administrative unit, control passage data passage three part.
The administrative unit of described TCP communication module includes audiomonitor, message response device, channel map and passage factory,
The connection request of wherein listener process 8080 port, if allow to set up connected, just using passage factory establishment passage object.
Message response device is used for response to network event, when window is notified that TCP communication module, Ran Houyou after receiving network event messages
Message response device is message distribution to corresponding passage；Channel map recording channel socket handle and the correspondence of passage object
Relation, the control passage data passage of each foundation all records in the table, can be quickly found by socket handle
Its passage object.Passage factory is responsible for creating the example of control passage data passage.
The control passage of described TCP communication module includes instructing separator and quasi- data channel chained list.Instruction separator pair
The data flow receiving buffering is processed, and data flow is divided into command frame one by one, then by the instruction distribution of receiver
Module is sent to the response of each internal module of receiver.Control passage also comprises a quasi- data channel chained list, preserves those persons in servitude
Belong to this control passage, but the not yet real data channel setting up connection.
The data channel of described TCP communication module includes one and sends agency, and this agency is accepting receiver internal module
After the data to be sent, with windows messaging for driving, asynchronously transmit data to distance host.
A kind of data buffer storage of grid receiver and sending method, using the asynchronous read and write of DDR3 memorizer, by FPGA
Stream drive hardware control interface as the moving data of software in machine, data is activation is carried out using TCP communication module, data is slow
Deposit and mainly comprise three phases with transmission process：
Caching, the data that grid receiver receives enters row cache by FPGA write DDR3 memorizer, and is utilized by FPGA
Data is transported to fifo interface by the free time of interface bus；
Move, in described software in machine, have a frequency spectrum data to move thread and specially Frame is moved, this thread
Execution following steps：
Step one, judges whether sweep parameter list is empty, continues executing with step one for sky for 50 milliseconds with regard to dormancy, otherwise takes
Gauge outfit of falling out node；
Step 2, creates correspondingly sized on process heap according to the fast fourier transform points in node parameter information
Relief area；
Step 3, with this buffer zone address and size as parameter, is driven by DeviceIoControl () function call stream
Data-moving function, by data-moving function data-moving in FPGA FIFO in relief area, wherein
DeviceIoControl () is an api function of operating system；
Step 4, carries out Logarithm conversion and compensating for frequency response to measurement data, and makes the head of this Frame, and head includes
Frequency, fast fourier transform points, timestamp information；
Step 5, with the socket handle of the data channel of current association as parameter, moving relief area in step 3
Data and step 4 in Frame head packing be sent to TCP communication module；
Step 6, if TCP communication module receives, execution step one, otherwise continue to attempt to step 5；
Transmission, the transmission of data is realized by the TCP communication module of receiver, and the transmitting procedure of data comprises the following steps：
Step a, request for data connects, and distance host is intended to receiving data, and the control passage first passing through foundation is to reception
Machine sends " port " instruction, and this instruction proposes, to receiver, the application setting up data cube computation, contains long-range in command frame
Main frame is used for the tcp port number that this data channel connects；
Step b, sets up and connects, and, after receiving response, port numbers when just being connected with application are to receiver for distance host
Initiate connection request；After receiver receives request, find the quasi- data channel consistent with this connection request port numbers, for this quasi- number
Connect according to Path Setup.
Step c, sends, and the internal module of receiver sends data always by data channel to distance host.During transmission,
Internal module with the socket handle of data channel, data block be cited as parameter, propose to send request to TCP communication module,
It is responsible for sending data blocks to network by TCP communication module.
The detailed process sending is controlled by TCP communication module, and TCP communication module searches passage according to socket handle first
Mapping table finds corresponding data channel, then just gives data channel the transmission task delegation of data block, data channel exists
After judging that channel statuses are normal, just sending task delegation to sending agency, send the real details that agency achieves transmission.
Send agency and have the buffer circle of a 64k byte, buffer circle is abstracted into end to end, using facing
Battery limit (BL) is protected, can be with multi-thread access.Under normal circumstances, write data run, in the context of data acquisition thread, sends number
According to the context running on main thread.Data FIFO in buffering, the space reusable edible of buffering.
After data block transmission request in collecting thread is delegated to send agency, send agency first that data block is big
Little compared with the free space of loop buffer.If free space cannot accommodate this data block, just refuse this request；Otherwise
Data block is added to the afterbody of data in buffering, updates the data trailer label, and deliver a data to window and send message.
This message, through the distribution of main thread, is eventually received by data channel.Data channel Preliminary Analysis message is joined
After number, transmission agency is entrusted to proceed to respond to message.Send agency can as much as possible in three iteration send in loop buffer
Data, if loop buffer is empty in an iterative process or sends blocked, all can drop by the wayside.Complete in iteration
Afterwards, if loop buffer still has data not send, deliver a data to window and send message, remain next response message
When send.
Certainly, described above is not limitation of the present invention, and the present invention is also not limited to the example above, and this technology is led
Change, remodeling, interpolation or replacement that the technical staff in domain is made in the essential scope of the present invention, also should belong to the present invention's
Protection domain.
Claims (1)
1. a kind of data buffer storage of grid receiver and sending method, is filled with sending using a kind of data buffer storage of grid receiver
Put, including data cache module and TCP communication module, described data cache module includes FPGA and DDR3 memorizer, described
FPGA is connected with DDR3 memorizer by interface circuit, and by the SOC(system on a chip) in external system bus and TCP communication module
It is connected, described TCP communication module is made up of SOC(system on a chip) and software in machine, and described SOC(system on a chip) is provided with Ethernet interface；
Described interface circuit is made up of control line, data path and clock line；
Described FPGA is provided with the fifo interface reading DDR3 memory data for described SOC(system on a chip)；
Described TCP communication module includes administrative unit, control passage data passage three part；
The administrative unit of described TCP communication module includes audiomonitor, message response device, channel map and passage factory；
The control passage of described TCP communication module includes instructing separator and quasi- data channel chained list；
The data channel of described TCP communication module includes one and sends agency；
Using the asynchronous read and write of DDR3 memorizer, the hardware controls as the moving data of software in machine are driven to connect by the stream of FPGA
Mouthful, data is activation is carried out using TCP communication module, it is characterized in that, data buffer storage and transmission process mainly comprise three phases：
Caching, the data that grid receiver receives enters row cache by FPGA write DDR3 memorizer, and utilizes interface by FPGA
Data is transported to fifo interface by the free time of bus；
Move, in described software in machine, have a frequency spectrum data to move thread and specially Frame is moved, this thread executes
Following steps：
Step one, judges whether sweep parameter list is empty, continues executing with step one for sky for 50 milliseconds with regard to dormancy, otherwise takes out row
Gauge outfit node；
Step 2, creates correspondingly sized buffering according to the fast fourier transform points in node parameter information on process heap
Area；
Step 3, with this buffer zone address and size as parameter, is driven by the system API Calls stream of DeviceIoControl ()
Dynamic data-moving function, by data-moving function data-moving in FPGA FIFO in relief area；
Step 4, carries out Logarithm conversion and compensating for frequency response to measurement data, and makes the head of this Frame, and head includes frequency
Rate, fast fourier transform points, timestamp information；
Step 5, with the socket handle of the data channel of current association as parameter, the number moving relief area in step 3
According to step 4 in Frame head packing be sent to TCP communication module；
Step 6, if TCP communication module receives, execution step one, otherwise continue to attempt to step 5；
Transmission, the transmission of data is realized by the TCP communication module of receiver, and the transmitting procedure of data comprises the following steps：
Step a, request for data connects, and distance host is intended to receiving data, and the control passage first passing through foundation is sent out to receiver
" port " is sent to instruct, this instruction proposes, to receiver, the application setting up data cube computation, contains distance host in command frame
The tcp port number connecting for this data channel；
Step b, sets up and connects, and distance host, after receiving response, is just initiated to receiver with applying for port numbers when connecting
Connection request；After receiver receives request, find the quasi- data channel consistent with this connection request port numbers, lead to for this quasi- data
Road is set up and is connected；
Step c, sends, and the internal module of receiver sends data always by data channel to distance host, during transmission, internal
Module with the socket handle of data channel, data block be cited as parameter, propose to send request to TCP communication module, by TCP
Communication module is responsible for sending data blocks to network.
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| CN106603172A (en) * | 2016-11-24 | 2017-04-26 | 中国电子科技集团公司第四十研究所 | Time stamp data time sharing reading-writing method applied to radio monitoring receiver |
| CN106788919A (en) * | 2016-11-24 | 2017-05-31 | 中国电子科技集团公司第四十研究所 | Self adaptation cut position I/Q data real-time monitoring implementation method in a kind of gridding receiver |
| CN109547355B (en) * | 2018-10-17 | 2022-05-06 | 中国电子科技集团公司第四十一研究所 | Storage analysis device and method based on gigabit Ethernet port receiver |
| CN113434455B (en) * | 2021-06-22 | 2023-10-24 | 中国电子科技集团公司第十四研究所 | Optical fiber interface data cache management method based on FPGA |
| CN113961212B (en) * | 2021-10-29 | 2024-05-10 | 重庆长安汽车股份有限公司 | OTA installation package deployment method and system based on Ethernet and method for upgrading vehicle controller |
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