CN104615386B - The outer caching device of one seed nucleus - Google Patents
The outer caching device of one seed nucleus Download PDFInfo
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Abstract
The outer caching device of one seed nucleus, including slave unit interface unit, control unit, memory cell, host device interface unit and synchronization unit.Slave unit interface unit receives and the access request of response main frame；Control unit accesses memory cell or sends the request to host device interface unit, and carry out the backfill of cache lines according to the request of register configuration information processing slave unit interface unit transmission；The data and its flag information of memory cell caching control unit write-in；Host device interface unit is responsible for downward primary storage device and sends access request, data cached required for obtaining；Synchronization unit is converted to the access request that host device interface unit is sent the signal for meeting next stage storage device clocked sequential.The invention provides a kind of access delay for effectively reducing nonvolatile memory, lift caching device outside the core of processor memory access performance.
Description
Technical field
The present invention relates to System on Chip/SoC (SoC) Integrated design field, more particularly to the outer caching device of a seed nucleus.
Background technology
With the horizontal continuous lifting of integrated circuit technology, the collection of on-chip system chip (SoC) is increasing on a large scale, work(
It can also become increasingly complex, be powerful.To meet diversified application demand, such as nonvolatile memory, EEPROM, FLASH etc. all
It is integrated into inside SoC chip, and capacity is also increasing.
Nonvolatile memory is commonly stored program and significant data in piece, and the startup and execution to system have important shadow
Ring.Particularly NorFlash, processor can directly read the director data of its storage, configuration processor.But due to NorFlash
Reading speed is far below the clock frequency of processor, and this executive mode can cause the performance of processor or even whole SoC systems
Bottleneck, efficiency are very low.Therefore, it is necessary to accelerate to the slow nonvolatile memory of memory access, reduce its access and prolong
When, improve the overall performance of system.
For being internally integrated the processor of high speed instruction caching, the performance bottlenecks of NorFlash reading speeds can be with
Obtain a certain degree of solution.But the cache integrated in processor core and processor close coupling, often underaction, does not have
It is designed for the accessing characteristic of NorFlash or other nonvolatile memories, it is also difficult to modify, integrating is difficult
Spend larger.
Simultaneously with the raising of integrated level, the power consumption of SoC System on Chip/SoCs is also increasing, and low power dissipation design has become
The important content of SoC design.Nonvolatile memory is as program and the storage region of significant data, often as storage subsystem
System is articulated in bus, and its frequency is mostly variable.Bus Clock Rate is improved when performance requirement is higher, reduces and accesses delay；
And memory clock frequency is reduced under conditions of certain performance is met, the power consumption of memory can be effectively reduced.
The content of the invention
In order to overcome larger, the processor memory access performance of the access of nonvolatile memory in existing SoC System on Chip/SoCs delay
Limited deficiency, the invention provides a kind of access delay for effectively reducing nonvolatile memory, lifting processor memory access
The outer caching device of the core of energy.
The technical solution adopted for the present invention to solve the technical problems is：
The outer caching device of one seed nucleus, including：
Slave unit interface unit, the read and write access for reception processing device or other main equipments are asked, and by access request
It is sent to control unit；The data cached or response message that reception control unit returns, is sent to processor or other main equipments；
Host device interface unit, the access request sent for reception control unit, next stage is sent to by access request
Storage system, the data or response message obtained are returned to control unit；
Control unit, comprising high area controller can be delayed, strategy controller and data cached type controllers are write, for receiving
The caching read and write access request that the slave unit interface unit is sent, according to register configuration information, access memory cell or straight
Connect and send the requests to host device interface unit, then obtained data cached or response message is returned into slave unit interface list
Member；
Memory cell, for the access request of reception control unit, data that storage host device interface unit obtains and its
Address mark information, return to the data cached of hit to control unit or be not hit by information；
Synchronization unit, for the clock sync signal according to input, the access request that host device interface unit is sent turns
It is changed to the access request signal for the clocked sequential for meeting next stage storage system, the data that next stage storage system is returned or sound
Information is answered to be converted to the signal for the clocked sequential for meeting the caching device.
Further, described control unit can high slow area controller, comprising NGe Kegaohuan areas configuration register, N is whole
Number, each can Gao Huan areas configuration register include can Gao Huan areas base address it is high-order, can Gao Huan areas size configuration bit and Ke Gao delay area
Enable bit, it is described can high slow area controller by memory access address with can be compared with Gao Huan areas configuration register, with judging the memory access
Whether location is positioned at can be in Gao Huan areas, if the memory access address, positioned at can be in Gao Huan areas, the outer caching device of the core caches the visit
The data of address storage are deposited, if memory access address, positioned at can be in Gao Huan areas, the outer caching device of the core returns to processor
After accessing data, the data are not cached.
Further, described control unit writes strategy controller, configurable to write strategy comprising writing policy control register
For write it is straight-through, write back or write access can not cache, write straight-through policy synchronization and update the corresponding contents of the memory cell and next
Level storage device, the corresponding contents that strategy only updates the memory cell caching are write back, are replaced in the cache contents changed
When just update next stage storage device, write access can not cache policy write operation is submitted directly to next stage storage device, no
The memory cell is updated.
Further, the data cached type controllers of described control unit, data cached type register, control are included
Type that can be data cached, the data cached type register include director data can cache bit and general data can cache
Position, director data can cache bit indicator data whether can be buffered, general data can cache bit instruction general data whether
It can be buffered.
The memory cell includes P roads group associative structure, the storage battle array for the memory composition that depth Q, storage width are W
Row, P, Q, W are integer.
The synchronization unit supports that the device and next stage storage device clock frequency ratio are F:1 signal is synchronous, and F is whole
Number, required clock sync signal is as caused by outside.
Beneficial effects of the present invention are mainly manifested in：1st, the access delay of nonvolatile memory is effectively reduced, at lifting
Manage device memory access performance；2nd, support variable frequency, flexibility are higher.
Brief description of the drawings
Fig. 1 is the block schematic diagram of the outer embodiment of caching device one of core of the present invention.
Fig. 2 is the control unit schematic diagram of one embodiment of the invention.
Fig. 3 is that the control unit of one embodiment of the invention can high slow area controller schematic diagram.
Fig. 4 is the synchronization unit schematic diagram of one embodiment of the invention.
Fig. 5 is the synchronization unit clock frequency ratio 4 of one embodiment of the invention:1 timing diagram.
Fig. 6 is the synchronization unit clock frequency ratio 2 of one embodiment of the invention:1 timing diagram.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
1~Fig. 6 of reference picture, the outer caching device of a seed nucleus, in SoC System on Chip/SoCs, including：
Slave unit interface unit, the read and write access request of reception processing device or other main equipments, and access request is sent
To control unit；The data cached or response message that reception control unit returns, is sent to processor or other main equipments.
Control unit, comprising can high slow area controller, strategy controller and data cached type controllers are write, described in reception
The caching read and write access request that slave unit interface unit is sent, according to register configuration information, access memory cell or directly will
Request is sent to host device interface unit, then obtained data cached or response message is returned into slave unit interface unit.
Memory cell, comprising some storage arrays, the access request of reception control unit, storage host device interface unit obtains
The data and its address mark information taken, return to the data cached of hit to control unit or be not hit by information.
Host device interface unit, the access request that reception control unit is sent, access request is sent to next stage storage
System, the data or response message obtained are returned to control unit.
Synchronization unit, according to the clock sync signal of input, the access request that main equipment unit is sent is converted to and met
The access request signal of the clocked sequential of next stage storage system, the data or response message that next stage storage system is returned turn
It is changed to the signal for the clocked sequential for meeting the caching device.
Further, described control unit can high slow area controller, comprising NGe Kegaohuan areas configuration register, N is whole
Number, each can Gao Huan areas configuration register include can Gao Huan areas base address it is high-order, can Gao Huan areas size configuration bit and Ke Gao delay area
Enable bit, it is described can high slow area controller by memory access address with can be compared with Gao Huan areas configuration register, with judging the memory access
Whether location is positioned at can be in Gao Huan areas, if the memory access address, positioned at can be in Gao Huan areas, the outer caching device of the core caches the visit
The data of address storage are deposited, if memory access address, positioned at can be in Gao Huan areas, the outer caching device of the core returns to processor
After accessing data, the data are not cached.
Further, described control unit writes strategy controller, configurable to write strategy comprising writing policy control register
For write it is straight-through, write back or write access can not cache, write straight-through policy synchronization and update the corresponding contents of the memory cell and next
Level storage device, the corresponding contents that strategy only updates the memory cell caching are write back, are replaced in the cache contents changed
When just update next stage storage device, write access can not cache policy write operation is submitted directly to next stage storage device, no
The memory cell is updated.
Further, the data cached type controllers of described control unit, data cached type register, control are included
Type that can be data cached, the data cached type register include director data can cache bit and general data can cache
Position, director data can cache bit indicator data whether can be buffered, general data can cache bit instruction general data whether
It can be buffered.
The memory cell includes P roads group associative structure, the storage battle array for the memory composition that depth Q, storage width are W
Row, P, Q, W are integer.
The synchronization unit supports that the device and next stage storage device clock frequency ratio are F:1 signal is synchronous, and F is whole
Number, required clock sync signal is as caused by outside.
2~Fig. 3 of reference picture, in the present embodiment, control unit can high slow area controller judge slave unit interface unit hair
The access request address sent whether positioned at can Gao Huan areas, output can Gao Huan areas matched signal；Data cached type controllers include
Data cached type register, according to the director data of the register can cache bit or general data can cache bit, and memory access
The data type of request, output can high slow type permission signals；Strategy controller is write, comprising writing policy control register, according to
The type of access request, output write request processing indication signal.Can cache request arbitrated logic receive above output signal, it is comprehensive
Judge whether this access request can be buffered.For read request, only can Gao Huan areas matched signal and Ke Gao delay type and permit
Perhaps the request is only cacheable when signal is effective；For write operation, only can Gao Huan areas matched signal, can high slow type permit
Perhaps when signal and write request processing indication signal are designated as writing straight-through strategy or writing back strategy, the request is cacheable.It can delay
The request deposited be sent to can cache request processing logic handled, not cacheable request will be sent to can not cache please
Processing logic is asked to be handled.
In this example, can cache request processing logic receive effectively request after, first access memory cell, if hit deposit
Storage unit, then the data obtained from memory cell are directly returned to slave unit interface unit；, can cache request if be not hit by
Processing logic sends the request to host device interface unit, waits host device interface unit to return to the data of request, will be from master
The data that facility interface unit obtains return to slave unit interface unit, and write storage unit, then carry out with the request
The backfill of other data of the same cache lines in location.Can not cache request processing logic receive effectively request after, will request send
To host device interface unit, the data that host device interface unit obtains are received, and return to slave unit interface unit.
Reference picture 3, in the present embodiment, control unit can high slow area controller include NGe Kegaohuan areas register, each
Can Gao Huan areas register include enable bit, can Gao Huan areas plot and Ke Gao delay area's size；Can the high comparator root for delaying area controller
According to can Gao Huan areas plot, can Gao Huan areas size, judge access request that slave unit interface unit sends whether can in Gao Huan areas,
With reference to enable bit, output NGe Kegaohuan areas matched signal；NGe Kegaohuan areas matched signal generates most after carrying out logic or operation
Afterwards can Gao Huan areas matched signal.
Reference picture 1 and Fig. 4, in the present embodiment, host device interface cell processing meets the request of ahb bus agreement, synchronous
Unit receives the transmission of host device interface unit by isochronous controller, sampling module, MUX and output register composition
Effective access request after, isochronous controller state machine in it starts, the downward primary storage device clock of control data signal
Domain timing conversion.The state machine has tetra- states of IDLE, DRIVE, WAIT and ERROR, only synchronously believes in the clock of input
Number effectively when State Transferring can just occur.Sampling module samples the return of next stage storage device when clock sync signal is effective
Data and response message.
IDLE：During without effective access request, state machine acquiescence is in IDLE states；Effective request is received, and clock is same
Step signal is effective, in the case of next stage storage device normal (hready_H of sampling module output is high, hresp_H 0),
State machine enters DRIVE states, and control MUX selects current access request signal, sends the request to next stage storage
Equipment.
DRIVE：Output register is maintained to be sent to effective request signal of next stage storage device, to ensure to meet at that time
Sequence requirement, if next stage storage device is normal, state machine enters WAIT states, otherwise returns to IDLE states.
WAIT：Next stage storage device returned data and response message are waited, if data normally return and without new
Request, state machine enters IDLE states；If data normally return and have new request, state machine is directly entered DRIVE states；
If next stage storage device returns to abnormal response message, state machine enters ERROR states.
ERROR：State machine enters IDLE states after waiting next stage storage device normally, to receive new request.
Reference picture 5, the figure is the outer cache clock frequency of core and next stage storage device clock frequency ratio is 4:1
Bus interface timing figure.In the 2nd clock cycle, synchronization unit receives effective access request that address is A, and clock is synchronous
Signal is height, and isochronous controller state machine switchs to DRIVE states by IDLE states.Because frequency ratio is 4:1, DRIVE state continues four
Clock cycle, output register is kept to be sent to effective request signal (hsel_L, htrans_L etc.) of next stage storage device.
Subsequent isochronous controller state machine enters WAIT states and waits request data to return.In the 7th clock cycle, next stage storage device
Export request data, but only after clock sync signal samples (the 10th clock cycle), data and response message
(hrdata_H, hready_H etc.) is just returned to host device interface unit.
Reference picture 6, the figure is the outer cache clock frequency of core and next stage storage device clock frequency ratio is 2:1
Bus interface timing figure.After isochronous controller state machine enters WAIT states, due to next stage storage device backward reference mistake
Response, isochronous controller state machine enters ERROR states under clock sync signal control, while characterizes this memory access and mistake occur
Signal hresp_H host device interface unit is returned to by synchronization unit.In last clock cycle of ERROR states,
Hready_L is sampled by clock sync signal, obtains hready_H signals.The signal characterizes wrong responses and terminated, together if height
Step controller state machine subsequently enters IDLE states, waits access request next time.
Claims (6)
1. the outer caching device of a seed nucleus, including：
Slave unit interface unit, the read and write access for reception processing device or other main equipments is asked, and access request is sent
To control unit；The data cached or response message that reception control unit returns, is sent to processor or other main equipments；
Host device interface unit, the access request sent for reception control unit, access request is sent to next stage storage
System, the data or response message obtained are returned to control unit；
It is characterized in that：The outer caching device of the core also includes：
Control unit, comprising high area controller can be delayed, strategy controller and data cached type controllers are write, it is described for receiving
The caching read and write access request that slave unit interface unit is sent, according to register configuration information, access memory cell or directly will
Request is sent to host device interface unit, then obtained data cached or response message is returned into slave unit interface unit；
Memory cell, for the access request of reception control unit, data and its address that storage host device interface unit obtains
Flag information, return to the data cached of hit to control unit or be not hit by information；
Synchronization unit, for the clock sync signal according to input, the access request that host device interface unit is sent is converted to
Meet the access request signal of the clocked sequential of next stage storage system, the data that next stage storage system is returned or response letter
Breath is converted to the signal for the clocked sequential for meeting the caching device；
Host device interface cell processing meets the request of ahb bus agreement, and synchronization unit is more by isochronous controller, sampling module
Road selector and output register composition, after receiving effective access request that host device interface unit is sent, the synchronization in it
Controller state machine starts, the downward primary storage device clock zone timing conversion of control data signal；The state machine have IDLE,
Tetra- states of DRIVE, WAIT and ERROR, only when the clock sync signal of input is effective, State Transferring can just occur；Sampling
Module samples the data and response message of next stage storage device return when clock sync signal is effective；
IDLE：During without effective access request, state machine acquiescence is in IDLE states；Effective request is received, and clock is synchronously believed
Number effectively, in the case of next stage storage device is normal, sampling module output hready_H for height, hresp_H 0, state
Machine enters DRIVE states, and control MUX selects current access request signal, sends the request to next stage storage and set
It is standby；
DRIVE：Output register is maintained to be sent to effective request signal of next stage storage device, to ensure to meet that its sequential will
Ask, if next stage storage device is normal, state machine enters WAIT states, otherwise returns to IDLE states；
WAIT：Next stage storage device returned data and response message are waited, if data normally return and please without new
Ask, state machine enters IDLE states；If data normally return and have new request, state machine is directly entered DRIVE states；If
Next stage storage device returns to abnormal response message, and state machine enters ERROR states；
ERROR：State machine enters IDLE states after waiting next stage storage device normally, to receive new request.
2. the outer caching device of core as claimed in claim 1, it is characterised in that：Described control unit can Gao Huan areas control
Device, comprising NGe Kegaohuan areas configuration register, N is integer, each can Gao Huan areas configuration register include can Gao Huan areas base address
A high position, can Gao Huan areas size configuration bit and Ke Gao delay area's enable bit, it is described can high slow area controller by memory access address with can be high slow
Whether area's configuration register is compared, judge the memory access address positioned at can be in Gao Huan areas, if the memory access address is positioned at can be high slow
In area, the outer caching device of the core caches the data of memory access address storage, if memory access address positioned at can in Gao Huan areas,
The outer caching device of the core does not cache to after processor backward reference data to the data.
3. the outer caching device of core as claimed in claim 1 or 2, it is characterised in that：Described control unit writes tactful control
Device processed, comprising writing policy control register, it is configurable write strategy for write it is straight-through, write back or write access can not cache, write straight-through plan
The slightly corresponding contents and next stage storage device of memory cell described in synchronized update, write back strategy and only update the memory cell and delay
The corresponding contents deposited, next stage storage device is just updated when the cache contents changed are replaced, and write access can not cache plan
Write operation is slightly submitted directly to next stage storage device, the memory cell is not updated.
4. the outer caching device of core as claimed in claim 1 or 2, it is characterised in that：Described control unit it is data cached
Type controllers, comprising data cached type register, the type that control can be data cached, the data cached type register
Comprising director data can cache bit and general data can cache bit, director data can cache bit indicator data whether can be delayed
Deposit, general data can cache bit instruction general data whether can be buffered.
5. the outer caching device of core as claimed in claim 1 or 2, it is characterised in that：The memory cell includes P roads group phase
It is coupled structure, the storage array for the memory composition that depth Q, storage width are W, P, Q, W is integer.
6. the outer caching device of core as claimed in claim 1 or 2, it is characterised in that：The synchronization unit supports the device
It is F with next stage storage device clock frequency ratio:1 signal is synchronous, and F is integer, and required clock sync signal is by outer
Caused by portion.
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| US20170017394A1 (en) * | 2015-07-15 | 2017-01-19 | Futurewei Technologies, Inc. | SYSTEM AND METHOD FOR DATA WAREHOUSE AND FINE GRANULARITY SCHEDULING FOR SYSTEM ON CHIP (SoC) |
| CN106557433A (en) * | 2015-09-28 | 2017-04-05 | 深圳市博巨兴实业发展有限公司 | A kind of method and apparatus of microcontroller cache |
| KR20200015185A (en) * | 2018-08-03 | 2020-02-12 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
| CN112765057A (en) * | 2020-12-30 | 2021-05-07 | 京信网络系统股份有限公司 | Data transmission method, PCIE system, equipment and storage medium |
| CN113806250B (en) * | 2021-09-24 | 2022-10-18 | 中国人民解放军国防科技大学 | Method for coordinating general processor core and vector component, interface and processor |
| CN115454502B (en) * | 2022-09-02 | 2023-06-02 | 杭州登临瀚海科技有限公司 | Method for scheduling return data of SIMT architecture processor and corresponding processor |
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