CN104679681A - High-speed bridge device for AHB (advanced high-performance bus) accessing on-chip SRAM (static random access memory) and operating method of high-speed bridge device - Google Patents
High-speed bridge device for AHB (advanced high-performance bus) accessing on-chip SRAM (static random access memory) and operating method of high-speed bridge device Download PDFInfo
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Abstract
The invention discloses a high-speed bridge device for an AHB (advanced high-performance bus) accessing an on-chip SRAM (static random access memory), which comprises a register and a plus one counter; during write operation, an SRAM address, i.e. an AHB address of the previous clock cycle, which is obtained after an AHB address is stored by the register for a beat is accessed; during read operation, at the beat of returning read operation data, a predicted address which is obtained after the plus one counter adds one to the AHB address is accessed, and at the beat of incomplete read operation data transmission, the AHB address is the SRAM address, i.e., the current AHB address is accessed. The invention also discloses an operating method of the high-speed bridge device for the AHB accessing the on-chip SRAM. The invention uses the buss bridge with an address prediction mechanism to accelerate the read-write access of the high-capacity SRAM, thus increasing the operating efficiency of the whole system.
Description
Technical field
The present invention relates to data high-speed process field, particularly relate to high speed Biodge device and the method for work thereof of SRAM on a kind of ahb bus access sheet.
Background technology
Also can realize in the system of complex data processing capacity with high-speed peripheral interface at one, SRAM plays a part data temporary storage usually.Use the original intention of Large Copacity SRAM to be improve system effectiveness, because in various memory device, read or write speed is from being register, SRAM, DRAM, FLASH, conventional hard successively near slow order.In SOC system, the normal CPU applied with IP form is for raising the efficiency its own band cache, and there is the interface of operation cache inside.Carry Large Copacity SRAM then can be selected in bus as cache when other data flow control module of system need data cached, benefit is can be used for and uses scheduling to multiple main device module, and can need to control size flexibly according to system.
The most frequently used bus of SOC (system on a chip) is AMBA bus, the relatively read-write sequence of its read-write sequence standard and SRAM, difference is that a clock period of write operation of SRAM completes, read operation needs to obtain data at the following clock cycle providing order, and AHB read-write operation is all first clock period transmission command, second clock period transmission data.The way that common AHB turns SRAM bridge is exactly that during write operation, command signal deposits a bat to SRAM according to judging that read-write operation selects different command signals to SRAM, and during read operation, the direct-connected SRAM of command signal, data line is direct-connected.But this mode is only applicable to low capacity SRAM, the sequential limitation of Large Copacity SRAM is that the delay of CK to Q is very large, wherein CK refers to the CK pin (clock pin) of SRAM, Q refers to the DO* pin (data out0 ~ 31 pin) of SRAM, such as, under 0.11 technique, CK to the Q of the 40KSRAM of UMC is approximately 4.2ns, add that other logic on timing path is easy to exceed 5ns, that is the frequency of 200M can not be met.If system clock needs to go to 200M and above, need the reading data of SRAM to deposit a bat to ensure the Time Created of bus signals.According to bus protocol, it is that data are unripe that hready_out signal demand drags down a bat to declare that bat clock period of depositing, and needs extra one to clap the clock period like this during single read data transmission.When burst, incremental or continuous single transmission, per triple time hready_out signal just needs to drag down a bat (see Fig. 1, wherein hrdata is that sram_rdata deposits a bat).The efficiency of whole system decreases.
Summary of the invention
In order to overcome the deficiencies in the prior art, the invention provides high speed Biodge device and the method for work thereof of SRAM on a kind of ahb bus access sheet, use the bus bridge with address prediction mechanism to accelerate the read and write access of Large Copacity SRAM, improve the operational efficiency of whole system.
For achieving the above object, the invention provides following technical scheme:
On ahb bus access sheet, a high speed Biodge device of SRAM, comprises register and adds a counter, and during write operation, the SRAM address obtained after a bat is deposited through register in access ahb bus address, namely goes up the ahb bus address of a clock period; During read operation, return bat in read operation data, access ahb bus address is through adding the predicted address obtained after a counter adds a counting, and do not complete bat in the transmission of read operation data, ahb bus address is SRAM address, namely accesses current ahb bus address.
Further, during write operation, at write operation when clapping and by writing the first count becoming and read, accessing ahb bus address and depositing through register the SRAM address obtained after a bat, namely going up the ahb bus address of a clock period.
Further, write operation is when clapping as the data beats of ahb bus write operation or the write operation of SRAM are when clapping; Describedly become the first count read into read-write when ahb bus accesses continued operation clap by writing the read command become when reading by writing.
Further, the transmission of described read operation data does not complete and claps is data beats when hready_out signal drags down, and the condition that described hready_out signal drags down is: be in hsel signal rising edge, hwrite signal negative edge, sram_wr_en signal negative edge and arsis read operation miss time.
The present invention also provides a kind of ahb bus to access the method for work of the high speed Biodge device of SRAM on sheet, and during write operation, the SRAM address obtained after a bat is deposited through register in access ahb bus address, namely goes up the ahb bus address of a clock period; During read operation, return bat in read operation data, access ahb bus address is through adding the predicted address obtained after a counter adds a counting, and do not complete bat in the transmission of read operation data, ahb bus address is SRAM address, namely accesses current ahb bus address.
Further, during write operation, at write operation when clapping and by writing the first count becoming and read, accessing ahb bus address and depositing through register the SRAM address obtained after a bat, namely going up the ahb bus address of a clock period.
Further, described write operation is when clapping as the data beats of ahb bus write operation or the write operation of SRAM are when clapping; Describedly become the first count read into read-write when ahb bus accesses continued operation clap by writing the read command become when reading by writing.
Further, the transmission of described read operation data does not complete and claps is data beats when hready_out signal drags down, and the condition that described hready_out signal drags down is: be in hsel signal rising edge, hwrite signal negative edge, sram_wr_en signal negative edge and arsis read operation miss time.
Beneficial effect of the present invention is as follows:
(1) the CK-Q time delay because of Large Copacity SRAM is excessive, adds level cache, and namely hrdata is depositing of sram_rdata and indirectly connected, reserves sequential allowance to other logics in bus, the clock frequency of system is improved and ensure that chip sequential.
(2) SRAM address produce in introduce predicted address only need read for the first time when carrying out read operation hready_out signal drag down offset from sram_rdata to hrdata one clap time delay, read operation afterwards can be got up continuously, formed flowing water.
(3) when occurring that when bus continued operation read-write switches or predicts the situation of not hitting, drag down hready_out signal, ensure that systemic-function is correct.
(4) upper layer software (applications) directly can carry out read-write operation to it according to system assignment to the address of SRAM, initiates the transmission of various data.
(5) choice for use when the present invention is adapted at SOC (system on a chip) bus carry Large Copacity SRAM, because the CK-Q time delay of Large Copacity SRAM is larger, read data time delay one clap can ensure to meet when high-frequency clock frequency device set up the retention time, leave enough sequential allowances to neighbor logic.Adopt the design can evade read data time delay one bat to feed back to system that bus brings and read efficiency continuously and reduce, be issued in the little logistical overhead prerequisite of increase the effect improving whole chip cost performance.
Accompanying drawing explanation
Fig. 1 is that existing common AHB turns SRAM bridge sequential chart.
Fig. 2 is that common AHB provided by the invention turns SRAM high speed bridge sequential chart.
Fig. 3 is high speed crane span structure composition provided by the invention.
Fig. 4 is the generation process flow diagram of SRAM address of the present invention.
Fig. 5 is that hready_out signal of the present invention drags down process flow diagram.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
As shown in Figure 3, the present invention turns on SRAM Bridge Foundation at common AHB and adds address prediction mechanism, relatively bus address and predicted address, if reading in sram of previous clock period unanimously can be carried, ensure that chip meet timing requirements while data can transmit continuously; Predicted address just refers to and adds an address counted to get, suppose that on Current bus, address is 0x0000_1234, this address is byte address, removing minimum two is then word address, i.e. 0x0000_048d, become 0x0000_048e after adding a counting, this address is exactly predicted address, returns bat then use this predicted address as SRAM address in the data of read operation.Therefore expense of the present invention is on common Bridge Foundation, increase by one add 1 counter and relevant steering logic, a hundreds of door can not be exceeded, efficiency can improve 1/3rd when bus sends continuous read operation, during opportunistic transmission and common AHB turn SRAM bridge equivalence.As shown in Figure 2, the present invention improves rear usage forecastings address, without the need to dragging down hready_out signal, contrasting improve read data efficiency with Fig. 1.
Fig. 3 is the generation process flow diagram of SRAM address of the present invention, and whether bus address determines to use according to read-write state and add a counter and add the result that a bat deposited by a counting or register, and then obtains SRAM address, wherein:
(1) bus address is the ahb bus address signal (haddr) entered from Biodge device input port.
(2) add a counting to refer to and carry out to the ahb bus address signal entered from input port the predicted address that logical add one operation obtains, this operation belongs to pure combinational logic, and namely predicted address produced in the same clock period of bus address.
(3) the ahb bus address signal that a bat refers to a clock period is deposited, address during total line write transactions is deposited by this operation, make it to write data with bus and be supplied to SRAM within the same clock period, meet the characteristic of SRAM write operational command data at same period.
The generation of SRAM address is similar to MUX, can select to add the predicted address counted to get or a bus address during read operation, uses the address of depositing a bat during write operation.
In Fig. 3, read operation data return bat---and it is all that a point order is clapped and data beats two bat completes that-ahb bus is read and write, order sending address, transmission mode and read write command, data beats transmission data, during write operation, data write to SRAM by ahb bus, during read operation, data return ahb bus by SRAM, so read operation data here return the data beats of clapping when referring to ahb bus read data in a transmission.
If the transmission of read operation data does not complete bat----read operation data beats runs into hready_out signal and drags down and will continue until hready_out signal is drawn high just declare that data beats completes, so read operation data are transmitted do not complete bat when namely referring to that in data beats, hready_out signal drags down.
Write operation when clap and by write become read first count---writing of-Yin SRAM is that order (comprising address, read-write) data complete together, and AHB to be points two bats (first order bat, then data beats) complete.So data line directly draws to SRAM, but address wire will use the bus address of a bat, namely deposits the bus address of a bat, so when clapping, write operation refers to that the data beats of ahb bus write operation or the write operation of SRAM are when clapping (because only needing a bat); Become read-write when the first count read refers to continued operation clap by writing the read command become when reading by writing, the continued operation of ahb bus has the concept of flowing water, by write change read time, write data beats and clap with read command and overlap, SRAM uses the address of depositing a bat and writes data and completes write operation.Read also to be the condition that hready_out signal drags down by writing to become, the read operation of bus needs time delay to complete.
Figure 4 shows that four conditions that hready_out signal drags down:
1. hsel signal rising edge, because when bus first count initiates transmission, from bus provide address to hrdata feed back to data will inevitably experience from sram_rdata to hrdata one clap time delay, drag down to declare that data are unripe so need hready_out signal.So no matter whether have forecasting mechanism, next bat hready_out signal of hsel signal rising edge all needs to drag down (as shown in Figure 1 and Figure 2).
2. hwrite signal negative edge, represents bus behavior and reads by writing change.Read to be that first count is read by writing change, namely the sequential that first count is read needs the bat time delay that hready_out signal drags down to offset from sram_rdata to hrdata.
3. sram_wr_en signal negative edge, represents SRAM behavior and reads by writing change.Because the bus address that during write operation, the address of SRAM uses to clap, namely the now bus read command cycle is that SRAM really carries out write operation, so sram_wr_en more late than hwrite one claps, the address of reading of corresponding SRAM is also the bus address using to clap, and still needs the bat time delay that hready_out signal drags down to offset from sram_rdata to hrdata.
4. arsis read operation is miss, when the predicted address of a upper clock period and the bus address of present clock period inconsistent, namely predict miss, then represent the data that SRAM reads in advance incorrect, become first and read because of current and need hready_out signal and drag down to offset one clap time delay from sram_rdata to hrdata.
The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (8)
1. the high speed Biodge device of SRAM on ahb bus access sheet, it is characterized in that: comprise register and add a counter, during write operation, the SRAM address obtained after a bat is deposited through register in access ahb bus address, namely goes up the ahb bus address of a clock period; During read operation, return bat in read operation data, access ahb bus address is through adding the predicted address obtained after a counter adds a counting, and do not complete bat in the transmission of read operation data, ahb bus address is SRAM address, namely accesses current ahb bus address.
2. a kind of ahb bus according to claim 1 accesses the high speed Biodge device of SRAM on sheet, it is characterized in that: during write operation, at write operation when bat and by writing the first count becoming and read, the SRAM address obtained after a bat is deposited through register in access ahb bus address, namely goes up the ahb bus address of a clock period.
3. a kind of ahb bus according to claim 2 accesses the high speed Biodge device of SRAM on sheet, it is characterized in that: described write operation is when clapping as the data beats of ahb bus write operation or the write operation of SRAM are when clapping; Describedly become the first count read into read-write when ahb bus accesses continued operation clap by writing the read command become when reading by writing.
4. a kind of ahb bus according to claim 1 and 2 accesses the high speed Biodge device of SRAM on sheet, it is characterized in that: the transmission of described read operation data does not complete and claps is data beats when hready_out signal drags down, and the condition that described hready_out signal drags down is: be in hsel signal rising edge, hwrite signal negative edge, sram_wr_en signal negative edge and arsis read operation miss time.
5. ahb bus described in a claim 1 accesses the method for work of the high speed Biodge device of SRAM on sheet, it is characterized in that: during write operation, the SRAM address obtained after a bat is deposited through register in access ahb bus address, namely goes up the ahb bus address of a clock period; During read operation, return bat in read operation data, access ahb bus address is through adding the predicted address obtained after a counter adds a counting, and do not complete bat in the transmission of read operation data, ahb bus address is SRAM address, namely accesses current ahb bus address.
6. a kind of ahb bus according to claim 5 accesses the method for work of the high speed Biodge device of SRAM on sheet, it is characterized in that: during write operation, at write operation when bat and by writing the first count becoming and read, the SRAM address obtained after a bat is deposited through register in access ahb bus address, namely goes up the ahb bus address of a clock period.
7. a kind of ahb bus according to claim 6 accesses the method for work of the high speed Biodge device of SRAM on sheet, it is characterized in that: described write operation is when clapping as the data beats of ahb bus write operation or the write operation of SRAM are when clapping; Describedly become the first count read into read-write when ahb bus accesses continued operation clap by writing the read command become when reading by writing.
8. the method for work of the high speed Biodge device of SRAM on a kind of ahb bus access sheet according to claim 5 or 6, it is characterized in that: the transmission of described read operation data does not complete and claps is data beats when hready_out signal drags down, and the condition that described hready_out signal drags down is: be in hsel signal rising edge, hwrite signal negative edge, sram_wr_en signal negative edge and arsis read operation miss time.
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| CN109783933A (en) * | 2019-01-14 | 2019-05-21 | 浙江大学 | A kind of bridging method of ahb bus access on piece SRAM |
| CN109800193A (en) * | 2019-01-14 | 2019-05-24 | 浙江大学 | A kind of bridge-set of ahb bus access on piece SRAM |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
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| CN116049047A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | EEPROM access structure and access method |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109656626A (en) * | 2018-12-11 | 2019-04-19 | 中国航空工业集团公司西安航空计算技术研究所 | One kind being based on ahb bus SD card data from method for carrying and device |
| CN109656626B (en) * | 2018-12-11 | 2022-05-17 | 中国航空工业集团公司西安航空计算技术研究所 | SD card data self-carrying method and device based on AHB bus |
| CN109783933A (en) * | 2019-01-14 | 2019-05-21 | 浙江大学 | A kind of bridging method of ahb bus access on piece SRAM |
| CN109800193A (en) * | 2019-01-14 | 2019-05-24 | 浙江大学 | A kind of bridge-set of ahb bus access on piece SRAM |
| CN109800193B (en) * | 2019-01-14 | 2020-07-28 | 浙江大学 | Bridging device of SRAM on AHB bus access chip |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112416823B (en) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN115114190A (en) * | 2022-07-20 | 2022-09-27 | 上海合见工业软件集团有限公司 | SRAM data reading system based on prediction logic |
| CN115114190B (en) * | 2022-07-20 | 2023-02-07 | 上海合见工业软件集团有限公司 | SRAM data reading system based on prediction logic |
| CN116049047A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | EEPROM access structure and access method |
| CN116049047B (en) * | 2022-12-30 | 2024-04-12 | 成都电科星拓科技有限公司 | EEPROM access method |
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