CN100458973C - High speed streamline long-time-delay multi-port SRAM quick access method - Google Patents
High speed streamline long-time-delay multi-port SRAM quick access method Download PDFInfo
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Abstract
This invention discloses a quick access method for a long time delay multi-port SRAM in a high speed pipeline providing a quick access method to the multi-port SRAM including designing a set of multi-port SRAM access control logic composed of a clock generating circuit, a SRAM port selector, a SRAM storage body and an output register to reduce data access delay effectively and increase the storage bandwidth.
Description
Technical field
The present invention relates to the access method of multiport static RAM SRAM (Static Random AccessMemory), especially be applied to the access method of the long delay random access memory in the high primary frequency deep stream waterline.
Background technology
Storer is one of core component of computing machine, and its performance is directly connected to the height of whole computer system performance.Design of memory systems is one of key issue of Computer Architecture design all the time.For a long time, because there is the gap on the huge speed in the unbalancedness of development between processor and the main memory.In order to solve the problem of storage bottleneck, modern computer all is provided with the cache memory Cache that one or more levels is made up of SRAM between processor and main memory.Cache has great significance for improving whole performance of computer systems, is indispensable parts.The storage system of pipeline organization is hidden access delay effectively by with the request of access streamlined, significantly improves the memory bandwidth of system, so be widely adopted.
Although SRAM is with respect to the other types storer, speed is faster, the access time is nanosecond (Nanosecond, ns) level, but from practical application, still can not satisfy the requirement that the high primary frequency streamline postpones memory access, have only several nanoseconds at zero point as the clock period of the streamline more than the Gigahertz, littler 1～10 times than the access delay of SRAM.Therefore, the SRAM access delay directly influences the performance of whole streamline to a great extent, and the method that the SRAM access speed is accelerated in research has great significance.
At present, the universal method of visit SRAM has in high-speed flow line: (1) is waited for and is carried out other operations again after the SRAM accessing operation is finished, and this is at present domestic generally use.The each visit of this method all needs to wait for several clock period, can not connected reference, and poor-performing; (2) with the ratio increase several times of SRAM data width by access cycle and system clock cycle, once visit can be read the data of a plurality of requests.This method can be alleviated the pressure of data access in the streamline at the address of adjacent visit consecutive hours, but in actual applications, owing to be difficult to guarantee the neighbor address visit, so the actual bandwidth utilization factor is not high.For example, in CPU Cache design, the address of adjacent visit is A, B, if B is not equal to A+1, the data of B address just can not make full use of the data of being looked ahead in visit A address so, therefore, still need to suspend the access stream waterline; (3) duplicate a plurality of SRAM, increase the visit data width, this method is similar to second method, belongs to second method in essence, and needs to increase a large amount of extra resources.Therefore, the defective that how to solve said method simultaneously seems particularly important in Project Realization.
SRAM has two kinds of single port SRAM and multi-port SRAMs.Multi-port SRAM is compared with single port SRAM, and access delay is long slightly, but multi-port SRAM has many cover read-write control circuits to same memory bank, can be the relation that walks abreast, be regardless of primary and secondary between each port, and promptly each port all can be carried out read-write operation; Also can be A distinction should be made between what is primary and what is secondary relation, promptly certain port can be carried out read-write operation and other port can only be carried out read operation.If can make full use of the access characteristics of a plurality of ports, then can realize resources duplication, make visit overlapping, reach the purpose that reduces access delay.Therefore research is significant to the overall performance that promotes streamline to the quick access method of multi-port SRAM.
Summary of the invention
The technical problem to be solved in the present invention is: at the long problem of multi-port SRAM visit time-delay in the high primary frequency streamline, utilize the application characteristic of multi-port SRAM, a kind of quick access method to multi-port SRAM is provided, make SRAM access stream aquation, the hiding data access delay, fully the memory bandwidth of exploitation multi-port SRAM improves the access efficiency of data, thereby promotes the overall performance of streamline significantly.
Technical scheme of the present invention is: the multi-port SRAM access control logic that design one cover clock generation circuit, SRAM port selector, SRAM memory bank and four parts of outlet registers group are formed, adopt this access control logic that multi-port SRAM is conducted interviews, improve data access efficiency.
The clock for a long time that clock generation circuit is based on phaselocked loop generates parts, and its method for designing is: it is made up of one or more phaselocked loops, and as input, output n (n is a SRAM port number) the individual cycle is n*T with system clock CLK_S
Clk_SSame frequency clock signal clk 1, CLK2 ... CLKn.The phase place of this n clock signal differs a system clock cycle time T successively
Clk_S
The major function of SRAM port selector is to select the SRAM available port and the output port useful signal is set, and its method for designing is: it is made up of idle port decision logic and n level output data useful signal station.Each grade output data useful signal station is made up of n register, corresponds respectively to n port of SRAM memory bank, is used to represent whether this port data is effective.Each rising edge at system clock CLK_S, the idle port decision logic is to each port clock signal clk 1 of SRAM, CLK2 ... CLKn samples, obtain idle port i (1≤i≤n) according to the clock status that samples, because the phase relation between the port clock is fixed, when learning the phase value of an a certain moment port clock, other port clocks phase place has at the moment also just been determined thereupon, all has been n*T when the clock period of each port clock
Clk_S, and phase place differs a system clock cycle T successively
Clk_SThe time, there is and have only a port clock rising edge saltus step to occur in the same system clock cycle, corresponding port is exactly an idle port with it; If write request (RW is 0), what the idle port decision logic was put idle port i writes enable signal Writei (i is a port numbers), the working port i of SRAM memory bank writes request msg Data in the SRAM memory bank under the driving of writing enable signal Writei; If read request (RW is 1), the idle port decision logic generates corresponding output data useful signal DValidi
1(i is a port numbers) writes the 1st station of exporting the useful signal station, and after a system clock cycle, it (is output data useful signal DValidi that the output data useful signal imports into to second station from first stop
2Be 1), transmit successively, behind n the system clock cycle, the outlet that this output useful signal arrives the SRAM port selector (is output data useful signal DValidi
nBe 1), at this moment since clock period of SRAM port be n*T
Clk_S, corresponding idle SRAM port i sampled output data among the output port i and to deposit, with output data useful signal DValidi after a port clock period (being n system clock cycle)
nDeliver to the outlet registers group together.
SRAM memory bank logical organization in SRAM memory bank and the classic method is basic identical, just has more access port.
The outlet registers group is used to deposit the valid data that SRAM memory bank port flows out, and its method for designing is: it is made of output register Reg_Out, the temporary formation Tmp_fifo of output data, Fifo steering logic and two MUX " MUX " and " the 2nd MUX ".The one MUX imports as data with n output port data of SRAM memory bank, with n output data useful signal DValid1 of SRAM port selector
n, DValid2
nDValidn
nAs the control input, select effective port data to deliver to the input end of Tmp_fifo; The Fifo steering logic is with the output data useful signal DValid1 of SRAM port selector
n, DValid2
nDValidn
nAs the control input, it is responsible for producing writing enable signal WrEn and reading the dummy status signal Fifo_Empty of enable signal RdEn and formation of the temporary formation Tmp_fifo of output data, and uses internal counter cnt that the valid data number of Tmp_fifo is counted; The temporary formation Tmp_fifo of output data has the n-1 item, it is imported as data with effective port data that a MUX selects, write enable signal WrEn and read enable signal RdEn with what the Fifo steering logic was exported, in order data are kept in and read as the control input; The 2nd MUX imports as data with n the output port data of temporary formation Tmp_fifo output data of output data and SRAM, with the output data useful signal DValid1 of SRAM port selector
n, DValid2
nDValidn
nTemporary formation Tmp_fifo dummy status signal Fifo_Empty imports as control with output data, selects valid data to deliver to output register Reg_Out; The Reg_Out bit wide is identical with the data bit width of each visit, also identical with each SRAM visit data bit wide, it is imported as data with the output data of the 2nd MUX, as the control input, when not stopping, upgrades by streamline the content of register with pipeline stall signal Stall with the output data of the 2nd MUX.
The one MUX output data writes the temporary formation Tmp_fifo of output data need satisfy one of following two conditions: (1) pipeline stall signal Stall effectively and have an output data useful signal DValidi
n(1≤i≤n) effective; (2) streamline does not pause (being that Stall is 0), but output data is kept in formation Tmp_fifo non-NULL (being that Fifo_Empty is 0) and had output data useful signal DValidi
n(1≤i≤n) effective.Therefore the formation logic of writing enable signal WrEn of the temporary formation Tmp_fifo of output data is:
Wherein, Fifo_Empty effectively is that the valid data counter cnt in the Fifo steering logic is 0, that is:
When streamline does not stop (being that Stall is 0) and during the temporary formation Tmp_fifo non-NULL (being that Fifo_Empty is 0) of output data, temporary formation to read enable signal RdEn effective, that is:
The formation logic of counter cnt is:
INC＝cnt+1
DEC＝cnt-1
When writing enable signal WrEn when effective, the temporary formation Tmp_fifo of output data writes the valid data of MUX output on the head of formation, when reading enable signal RdEn when effective, the temporary formation Tmp_fifo of output data delivers to the data of formation afterbody the output terminal of the temporary formation Tmp_fifo of output data.
When the temporary formation Tmp_fifo output data of output data was effective, the 2nd MUX preferentially selected the output data of the temporary formation Tmp_fifo of output data.The selection logic of the 2nd MUX is: if the temporary formation Tmp_fifo formation non-NULL (being that Fifo_Empty is 0) of output data selects output data to keep in the output data of formation Tmp_fifo; If the temporary formation Tmp_fifo formation of output data is empty (being that Fifo_Empty is 1), then select effective output data of SRAM port.
When streamline did not stop, then the output data of the 2nd MUX was upgraded the content of output register Reg_Out continuously, used for outside.
Adopt the multi-port SRAM access control logic to be to the process that SRAM conducts interviews:
1. clock generation circuit as input, is exported n clock signal clk 1, CLK2 with CLK_S ... CLKn, as the work clock of each read/write port of SRAM memory bank, and as the input signal of SRAM port selector.(1≤i≤n) drives down and works each port, and the unified logic of other parts is driven by CLR_S except that the SRAM memory bank at the CLKi of correspondence;
2. when external request Rqt_Valid is effective, the SRAM port selector is converted into the exterior read-write request read-write operation signal of SRAM, obtain available idle port according to the idle port decision logic, if write request (being that RW is 0), put SRAM the i port write enable signal Writei (i be idle port number); If read request (being that RW is 1), put the output data useful signal DValidi of respective free port
1, write the 1st station of exporting the useful signal station, after a system clock cycle, it (is output data useful signal DValidi that the output data useful signal imports into to second station from first stop
2Be 1), transmit successively, behind n the system clock cycle, the outlet that this output useful signal arrives the SRAM port selector (is output data useful signal DValidi
nBe 1).
3.SRAM memory bank all has a working port at each system clock cycle, (1≤i≤n) input control signal is judged when Writei is effective, writes request msg Data in the memory bank working port i; When Writei is invalid, the data corresponding with request address are read, after a port clock period (being n system clock cycle), output data is sampled among the output port i and deposits, the output data useful signal DValidi that this moment is corresponding
nAlso just in time arrive the outlet of SRAM port selector, deliver to the outlet registers group with output data.
4. the outlet registers group is imported as data with n port data of SRAM memory bank, with the output data useful signal DValid1 of SRAM port selector output
n, DValid2
nDValidn
nImport as control with pipeline stalling signal Stall, when the effective or temporary formation Tmp_fifo of Stall signal non-NULL, the output data of SRAM memory bank is saved among the temporary formation Tmp_fifo; When output data is kept in formation Tmp_fifo non-NULL, the 2nd MUX selects the output data of the temporary formation Tmp_fifo of output data and is sent to outlet register Reg_Out, when the temporary formation Tmp_fifo of output data was sky, the 2nd MUX selected the output data of SRAM memory bank also to be sent to outlet register Reg_Out.
Adopt the present invention can reach following technique effect:
Effectively reduce data access delay, improve memory bandwidth.If be t the access cycle of SRAM
AC, the clock period of system is T
Clk_S, for a continuous a read request, according to traditional SRAM access method, to read request to the time of obtaining last read data be t from sending first
R=a*t
AC, and adopt the present invention to carry out SRAM visit t
R=(n+a) * T
Clk_S(the 1st request of sending out needs just can obtain data behind n system clock cycle).Than traditional access method, the speed-up ratio E that the present invention obtains is:
As a during, E ≈ t is arranged much larger than n
AC/ T
Clk_SFor long delay SRAM, t
ACGreater than t
Clk_s, use the present invention to conduct interviews and obviously be better than conventional access methods.
Description of drawings
Fig. 1 is the building-block of logic of first kind and the second kind used access circuit of SRAM access method in the background technology.
Fig. 2 is a multi-port SRAM access control logic synoptic diagram of the present invention.
Fig. 3 is each port clock frequency and the phase diagram that has adopted four port SRAMs of the present invention.
Embodiment
Fig. 1 is the building-block of logic of first kind and the second kind used access circuit of SRAM access method in the background technology, and this access circuit is made up of SRAM memory bank, idling cycle decision circuitry and output register.SRAM memory bank (generally being single port) is preserved the outside data that write; The idling cycle decision circuitry judges according to the state of current latent period counter whether SRAM is in busy condition, if be not in a hurry then can serve new external request; Output register is deposited the data of SRAM output when output data is effective, returns to the external users.Each visit, idling cycle decision circuitry control visit is waited for, waits for and can not serve new request therebetween, has greatly influenced the overall access performance.
Fig. 2 is a multi-port SRAM access control logic synoptic diagram of the present invention.The multi-port SRAM access control logic comprises that phase clock produces circuit, SRAM port selector, SRAM memory bank and four parts of outlet registers group.
Phase clock produces circuit to be made up of one or more phaselocked loops, and as input, output n (n is a SRAM port number) the individual cycle is n*T with system clock CLK_S
Clk_SSame frequency clock signal.The phase place of this n clock signal differs a system clock cycle time T successively
Clk_S
The SRAM port selector is made up of idle port decision logic and n level output data useful signal station.
Each grade output data useful signal station is made up of n register, corresponds respectively to n port of memory bank, is used to represent whether this port data is effective.At each rising edge of system clock CLK_S, the idle port decision logic is to each port clock signal clk 1 of SRAM, CLK2 ... CLKn samples, and obtains idle port i according to the clock status that samples; If write request (RW is 0), what port selector was put idle port i writes enable signal Writei (i is a port numbers), and the working port i of SRAM memory bank writes request msg Data in the SRAM memory bank under the driving of writing enable signal Writei; If read request (RW is 1), port selector generates corresponding output data useful signal DValidi
1(i is a port numbers) writes the 1st station of exporting the useful signal station, and after a system clock cycle, it (is output data useful signal DValidi that the output data useful signal imports into to second station from first stop
2Be 1), transmit successively, behind n the system clock cycle, the outlet that this output useful signal arrives port selector (is output data useful signal DValidi
nBe 1), at this moment since clock period of SRAM port be n*T
Clk_S, corresponding idle SRAM port i sampled output data among the output port i and to deposit, with output data useful signal DValidi after a port clock period (being n system clock cycle)
nDeliver to the outlet registers group together.The state that cooperates external request useful signal Rqt_valid, request type RW and pipeline stall signal Stall again, can correspondingly generate the output data useful signal DValidi (1≤i≤n) of each port output, SRAM for the n port, output data useful signal DValidi need deposit the n station, is respectively DValidi
1, DValidi
2DValidi
n, this n station register is not subjected to the Stall signal controlling, and each system clock cycle useful signal all is updated to next register, arrives the outlet of SRAM port selector behind n system cycle, and registers group is used for export.
SRAM memory bank logical organization in SRAM memory bank and the classic method is basic identical, just has more access port.
The outlet registers group is made of the temporary formation Tmp_fifo of output register Reg_Out, output data, Fifo steering logic and two MUX the one MUX and the 2nd MUX.The one MUX imports as data with n output port data of SRAM memory bank, with n output data useful signal DValid1 of SRAM port selector
n, DValid2
nDValidn
nAs the control input, select effective port data to deliver to the input end of the temporary formation Tmp_fifo of output data; The Fifo steering logic is with the output data useful signal DValid1 of SRAM port selector
n, DValid2
nDValidn
nAs the control input, it is responsible for producing writing enable signal WrEn and reading the dummy status signal Fifo_Empty of enable signal RdEn and formation of the temporary formation Tmp_fifo of output data, and uses internal counter cnt that the valid data number of the temporary formation Tmp_fifo of output data is counted; The temporary formation Tmp_fifo of output data has the n-1 item, it is imported as data with effective port data that a MUX selects, write enable signal WrEn and read enable signal RdEn with what the Fifo steering logic was exported, in order data are kept in and read as the control input; The 2nd MUX imports as data with the output data of the temporary formation Tmp_fifo of output data and n the output port data of SRAM, with the output data useful signal DValid1 of SRAM port selector
n, DValid2
nDValidn
nTemporary formation Tmp_fifo dummy status signal Fifo_Empty imports as control with output data, selects valid data to deliver to output register Reg_Out; Output register Reg_Out bit wide is identical with the data bit width of each visit, also identical with each SRAM visit data bit wide, it is imported as data with the output data of the 2nd MUX, as the control input, when not stopping, upgrades by streamline the value of register with pipeline stall signal Stall with the output data of the 2nd MUX.
Fig. 3 is each port clock frequency and the phase diagram that adopts four port SRAMs of the present invention's design.The port clock of four port SRAMs and the frequency relation of system clock are f
s: f
Ram=1: 4, each port clock phase differs a system clock cycle time T successively
Clk_SAnd all staggering with the system clock rising edge, (tp must be greater than the address Time Created of RAM for identical time span tp, to guarantee that ram port can sample stable data), promptly first rising edge of CLK_A falls behind tp than first rising edge of CLK_S as shown in the figure, first rising edge of CLK_B falls behind tp than second rising edge of CLK_S, first rising edge of CLK_C falls behind tp than the 3rd rising edge of CLK_S, and first rising edge of CLK_D falls behind tp than the 4th rising edge of CLK_S.Because the phase relation between the port clock is fixed, when learning the phase value of an a certain moment port clock, other port clocks phase place has at the moment also just been determined thereupon.As can be seen from the figure CLK_S is the circulation of four kinds of out of phase values to the sampled value of CLK_A, is made as a
1, a
2, a
3, a
4, by the phase value a of CLK_A
1Can obtain the phase value of other port clocks of synchronization, availability vector is expressed as: (a
1, b
1, c
1, d
1); In like manner can obtain the vector value under other situations: (a
2, b
2, c
2, d
2) (a
3, b
3, c
3, d
3), (a
4, b
4, c
4, d
4).It can also be seen that from figure has and has only a port clock rising edge saltus step to occur in the same system clock cycle, corresponding port is exactly an idle port with it.The 1st request of sending out need just can be obtained required data after 4 clap.
Following table is to adopt the present invention that four port SRAMs are conducted interviews for the needed system clock cycle number of continuous request with respect to background technology first method and the needed system clock cycle number of second method comparison sheet.All requests are read request in the table.For first request, the access process of three kinds of methods is identical, all needs four systems clock period T
Clk_SFor second request, the background technology first method can only serial access, so need other 4 clock period to handle, needs 8 clock period altogether; The background technology second method is at the request address consecutive hours, because the data of second request have got in first request of processing, do not need the extra cycle, so only need 4 clock period altogether, and when request address is discontinuous, the background technology second method still needs other 4 clock period to handle second request, so need 8 clock period altogether; When using method of the present invention to conduct interviews, because request is that flowing water is handled, so second request handled the 2nd clock period, its result can obtain the 5th clock period, therefore needed 5 clock period altogether.The rest may be inferred, can draw under other situations three kinds of needed clock periodicities of distinct methods.As seen from the table, when the number of continuous request during much larger than the port number, access time of the present invention obviously is better than the background technology first method, if request address is discontinuous, access time so of the present invention also obviously is better than the background technology second method, if request address is continuous, the access time of background technology second method is the shortest, but in the practical application, the totally continuous situation of request address is seldom.Therefore the present invention has important practical sense to the access speed that improves SRAM.
Required periodicity comparison sheet when the present invention and background technology practical application
| Continuous read request number | Adopt periodicity required for the present invention | First kind of required periodicity of access method of background technology | Second kind of required periodicity of access method of background technology |
| 1 request | 4 | 4 | 4 |
| 2 requests | 5 | 8 | The address is continuous: 4 addresses are discontinuous: 8 |
| 4 requests | 7 | 16 | The address is continuous: 4 addresses are discontinuous: 16 |
| 128 requests | 131 | 512 | The address is continuous: 128 addresses are discontinuous: 512 |
Claims (3)
1. the quick access method of long-time-delay multi-port SRAM in the high-speed flow line, method is design one a cover access control logic, adopt this access control logic that SRAM is conducted interviews, it is characterized in that described access control logic is the multi-port SRAM access control logic, it is made up of clock generation circuit, SRAM port selector, SRAM memory bank and four parts of outlet registers group; The method for designing of these four parts is respectively:
1.1 the method for designing of clock generation circuit is: it is made up of one or more phaselocked loops, and as input, exporting n cycle is n*T with system clock CLK_S
Clk_SSame frequency clock signal, the phase place of this n clock signal differs a system clock cycle time T successively
Clk_S, n is a SRAM port number;
1.2SRAM the method for designing of port selector is: it is made up of idle port decision logic and n level output data useful signal station; Each grade output data useful signal station is made up of n register, corresponds respectively to n port of SRAM memory bank, is used to represent whether this port data is effective; At each rising edge of system clock CLK_S, the idle port decision logic is to each port clock signal clk 1 of SRAM, CLK2 ... CLKn samples, and obtains idle port i according to the clock status that samples;
1.3 the method for designing of outlet registers group is: it is made of output register Reg_Out, the temporary formation Tmp_fifo of output data, Fifo steering logic and two MUX " MUX " and " the 2nd MUX ";
1.4 adopt the multi-port SRAM access control logic to be to the process that SRAM conducts interviews:
1.4.1 clock generation circuit as input, is exported n clock signal clk 1, CLK2 with CLK_S ... CLKn, each port is worked under the CLKi of correspondence drives, and the unified logic of other parts is driven by CLR_S except that the SRAM memory bank;
When 1.4.2 external request Rqt_Valid is effective, the SRAM port selector is converted into the exterior read-write request read-write operation signal of SRAM, obtain available idle port according to the idle port decision logic, if write request, put SRAM the i port write enable signal Writei; If read request, put the output data useful signal DValidi of respective free port
1, write the 1st station of exporting the useful signal station, after a system clock cycle, it is DValidi that the output data useful signal imports into to second station from first stop
2Be 1, transmit successively that behind n the system clock cycle, the outlet that this output useful signal arrives the SRAM port selector is DValidi
nBe 1;
1.4.3SRAM the working port i of memory bank judges input control signal, when Writei is effective, request msg Data is write in the memory bank; When Writei is invalid, the data corresponding with request address are read, after a port clock period was n system clock cycle, output data was sampled among the output port i and deposits, the output data useful signal DValidi that this moment is corresponding
nAlso just in time arrive the outlet of SRAM port selector, deliver to the outlet registers group with output data; Wherein, 1≤i≤n;
1.4.4 the outlet registers group is imported as data with n output port data of SRAM memory bank, with the output data useful signal DValid1 of SRAM port selector output
n, DValid2
n... DValidn
nWith pipeline stalling signal Stall as control input, during the temporary formation Tmp_fifo non-NULL of effective or output data, the output data of SRAM memory bank is saved among the temporary formation Tmp_fifo of output data when the Stall signal; When output data is kept in formation Tmp_fifo non-NULL, the 2nd MUX selects the output data of temporary formation Tmp_fifo and is sent to outlet register Reg_Out, when the temporary formation Tmp_fifo of output data was sky, the 2nd MUX selected the output data of SRAM memory bank also to be sent to outlet register Reg_Out.
2. the quick access method of long-time-delay multi-port SRAM in a kind of high-speed flow line as claimed in claim 1, it is characterized in that a described MUX imports as data with n output port data of SRAM memory bank, with n output data useful signal DValid1 of SRAM port selector
n, DValid2
n... DValidn
nBe the control input, select effective port data to deliver to the input end of the temporary formation Tmp fifo of output data; The temporary formation Tmp_fifo of output data has the n-1 item, and it is imported as data with effective port data that a MUX selects, with the output data useful signal DValid1 of SRAM port selector
n, DValid2
n... DValidn
nBe the control input; The Fifo steering logic is responsible for producing writing enable signal WrEn and reading the dummy status signal Fifo_Empty of enable signal RdEn and formation of the temporary formation Tmp_fifo of output data, and uses internal counter cnt that the valid data number of the temporary formation Tmp_fifo of output data is counted; The 2nd MUX imports as data with n the output port data of temporary formation Tmp_fifo output data of output data and SRAM, with the output data useful signal DValid1 of SRAM port selector
n, DValid2
n... DValidn
nBe the control input with the temporary formation Tmp_fifo dummy status signal Fifo_Empty of output data, select valid data to deliver to output register Reg_Out; Output register Reg_Out bit wide is identical with the data bit width of each visit, also identical with each SRAM visit data bit wide, it is imported as data with the output data of the 2nd MUX, as the control input, when not stopping, upgrades by streamline the content of register with pipeline stall signal Stall with the output data of the 2nd MUX.
3. the quick access method of long-time-delay multi-port SRAM in a kind of high-speed flow line as claimed in claim 1 or 2 is characterized in that the formation logic of writing enable signal WrEn of the temporary formation Tmp_fifo of output data is:
WrEn＝(DValid1∨DValid2∨····∨DValidn)∧(Fifo_Empty∨Stall)；
Wherein, Fifo Empty effectively is that the valid data counter cnt in the Fifo steering logic is 0, that is: Fifo_Empty=Cnt[i] ... ∨ cnt[0]
The formation logic of reading enable signal RdEn of the temporary formation Tmp_fifo of output data is:
RdEn＝(Fifo_Empty∨Stall)；
The formation logic of counter cnt is:
INC＝cnt+1
DEC＝cnt-1
cnt[k]＝(WrEn∧RdEn∧INC[k])∨(WrEn∧RdEn∧DEC[k])；(0≤K≤i)。
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| CN101566941B (en) * | 2009-06-03 | 2013-08-07 | 北京中星微电子有限公司 | FIFO storage unit based on static random access memory (SRAM) |
| US8959469B2 (en) | 2012-02-09 | 2015-02-17 | Altera Corporation | Configuring a programmable device using high-level language |
| CN103219037B (en) * | 2013-04-22 | 2016-01-20 | 中国科学院半导体研究所 | The on-chip memory of multi-port read-write |
| CN106681940B (en) * | 2016-12-15 | 2018-06-22 | 建荣半导体（深圳）有限公司 | Simulate Multiport approach, its device, memory, window processing module and electronic equipment |
| CN109271333B (en) * | 2017-07-17 | 2022-03-01 | 深圳市中兴微电子技术有限公司 | SRAM control method, controller and control system |
| CN113778335B (en) * | 2021-09-08 | 2024-03-08 | 山东华芯半导体有限公司 | Control method of multi-port low-delay access SRAM group in SSD master control |
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