CN1240299A

CN1240299A - Assembly line double-port integrated circuit memory

Info

Publication number: CN1240299A
Application number: CN 99108672
Authority: CN
Inventors: 阿伦·S·罗森斯坦; 斯科特·乔治·诺格尔
Original assignee: Motorola Inc
Current assignee: NXP USA Inc
Priority date: 1998-06-23
Filing date: 1999-06-22
Publication date: 2000-01-05
Anticipated expiration: 2019-06-22
Also published as: CN1192390C

Abstract

The present invention provide a pipelined dual port integrated circuit memory (20) including an array (21) of static random access memory (SRAM) cells, wherein each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). Each port's access is performed synchronously with respect to a corresponding clock signal. The two clock signal signals are asynchronous with respect to each other. When access requests are received from both ports substantially simultaneously, an arbitration circuit (24) determines which port receives priority. The port which receives priority accesses the array (21) first. The arbitration circuit (24) ensures that substantially simultaneous access requests are serviced sequentially and occur within a single cycle of a corresponding clock signal.

Description

Assembly line double-port integrated circuit memory

Relate generally to storer of the present invention, and relate to dual-ported memory especially.

Dual-ported memory can be widely used in multiple application.They have specific use in the communications field and multicomputer system.In multicomputer system, a processor can write array to data, and another processor can be read data.Especially, two-port RAM s is particularly suitable for being known as the communications applications of ATM(Asynchronous Transfer Mode).In an ATM exchange, mass data must transmit between 2 treatment facilities.Another communications applications is IEEE 802.3 (known under the obtainable trade mark " Ethernet " from the Digital Equipment Corporation usually) communications router of a standard.The application of these types has not expensive but comprise that the dual-ported memory of a big array has a kind of demand.

Traditionally, a kind of double-port random incoming memory (RAMs) that makes up in two kinds of technology of use.In first kind of technology, each memory cell is real dual-port, thereby needs 8 transistors.Because big dual port memory cell makes array itself very big, and is very expensive based on the integrated circuit memory of this technology.Second kind of technology utilization has the standard single port static RAM (SRAM) unit of a subregion array.If 2 ports wish to insert identical subregion simultaneously, one during these insert so must be delayed.Along with the growth of number of partitions, the possibility that clashes reduces, but because extra decoding and collision detection circuit, expense increases.What need like this, is one and uses traditional single port sram cell but simultaneously not expensive and big fast two-port RAM.These demands can be satisfied by the present invention, and the features and advantages of the present invention further describe accompanying drawing and associated description thereof.

Fig. 1 illustrates to constitute part block scheme and the partial logic figure according to assembly line double-port integrated circuit memory of the present invention.

Fig. 2 illustrates to constitute the part block scheme and the partial logic figure of a part of the array of the Fig. 1 that comprises single port static RAM (SRAM) unit.

Fig. 3 illustrates the part block scheme and the partial logic figure of arbitration circuit of pie graph 1.

Fig. 1 illustrates to constitute part block scheme and the partial logic figure according to storer 20 of the present invention.Storer 20 is integrated circuit dual-port static incoming memories (SRAM) at random, generally comprises 21, one arbitration circuits 24 of a single port SRAM array,

weld zone

26 and 28, one importations 30 and an output 50.Array 21 has an input end that is used to receive a N bit addresses, and a control entry terminal that is used for received signal W is used for the input end of clock that reception is labeled as the clock signal of " CLKX " and " CLKY ", and one is used for reception and is labeled as " D _IN" the data input pin of M bit data value, one is used to provide and is labeled as " D _OUT" the output terminal of N bit data value.Array 21 comprises a demoder square frame 22 and a write control circuit 23 simultaneously.

20 pairs of 2 clock signals that are labeled as " CLOCK (X) " and " CLOCK (Y) " that receive on

weld zone

26 and 28 respectively of storer respond.Arbitration circuit 24 has a first input end of linking on the weld zone 26 that is used to receive CLOCK (X), link second input end on the weld zone 28 that is used to receive CLOCK (Y) and be used to provide signal CLKX and CLKY to the output terminal of array 21, an output terminal that is used to provide the control signal that is labeled as " XYSEL ", an output terminal that is used to provide the output terminal of the signal that is labeled as " QCLKX " and is used to provide the signal that is labeled as " QCLKY ".

Importation 30 generally comprises weld zone 31-36, D flip-flop 40-45 and multiplexer (MUXes) 46-48.Weld zone 31 receives a N bit addresses signal that is labeled as " ADD (X) ".Weld zone 32 receives a N bit addresses signal that is labeled as " ADD (Y) ".Weld zone 33 receives a write control signal that is labeled as W (X).Weld zone 34 receives a write control signal that is labeled as W (Y).Weld zone 35 receives one and is labeled as " D _IN(X) " M bit input data signal.Weld zone 36 receives one and is labeled as " D _IN(Y) " M Bit data input signal.Be noted that each representative be used to receive address signal separately N weld

zone weld zone

31 and 32 and each representative be used to receive separately D _INThe

weld zone

35 and 36 of the M of a signal weld zone in order to simplify, only is illustrated as a single weld zone in Fig. 1.

Trigger 40 has a D input end of linking weld zone 31, an input end of clock that is used for received signal CLOCK (X), a Q output terminal, and representative receives each address signal of ADD (X) and in N the D flip-flop of each latch address signal one is provided.Trigger 41 has a D input end of linking weld zone 32, an input end of clock that is used for received signal CLOCK (Y), and a Q output terminal, and representative receives each address signal of ADD (Y) and in N the trigger of latch address signal one is provided.Trigger 42 has a D input end of linking weld zone 33, an input end of clock and a Q output terminal that is used for received signal CLOCK (X).Trigger 43 has a D input end of linking weld zone 34, an input end of clock and a Q output terminal that is used for received signal CLOCK (Y).Trigger 44 has a D input end of linking weld zone 35, an input end of clock that is used for received signal CLOCK (X), and a Q output terminal, and represent received signal D _INIn the M of each signal (X) trigger one.Trigger 45 has a D input end of linking weld zone 36, an input end of clock that is used for received signal CLOCK (Y), and a Q output terminal, and represent received signal D _INIn the M of corresponding signal (Y) trigger one.

MUX 46 has a first input end of linking the Q output terminal of trigger 40, link second input end of the Q output terminal of trigger 41, a control input end and an output terminal that is used for received signal XYSEL, and the representative corresponding output that receives each address signal of ADD (X) and ADD (Y) and it is provided as signal ADD to one among N the MUXes of array 21.MUX 47 has a first input end of linking the Q output terminal of trigger 42, link second input end of the Q output terminal of trigger 43, control input end that is used for received signal XYSEL and one are used to provide the output terminal of signal W to array 21.MUX 48 has a first input end of linking the Q output terminal of trigger 44, links second input end of the Q output terminal of trigger 45, and control input end that is used for received signal XYSEL and one are used to provide signal D _INGive the output terminal of array 21, and representative receives D _IN(X) and D _IN(Y) each signal and corresponding output that it is provided are as signal D _INGive among M the MUXes of array 21.

Output 50 generally comprises D flip-flop 51-54, tri-state

buffers

55 and 56 and weld zone 60-64.Trigger 51 has a D input end of linking the output terminal of array 21, an input end of clock that is used for received signal QCLKX, and an output terminal, and represent received signal D _OUTEach signal and in M the trigger of corresponding output one is provided.Trigger 52 has a D input end of linking the Q output terminal of trigger 51, an input end of clock and an output terminal that is used for received signal CLOCK (X), and represent each corresponding to one in one M the trigger in the previous trigger of representing by trigger 51.Trigger 53 has a D input end of linking the D output terminal of array 21, an input end of clock that is used for received signal QCLKY, and an output terminal, and represent received signal D _OUTEach signal and in M the trigger of corresponding output one is provided.Trigger 54 has a D input end of linking the Q output terminal of trigger 53, an input end of clock and an output terminal that is used for received signal CLOCK (Y), and represent each corresponding to one in one M the trigger in the previous trigger of representing by trigger 53.Buffer 55 has a data input pin of linking the Q output terminal of trigger 52, a data output terminal and a control end of linking weld zone 60, and representative is linked one in M corresponding one buffer of trigger 52.Buffer 56 has a data input pin of linking the Q output terminal of trigger 54, an output terminal and a control input end of linking weld zone 63, and representative is linked one in each M the buffer of trigger 54.Weld zone 60 receives an output enable signal that is labeled as " OE (X) " of linking the control input end of buffer 55.The output terminal of buffer 55 is linked in weld zone 61, is used to provide one to be labeled as " DATA _OUT(X) " output signal, and representative is corresponding to one in M the weld zone of each buffer that resembles buffer 55.The output terminal of buffer 56 is linked in weld zone 62, is used to provide one to be labeled as " DATA _OUT(Y) " signal, and representative is linked one in M the weld zone of corresponding one output of buffer 56.Weld zone 63 receives a control end that is labeled as the output enable signal of " OE (Y) " and is linked buffer 56.

At work, storer 20 serves as the static random incoming memory (SRAM) of a complete dual-port.In storer 20, the situation that an access can not take place in the single cycle of its corresponding clock signals can not appear.In addition, storer 20 uses 6 layer transistor SRAM units of a standard, has avoided the special dual port cell that need be associated with another kind of dual-port technology like this.

The access of storer 20 by allowing array 21 these advantages occur realizing in that each port is asynchronous, and wherein each saltus step from low to high that inserts with separately clock signal begins.Like this, as long as signal CLOCK (X) and CLOCK (Y) have a low frequency of maximum frequency than regulation, storer 20 guarantees that all accesses finish in the single cycle of their clock period separately.Especially, dual-port SRAM 20 uses arbitration circuits 24 to guarantee when from low to high a saltus step almost appears in CLOCK (X) and CLOCK (Y) simultaneously, gives access on the X port right of priority.And arbitration circuit 24 is guaranteed can not run into metastable problem for very small amount of crooked (skew) between CLOCK (X) and CLOCK (Y).

Array 21 is energy one-port memory centers with 2 times of accesses of one speed among signal CLOCK (X) or the CLOCK (Y).Usually, storer 20 response external insert request and produce the request that is used to insert array 21.Arbitration circuit 24 is guaranteed to be provided for array 21 than early one in 2 access requests, except inserting the received situation simultaneously of asking almost at 2.In this case, arbitration circuit 24 is authorized X port right of priority.

Especially, arbitration circuit 24 output signal XYSEL indicate whether that X port or Y port have been given and are linked into array 21.In this certain embodiments, the access of logic high representative on the X port, and the access of logic low representative on the Y port.If signal XYSEL is a logic high like this, MUX 46 selects its first input and provides signal ADD (X) to give array 21 as N bit signal ADD.Use demoder 22 to carry out traditional row and column decoding after the array 21 so that signal D to be provided _OUT(it is a read cycle that supposition inserts).Similarly, if arbitration circuit 24 provides the signal XYSEL of a logic low, MUX 46 selects its second input.Signal XYSEL selects corresponding to the MUX 47 of that port of arbitration circuit 24 accord priority and 48 input.In addition, arbitration circuit 24 provides clock signal clk X and CLKY the write control circuit 23 to array 21.Notice that clock signal clk X and CLKY can be replaced by a single clock signal in other embodiments.

Signal QCLKX and QCLKY control the read data path of X and Y port respectively.Signal QCLKX is imported into the input end of clock of trigger 51, and signal QCLKY is imported into the input end of clock of trigger 53.Notice that the data outgoing route comprises that also the next rising edge of using signal CLOCK (X) and CLOCK (Y) respectively imports the

trigger

52 and 54 that adds of data synchronously.

Buffer

55 and 56 is signal " DATA _OUTAnd " DATA (X) " _OUT(Y) " provide conventional three-state control.

Fig. 2 illustrates to constitute the part block scheme and the partial logic figure of a part 70 of the array 21 of the Fig. 1 that comprises one-port memory unit 80.Memory cell 80 is the static RAM (SRAM) unit that insert of the signal activation that is labeled as " WL " by conduction on word line 72, and respectively at paratope line to 74 and 76 differential data signals that produce and be labeled as " BL " and " BL ".Memory cell 80 comprises N NMOS N-channel MOS N (MOS)

transistor

82 and 84 and phase inverter 86 and 88.Transistor 82 has the first electric current utmost point of linking bit line 74, links the grid and the second electric current utmost point of word line 72.Transistor 84 has the first electric current utmost point of linking bit line 76, links the grid and the second electric current utmost point of word line 72.Phase inverter 86 has an input end and the output terminal of linking the second electric current utmost point of transistor 84 of linking the second electric current utmost point of transistor 82.Phase inverter 88 has an input end of an output terminal of linking phase inverter 86 and links an output terminal of the input end of phase inverter 86.

At work, memory cell 80 is logic states because the back-to-back work of

phase inverter

86 and 88 and single port 6 transistor memory cell of stored standard.Notice as institute's description here that the transistorized number in memory cell also comprises access transistor except the transistor that execution is stored.Memory cell 80 is inserted by the starting of word line 72 traditionally.When word line 72 effectively the time,

transistor

82 and 84 beginning conductings are coupled to

bit line

74 and 76 to the content of memory cell as a relatively little differential voltage.The detected subsequently and output of this voltage, during a write cycle time, external circuit provides a big relatively differential voltage to rewrite the content that exists in the memory cell 80 between BL and BL.

Memory cell 80 is different with 8 transistor dual port memory cell of a standard.At first, it includes only 6 rather than 8 transistors.The second, it only link single paratope line to rather than two pairs independently paratope line is right, saved 2 additional access transistors.And, compare with 2 word lines that are used for dual port memory cell, have only the word line of a single energy incoming memory unit 80.Except saving 2 transistors, right being connected also reduced the quantity that enters with the metal connecting line of output storage unit 80 with single bit line only to link single word line.These effects allow to use relatively cheap traditional sram cell to make up array 21.Note to use the array of the one-port memory cell formation that resembles memory cell 80 will be based on the real dual-ported memory of corresponding 8 transistors array size about 25%.

Fig. 3 illustrates the part block scheme and the partial logic figure of arbitration circuit 24 of pie graph 1.Arbitration circuit 24 comprises a single-shot trigger circuit 100 and 101, set-reset flip-floop 102 and 103, and phase inverter 104 and 105, NOR latchs 110, and NAND latchs 120, phase inverter 130 and 131, one-shot circuit 132 and 133, phase inverter 134 and 135 and set-reset flip-floop 136.One-shot circuit 100 has an input end and an output terminal of linking the weld zone 26 that is used for received signal CLOCK (X).One-shot circuit 101 has an input end and an output terminal of linking the weld zone 28 that is used for received signal CLOCK (Y).Trigger 102 has a S input end of linking the output terminal of one-shot circuit 100, a R input end and a Q output terminal.Trigger 103 has a S input end of linking the output terminal of one-shot circuit 101, a R input end and a Q output terminal.Phase inverter 104 has an input end and an output terminal of linking the Q output terminal of trigger 102.Phase inverter 105 has an input end and an output terminal of linking the Q output terminal of trigger 103.

NOR latchs 110 and comprises NOR door 111 and 112.NOR door 111 has a first input end of linking the output terminal of phase inverter 104, one second input end and an output terminal.NOR door 112 has a first input end of linking the output terminal of NOR door 111, links second input end of output terminal of phase inverter 105 and the output terminal of second input end of linking NOR door 111.

NAND latchs 120 and comprises NAND door 121 and 122.NAND door 121 has a first input end of linking the output terminal of NOR door 111, one second input end and an output terminal.NAND door 122 has a first input end of linking the output terminal of NAND door 121, second input end of an output terminal of linking NOR door 112 and the output terminal of second input end of linking NAND door 121.Phase inverter 130 has an input end and an output terminal of linking the output terminal of NAND door 121.Phase inverter 131 has an input end and an output terminal of linking the output terminal of NAND door 122.One-shot circuit 132 has an input end and an output terminal that is used to provide signal CLKX of linking the output terminal of phase inverter 130.One-shot circuit 133 has an input end and an output terminal that is used to provide signal CLKY of linking the output terminal of phase inverter 131.Phase inverter 134 has the input end of an output terminal of linking one-shot circuit 132 and links the output terminal of the R input end of the trigger 102 that is used to provide signal QCLKX.Phase inverter 135 has the input end of an output terminal of linking one-shot circuit 133 and links the output terminal of the R input end of the trigger 103 that is used to provide signal QCLKY.Trigger 136 has the S input end of an output terminal of linking one-shot circuit 132 and R input end and Q output terminal that is used to provide signal XYSEL of an output terminal of linking one-shot circuit 133.

Arbitration circuit 24 comprises two one-shot circuit, is used for providing the short period pulse to eliminate noise saltus step at signal CLOCK (X) and CLOCK (Y).One-shot circuit 100 and 101 pulse width are enough short when with convenient CLOCK (X) and CLOCK (Y) a relative low frequency being arranged, be provided with input invalid before, trigger 102 and 103 reset and import and will not take place.Trigger 102 and 103 Q output terminal are reversed and are provided for NOR and latch 110 input end.

Notice that NOR latchs 110 can become metastable fixed under certain conditions.Under these conditions, the attempt of NOR door 111 and 112 output terminal is maintained fixed an intermediate level.Yet arbitration circuit 24 latchs 120 by NAND and eliminates this metastable state situation.NAND is set latchs 120 thresholding, if become metastable fixed so that NOR latchs 110, NAND latchs 120 will continue operate as normal.NAND latchs 120 output and further oppositely is input to one-shot circuit 132 and 133.One-shot circuit 132 and the 133 slow or unsettled clock signals of conversion also produce the spike pulse with a finite duration response.One-shot circuit 132 and 133 output are by anti-phase signal QCLKX and the QCLKY of providing, and these two signals are fed the R input end that sends back to trigger 102 and 103.This feedback operation has been eliminated at NOR and has been latched any metastable state in 110.

Although the present invention describes with reference to certain embodiments, can do further change and improve those skilled persons of present technique.Therefore should be appreciated that the present invention comprises all these and do not depart from as improvement, variation in the defined scope of the present invention in the attached claim.

Claims

1, an integrated circuit memory (20) is characterized in that:

Many memory cells (21), each of many memory cells (21) is linked single word line and single bit line to last;

Link many memory cells (21), be used for responding the address decoder (22) of a memory cell of many memory cells of address selection (21) of reception;

Link address decoder (22), be used to incoming memory unit (21) array to be provided to first address port (31) of first address of address decoder (22);

Link address decoder (22), be used to incoming memory unit (21) array to be provided to second address port (32) of second address of address decoder (22);

Link memory cell array, be used for responding the data reading port of first or second address from memory cell (21) array sense data;

Link memory cell (21) array, be used to respond first or second address the write data port of writing data into memory unit (21) array; With

Link first and second address ports, be used to receive the arbitration circuit (24) of first clock signal and second clock signal, first and second clock signals are asynchronous mutually, and arbitration circuit (24) determines that during an input of integrated circuit memory (20) in first address and second address which is provided for memory cell (21) array.

2, the storer of claim 1 (20), wherein arbitration circuit (24) guarantee basic request simultaneously basically first or the second clock signal in pre-one the single clock period of determining in order serviced.

3, the storer of claim 1 (20), wherein arbitration circuit (24) determine first or the second clock signal in which first saltus step, then and provide and select signal to be used for selecting the some of first or second address to offer memory cell (21) array.

4, the storer of claim 1 (20), wherein first and second clock signals are provided for address decoder (22), data reading port and write data port, wherein conduct is to the response of the arbitration circuit (24) of the first saltus step of definite first clock signal, use is used to insert first clock signal incoming memory unit (21) array regularly, and, be used to insert second clock signal incoming memory unit (21) array of timing as response to the arbitration circuit (24) of determining the saltus step of second clock signal elder generation.

5, pipeline-type dual-port static incoming memory (20) at random is characterized in that:

Many static random incoming memory unit (21), each in static random incoming memory unit (21) array is linked single word line and single bit line to last;

Be used to receive the arbitration circuit (24) of first clock signal and second clock signal, first and second clock signals are asynchronous mutually, arbitration circuit (24) is used for determining first or which first saltus step of second clock signal, and in response, provides one to select signal;

Link static random incoming memory unit (21) array, be used to respond the address of reception, select the address decoder (22) of a memory cell in static random incoming memory unit (21) array;

Link address decoder (22), be used to respond the selection signal that is in first logic state, for inserting first address port (31) that static random incoming memory unit (21) array is provided to first address of address decoder (22);

Link address decoder (22), be used to respond the selection signal that is in second logic state, for inserting second address port (32) that static random incoming memory unit (21) array is provided to second address of address decoder (22);

Link static random incoming memory unit (21) array, be used to respond first address of reception, therefrom read or write data to first FPDP of static random incoming memory unit (21) array, wherein first FPDP uses first clock signal regularly;

Link static random incoming memory unit (21) array, be used to respond second address of reception, therefrom read or write data to second FPDP of static random incoming memory unit (21) array, wherein second FPDP is used the second clock signal timing.

6, the storer of claim 5 (20), wherein arbitration circuit (24) guarantee basic access request simultaneously basically first or the second clock signal in pre-one the single clock period of determining in order serviced.

7, the storer in any one of claim 3,5 or 6 (20), wherein arbitration circuit (24) is characterised in that:

First trigger (100) has the output terminal that is used to receive the first input end of first clock signal and is used to provide the first latch clock signal;

Second trigger (101) has the output terminal that is used to receive the first input end of second clock signal and is used to provide the second latch clock signal;

First pair of quadrature coupling logic gate (110) has links first (100) and first and second input ends and first and second output terminals of the output terminal of second (101) trigger respectively; With

The 3rd trigger (136) has the first input end of first output terminal of linking first pair of quadrature coupling logic gate (110), links second input end and the output terminal that is used to provide the selection signal of second output terminal of first pair of quadrature coupling logic gate (110).

8, the storer of claim 7 (20), wherein arbitration circuit (24) is further characterized in that second pair of quadrature coupling logic gate (120), second pair of quadrature coupling logic gate (120) has first and second input ends of first and second output terminals of linking first pair of quadrature coupling logic gate (110), links first output terminal and second output terminal of linking second input end of the 3rd trigger (136) of the first input end of the 3rd trigger (136).

9, the storer of claim 8 (20), wherein arbitration circuit (24) is further characterized in that:

First pulse producer (132) has the input end of first output terminal of linking second pair of quadrature coupling logic gate (120), links the output terminal of the first input end of the 3rd trigger (136); With

Second pulse producer (133) has the input end of second output terminal of linking second pair of quadrature coupling logic gate (120), links the output terminal of second input end of the 3rd trigger (136).

10, the storer of claim 9 (20), wherein first trigger (102) has second input end of the output terminal of linking first pulse producer (132), and second trigger (103) has second input end of the output terminal of linking second pulse producer (133).