CN107315703B - Dual priority control type fair arbiter - Google Patents
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Abstract
The invention relates to the field of integrated circuits, in particular to a double-priority control type fair arbitration unit which is designed and further forms a tree-shaped fair arbiter, so that the tolerance of the fair arbiter to process deviation is enhanced, and the robustness of the tree-shaped fair arbiter is improved. The technical scheme adopted by the invention is that the double-priority control type fair arbiter consists of a preselection part, an arbitration part, a response part and a request transmission part, wherein the input of the preselection part is request signals-req 0 and-req 1, delay request signals-r 0 and-r 1 are output, and two priority selection signals ps _ odd and ps _ even are output; the arbitration section inputs r0 and r1, determines the priority of output according to the cases of ps _ odd and ps _ even, and outputs arbitration result signals x0 and x 1. The invention is mainly applied to the integrated circuit design and manufacture occasions.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to a strong robustness priority round robin fairness arbiter.
Background
An arbiter is a type of architecture widely used in Asynchronous Digital Signal Processing (ADSP) circuits, and its main function is to dynamically allocate a single system shared resource to all units requiring the resource. For example, in an asynchronous single bus system, all master modules need to occupy a shared bus for data transmission when generating output; when a plurality of main modules request to occupy the shared bus at the same time, the arbitrator sequences the requests so that asynchronous communication can be carried out according to the sequence, and the problem of system disorder caused by request collision is avoided.
An important characteristic of an arbiter is its fairness in ordering requests. If the ordering of each time is the same, the requests of some units in the system are always responded with priority, and the requests of other units are always responded with the last, so that the same-level system units have different priorities, the bus is blocked by high-priority data, and even low-priority data is directly lost, which is not favorable for maintaining the integrity of signals.
The basic structure of a conventional fair arbiter is shown in FIG. 1, which is composed of (2)n-1) n-layer binary tree structure composed of fair arbitration units, wherein the lowest layer (i.e. the nth layer) has-req 0 to-req (2)n-1) 2 in allnA request signal input and-ack 0 to-ack (2)n-1) 2 in allnAnd outputting the response signal. Each fair arbitration unit can complete arbitration work of two requests of the current layer, generates a request signal of an upper layer, and returns a response signal to an arbitration unit of a lower layer according to the arbitration sequence after receiving a response signal returned by the upper layer. The top layer (i.e. layer 1) unit of the tree-type fair arbiter transmits the generated request signal to the external circuit, and receives the response signal returned by the external circuit to transmit to the lower layer.
The fair arbitration unit mainly depends on the RS flip-flop to realize the fair arbitration function, and the circuit structure of the basic RS flip-flop is shown in FIG. 2 and consists of two NAND gates NAND1 and NAND2, wherein the input of the NAND1 is R and the output Q of the NAND2, and the input of the NAND2 is S and the outputs Q of the NAND 1. The RS trigger needs to meet the constraint condition for normal operation, i.e.
S+R＝1 (1)
It can be seen that when the R and S inputs are both 0, the output of the flip-flop will be 1 and in an unstable state, which will disturb the normal operation of the fair arbiter. To avoid the above situation, the fair arbitration unit is generally divided into four parts, namely a pre-selection part, an arbitration part, a response part and a request transmission part, as shown in fig. 3(a), wherein the specific circuits of the arbitration part are shown in fig. 3(b), (c). The operation sequence of the arbitration unit is shown in fig. 4: after receiving the low and effective request signals-req 0 and-req 1, the preselection part respectively carries out certain time delay and outputs the signals to r0 and r1, and simultaneously judges the overlapping condition between-req 0 and-req 1: if the current overlapping is the odd overlapping since the circuit starts to work, the priority selection signal ps is kept to be 0; if the even-numbered overlap is present, ps generates a pulse with high active level to be input into the arbitration section, the priority of NAND1 is raised, and the output x1 of the arbitration section is pulled down in advance before r0 and r1 reach the arbitration section, thereby avoiding the generation of unstable state.
The structure has the defects that the structure is greatly influenced by the process and mainly comprises the following steps: first, in the case of odd overlapping, the preselected portion will not generate ps valid pulses, and to avoid generating an indeterminate state in this case, the NAND0 of the arbitration portion must always have a strong pull-down capability, but not exceed the pull-down capability of the NAND1 when ps is valid, otherwise ps will not play a role in priority selection when even overlapping; second, the effective interval of the ps pulse must span before and after the falling edges of r0 and r1 arrive, i.e., the ps rising edge must occur before the falling edges of r0 and r1 arrive, and the ps falling edge must occur after the falling edges of r0 and r1 arrive, as shown by the dashed-line box in fig. 4. The above two points have extremely high requirements on the circuit performance, and are easily affected by process deviation, so that the circuit cannot work normally, and the circuit robustness is poor.
Disclosure of Invention
In order to overcome the defects of the prior art and solve the problems that the prior fair arbitration unit circuit has low tolerance to process deviation and poor circuit robustness is caused, the invention aims to design a dual-priority control type fair arbitration unit and further form a tree-shaped fair arbiter, so that the tolerance of the fair arbiter to the process deviation is enhanced, and the robustness of the fair arbiter is improved. The technical scheme adopted by the invention is that the double-priority control type fair arbiter consists of a preselection part, an arbitration part, a response part and a request transmission part, wherein the input of the preselection part is request signals-req 0 and-req 1, delay request signals-r 0 and-r 1 are output, and two priority selection signals ps _ odd and ps _ even are output; the arbitration part inputs r0 and r1, determines the output priority according to the conditions of ps _ odd and ps _ even, and outputs arbitration result signals x0 and x 1; the response part generates response signals-ack 0 AND-ack 1 of the current level according to response signals-ack returned by a superior level AND arbitration results-x 0 AND-x 1, the request transmission part has the function of carrying out AND operation on-req 0 AND-req 1 to form-req to be continuously output to the next level, the arbitration part is a two-way completely symmetrical structure consisting of two AND gates AND0 AND AND1 AND two NOR gates NR0 AND NR1, the AND0 takes an arbitration signal-x 1 output by NR1 AND a delay request signal-r 0 as inputs, the output AND ps _ odd are input to NR0, AND accordingly an arbitration signal-x 0 is generated; the AND1 takes the arbitration signal-x 0 output by NR0 AND the delayed request signal-r 1 as inputs, AND its output AND ps _ even are input to NR1, thus generating arbitration signal-x 1, when the request signals-req 0 AND-req 1 are overlapped for odd times, because ps _ odd is valid AND ps _ even is invalid, NR0 is forced to be pulled low, so that-x 0 has higher priority than-x 1; whereas at even-numbered overlaps, NR1 is forced to be pulled low so that x1 has priority over x0 because ps _ even is active and ps _ odd is inactive, thus achieving fair arbitration for the priority rotation.
In the preselection part, a request signal req0 passes through an inverter to form req0, req0 passes through a delay module DL0 to form d _ req0, and d _ req0 passes through an inverter and a delay module DL1 to output a delay request signal r 0; r0 and d _ req0 are simultaneously input into a nand gate to generate a low-level effective pulse signal c0, the request signal req1 also passes through an inverter to form req1, req1 passes through a delay module DL2 to form d _ req1, and d _ req1 passes through an inverter and a delay module DL3 to output a delay request signal r 1; r1 and d _ req1 are input into a NAND gate at the same time, a low-level effective pulse signal c1 is generated, and the delay time of DL0 DL3 is completely the same and is marked as tdC0 and c1 form collision pulses cp through a NOR gate, i.e., cp generates a width of 2t whenever req0 and req1 are low at the same timedCp is input to clk ends of two D flip-flops FD1 and FD2, a-Q end of FD1 is connected with the D end, and the Q end outputs Q1; the Q terminal of FD2 is connected to the D terminal, and Q2 is output, the Q terminal is not enabled, cp is respectively AND-operated with Q1 and Q2 to form two priority control signals ps _ odd and ps _ even, the ps _ odd valid ps _ even is kept invalid when the request signal is overlapped for the odd times, and the ps _ even valid ps _ odd is kept invalid when the request signal is overlapped for the even times, in addition, since the falling edge of-r 0/r 1 to the falling edge of ps _ odd/ps _ even needs to pass through the delay action of DL1/DL3 and at least three logic gates, the falling edge of-r 0/r 1 can be always at the time of ps _ odd/ps _ eThen t is guaranteed as long as t comes after the ven falling edgedThe delay from d _ req0/d _ req1 to ps _ odd/ps _ even is larger than the delay, so that the effective level of ps _ odd/ps _ even can be ensured to span r 0/r 1 before and after the falling edge arrives.
The response part function is composed of two three-input AND gates, the inputs of the two AND gates are-req 0, -x 0, -ack and-req 1, -x 1 and-ack, respectively, after receiving the response signal-ack returned from the previous stage, the response part determines the response signal-ack 0 or-ack 1 transmitted to the next stage according to the request signals-req 0 and-req 1 of the current stage and the arbitration results-x 0 and-x 1.
The invention has the characteristics and beneficial effects that:
the round-robin-right-fairness arbitration structure based on single-priority control reduces the accuracy of an arbitration part on the pull-down capability requirement of an output circuit by adding one priority control signal, so that the inclusion of the circuit on process deviation is improved, and the robustness of an arbiter is enhanced.
Description of the drawings:
fig. 1 is a tree structure diagram of a fair arbiter.
Fig. 2 is a diagram of a basic RS flip-flop.
Fig. 3 shows a basic structure of a single priority control type fair arbitration unit (a) as a specific circuit of the arbitration partial structure (c) NAND1 in (b).
FIG. 4 is a timing diagram of the operation of the single priority control type fair arbitration unit.
Fig. 5 is a schematic diagram of a double priority control type fairness arbitration unit, in which, (a) a basic configuration, (b) a preselection section circuit configuration, (c) an arbitration section circuit configuration, (d) a response section circuit configuration, and (e) a request transmission section circuit configuration.
FIG. 6 is a timing diagram of the operation of the dual priority control type fair arbitration unit.
Detailed Description
The fair arbitration unit structure adopted by the invention is shown in fig. 5(a), and consists of a preselection part, an arbitration part, a response part and a request transmission part, and the specific circuits of the parts are shown in fig. 5(b) to (e), wherein the input of the preselection part is request signals-req 0 and-req 1, delayed request signals-r 0 and-r 1 are output, and two priority selection signals ps _ odd and ps _ even; the arbitration part inputs r0 and r1, determines the output priority according to the conditions of ps _ odd and ps _ even, and outputs arbitration result signals x0 and x 1; the acknowledge section generates acknowledge signals ack0 and ack1 of the present stage based on acknowledge signals ack returned from the upper stage and arbitration results x0 and x 1. The operation sequence of the circuit is shown in fig. 6. The operating principle of the circuit is described as follows:
the request signal-req 0 passes through an inverter to form req0, req0 passes through a delay module DL0 to form d _ req0, and d _ req0 passes through an inverter and a delay module DL1 to output a delay request signal-r 0; r0 and d _ req0 are input to a NAND gate at the same time, and an active low pulse signal c0 is generated. The request signal-req 1 also passes through an inverter to form req1, req1 passes through a delay module DL2 to form d _ req1, and d _ req1 passes through an inverter and a delay module DL3 to output a delay request signal-r 1; r1 and d _ req1 are input to a NAND gate at the same time, and an active low pulse signal c1 is generated. The delay times of DL 0-DL 3 are all identical and are all marked as td. C0 and c1 form collision pulses cp through a NOR gate, i.e., cp generates a width of 2t whenever req0 and req1 are low at the same timedHigh level pulse. cp is input to clk ends of two D flip-flops FD1 and FD2, a-Q end of FD1 is connected with the D end, and the Q end outputs Q1; the terminal Q of FD2 is connected to the terminal D, and outputs Q2, while the terminal Q is not activated. cp and q1, q2 respectively form two priority control signals ps _ odd and ps _ even. The ps _ odd valid ps _ even remains in an invalid state when the request signal overlaps an odd number of times, and the ps _ even valid ps _ odd remains in an invalid state when the request signal overlaps an even number of times. In addition, since the falling edge of r 0/. about. 1 to ps _ odd/ps _ even needs to pass through DL1/DL3 and the delay action of at least three logic gates, the falling edge of r 0/. about. 1 will definitely come after the falling edge of ps _ odd/ps _ even, so long as t is guaranteeddGreater than the delay d _ req0/d _ req1 to ps _ odd/ps _ even ensures that the effective level of ps _ odd/ps _ even spans r 0/r 1 falling edgeBefore and after the arrival.
The arbitration part is a two-way completely symmetrical structure consisting of two AND gates AND0 AND an AND1 AND two NOR gates NR0 AND NR 1. The AND0 takes as input the arbitration signal x1 output by NR1 AND the delayed request signal r0, the output of which is input to NR0 with ps _ odd, thereby generating the arbitration signal x 0; the AND1 takes as input the arbitration signal x0 output by NR0 AND the delayed request signal r1, the output of which is input to NR1 with ps _ even, thereby generating the arbitration signal x 1. When request signals req0 and req1 overlap odd numbers of times, NR0 is forced to be pulled low so that x0 has higher priority than x1 because ps _ odd is active and ps _ even is inactive; whereas at even-numbered overlaps, since ps _ even is active and ps _ odd is inactive, NR1 is forced to be pulled low, so that x1 has a higher priority than x 0. This achieves fair arbitration of the priority rotation.
The request transmission part has the function of carrying out AND operation on the req0 and the req1 to form req to be continuously output to the next stage.
The answering part function is composed of two three-input and gates. The inputs to the two AND gates are req0, -x 0, -ack and req1, -x 1, -ack, respectively. After receiving the acknowledge signal ack returned from the previous stage, the acknowledge portion determines the acknowledge signal ack0 or ack1 to be transmitted to the next stage according to the request signal req0 and req1 of the current stage and the arbitration result x0 and x 1.
In one example of the present invention, it is considered that such a dual priority control type fairness arbiter is implemented under a 0.11 μm process with a power supply voltage of 1.5V. Due to the need to guarantee tdAnd the delay is larger than the delay to be passed by D _ req0/D _ req1 to ps _ odd/ps _ even, and the delay is the sum of the delay from the clk end to the Q/Q end of a NAND gate, a NOR gate and a D flip-flop at the longest, and the typical value is about 0.7-1.1 ns. On the other hand, considering the arbitration speed, the delay between DL 0-DL 3 should not be too long, so tdMay take about 2 ns.
Claims (2)
1. A double-priority control type fairness arbitrator is characterized by comprising a preselection part, an arbitration part, a response part and a request transmission part, wherein the preselection part is used for performing arbitration on the basis of a priority value of a request transmission partThe input is request signals req0 and req1, the delay request signals r0 and r1 and two priority selection signals ps _ odd and ps _ even are output; the arbitration part inputs r0 and r1, determines the output priority according to the conditions of ps _ odd and ps _ even, and outputs arbitration result signals x0 and x 1; the response part generates response signals-ack 0 AND-ack 1 of the current level according to response signals-ack returned by a superior level AND arbitration results-x 0 AND-x 1, the request transmission part has the function of carrying out AND operation on-req 0 AND-req 1 to form-req to be continuously output to the next level, the arbitration part is a two-way completely symmetrical structure consisting of two AND gates AND0 AND AND1 AND two NOR gates NR0 AND NR1, the AND0 takes an arbitration signal-x 1 output by NR1 AND a delay request signal-r 0 as inputs, the output AND ps _ odd are input to NR0, AND accordingly an arbitration signal-x 0 is generated; the AND1 takes the arbitration signal-x 0 output by NR0 AND the delayed request signal-r 1 as inputs, AND its output AND ps _ even are input to NR1, thus generating arbitration signal-x 1, when the request signals-req 0 AND-req 1 are overlapped for odd times, because ps _ odd is valid AND ps _ even is invalid, NR0 is forced to be pulled low, so that-x 0 has higher priority than-x 1; when overlapping even times, because ps _ even is effective and ps _ odd is ineffective, NR1 is forced to be pulled down, so that x1 has higher priority than x0, and thus fair arbitration of priority rotation is realized; in the preselection part, a request signal req0 passes through an inverter to form req0, req0 passes through a delay module DL0 to form d _ req0, and d _ req0 passes through an inverter and a delay module DL1 to output a delay request signal r 0; r0 and d _ req0 are simultaneously input into a nand gate to generate a low-level effective pulse signal c0, the request signal req1 also passes through an inverter to form req1, req1 passes through a delay module DL2 to form d _ req1, and d _ req1 passes through an inverter and a delay module DL3 to output a delay request signal r 1; r1 and d _ req1 are input into a NAND gate at the same time, a low-level effective pulse signal c1 is generated, and the delay time of DL0 DL3 is completely the same and is marked as tdC0 and c1 form collision pulses cp through a NOR gate, i.e., cp generates a width of 2t whenever req0 and req1 are low at the same timedIs inputted to two D flip-flops FD1 and the clk end of FD2, the-Q end of FD1 is connected with the D end, and the Q end outputs Q1; the Q terminal of FD2 is connected to the D terminal, and Q2 is output, the Q terminal is not enabled, cp is respectively ANDed with Q1 and Q2 to form two priority control signals ps _ odd and ps _ even, the ps _ odd valid ps _ even is kept invalid when the request signal is overlapped for the odd times, and the ps _ even valid ps _ odd is kept invalid when the request signal is overlapped for the even times, in addition, since the falling edge of-r 0/r 1 to the falling edge of ps _ odd/ps _ even needs to pass through the delay action of DL1/DL3 and at least three logic gates, the falling edge of-r 0/r 1 can always arrive after the falling edge of ps _ odd/ps _ even, so long as t is guaranteeddThe delay from d _ req0/d _ req1 to ps _ odd/ps _ even is larger than the delay, so that the effective level of ps _ odd/ps _ even can be ensured to span r 0/r 1 before and after the falling edge arrives.
2. The double-priority control type fair arbiter of claim 1, wherein the response section function is composed of two three-input and gates, the inputs of the two and gates are-req 0, -x 0, -ack and-req 1, -x 1, -ack, respectively, and the response section, upon receiving the response signal-ack returned from the previous stage, decides the response signal-ack 0 or-ack 1 to be transferred to the next stage according to the request signals-req 0 and-req 1 of the current stage and the arbitration results-x 0 and-x 1.
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| CN110083563B (en) * | 2019-04-01 | 2022-10-28 | 吉林大学 | Arbitration circuit for realizing fair arbitration based on cyclic priority |
| CN111211775B (en) * | 2020-01-14 | 2023-05-30 | 西安电子科技大学 | Three-input average arbitration circuit for dynamic vision sensor |
| CN113641605B (en) * | 2021-07-16 | 2024-10-01 | 南京大学 | Polling arbiter applicable to asynchronous circuit and method thereof |
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