CN111211775B - Three-input average arbitration circuit for dynamic vision sensor - Google Patents
Three-input average arbitration circuit for dynamic vision sensor Download PDFInfo
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Abstract
The invention discloses a three-input average arbitration circuit for a dynamic vision sensor, which mainly solves the problem that the prior art cannot realize fair arbitration when three input request signals cannot be realized. The system comprises a preselection unit, a priority selection unit and a communication unit, wherein three request signals R1, R2 and R3 simultaneously pass through the three units, and a request signal to the previous stage is generated in the communication unit; the priority selecting unit generates three priority selecting signals to the preselecting unit after receiving the previous-stage response signals; the preselection unit generates three preselection signals to the communication unit according to the three priority selection signals; the communication unit generates final three arbitration results A1, A2, A3 based on the three pre-selected signals. The invention controls the pull-down capability of the output end of the three-input RS trigger by utilizing the change of the priority control signal, so that the priorities of the three input request signals are evenly ordered in multiple simultaneous requests, and a fair arbitration result is realized. Can be used for dynamic vision sensor.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a three-input average arbitration circuit which can be used for a dynamic vision sensor.
Background
Most of the current dynamic vision sensors adopt an asynchronous processing mode, when a plurality of pixels need to be processed at the same time, an arbiter is needed to determine the priority order of pixel request signals, and the fairness of sequencing is important.
For the number of pixels of 2 N1 ×2 N2 Dynamic vision sensor of each, its used arbiterIs formed by cascading a plurality of two-input average arbitration units, as shown in figure 1, wherein N1 and N2 are integers, N1 is more than or equal to 1, N2 is more than or equal to 1, when the input is 2 N When each, and the arbiter is at 2 N Secondary 2 N When the request signals simultaneously generate requests, the arbiter can realize the rotation priority of each request signal, wherein N is an integer, and N is more than or equal to 1.
For the arbiter formed by cascading a plurality of two-input average arbitration units, the number of the used pixels is 3×2 N ×3×2 N In the dynamic vision sensor of (a), the number of the finally cascaded arbitration units is 3, namely, the number of the request of the last level arbitration unit is 3, and when the 3 request signals continue to request the last level arbitration unit, two-input arbitration units are required to be cascaded, as shown in fig. 2. In this structure, the request signal passing through one two-input arbitration unit is R3, while the two request signals passing through the other two-input arbitration unit are R1 and R2, and in the simultaneous requests of a plurality of times, the number of times that the request signal R3 appears with high priority is twice as large as the number of times that the request signal R1 and the request signal R2 appear with high priority, such priority ordering is unfair, which results in that the request signal with low priority is always in a state of not being responded, and affects the sensing of the low priority pixel on the light intensity change.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a three-input average arbitration circuit for a dynamic vision sensor, which is used for realizing fair three-input arbitration by circularly sequencing the priorities of request signals after 6 times of 3-input simultaneous requests and averaging the priority sequencing of each input request signal when 3 times of 3-input simultaneous requests.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
1. a three-input average arbitration unit circuit for a dynamic vision sensor, comprising a preselection unit 1, a priority selection unit 2 and a communication unit 3, characterized in that:
the preselection unit 1 inputs three request signals R1, R2, R3 and three priority selection signals a, b, c, and outputs three preselection signals Q1, Q2, Q3;
the priority selecting unit 2 inputs three request signals R1, R2, R3 and a previous-stage response signal E, and outputs three priority selecting signals a, b, c;
the communication unit 3 inputs three request signals R1, R2 and R3, three pre-selection signals Q1, Q2 and Q3 and a previous stage response signal E, and outputs a request signal req of the previous stage and three final arbitration results A1, A2 and A3;
three request signals R1, R2, R3 are simultaneously subjected to three units of preselection, priority selection and communication, and a request signal req to the previous stage is firstly generated in the communication unit 3; the priority selecting unit 2 generates three priority selecting signals a, b and c to the preselection unit 1 after receiving the previous-stage response signal E; the preselection unit 1 generates three preselection signals Q1, Q2, Q3 to the communication unit 3 based on the three priority selection signals a, b, c; the communication unit 3 generates the final three arbitration results A1, A2, A3 on the basis of the three pre-selected signals Q1, Q2, Q3.
Further, the preselection unit is composed of a three-input RS trigger, the input ends of the preselection unit are respectively connected with two inverters, the output ends of the preselection unit are respectively connected with three NMOS tubes, namely after the second NMOS tube and the third NMOS tube are connected in parallel, one end of the preselection unit is connected with the first NMOS tube in series, and the other end of the preselection unit is grounded;
the three request signals R1, R2 and R3 respectively generate opposite-phase request signals R1b, R2b and R3b through a first phase inverter, respectively generate in-phase request signals RS1, RS2 and RS3 through a second phase inverter to the three-input RS trigger, and the three priority selection signals a, b and c are respectively connected with the first NMOS tube to control the three-input RS trigger to generate three preselected signals Q1, Q2 and Q3.
Further, the priority selection unit comprises four three-input NOR gates, eight inverters, eight two-input NOR gates, a shift register, three D flip-flops and fifteen transmission gates;
the output ends of the four three-input NOR gates are respectively connected with one inverter and then one input end of the two-input NOR gate to form four parallel inputs, one of which is connected with the shift register, and the other three of which are respectively connected with three D triggers to form four pre-priority signal generating circuits;
the five transmission gates are in a group, the first three transmission gates are connected in parallel and then are connected with one end of a fourth transmission gate, one end of the fifth transmission gate is grounded, and the other end of the fifth transmission gate is connected with the other end of the fourth transmission gate to form three groups of priority selection circuits;
the four two-input NOR gate outputs are respectively and correspondingly connected with four inverters to form a control transmission circuit;
further, the communication unit includes: a three-input AND gate, three-input OR gates, three inverters; wherein three inverters are respectively connected to the second input end of each three-input OR gate;
three request signals R1, R2 and R3 are input to the three-input and gate to generate a request signal req to the previous stage, the three request signals R1, R2 and R3 are respectively connected to the first input of each three-input or gate, the three pre-selected signals Q1, Q2 and Q3 are respectively connected to the second input of each three-input or gate after passing through an inverter, the previous stage response signal E is simultaneously connected to the third input of each three-input or gate, and finally arbitration result signals A1, A2 and A3 are generated.
Compared with the prior art, the invention has the following advantages:
firstly, the invention adopts the three-input average arbitration unit circuit, and uses the change of the priority control signals a, b and c to control whether the NMOS tube at the output end of the three-input RS trigger is conducted or not, so that the pull-down capability of the preselected signals Q1, Q2 and Q3 is different, thereby controlling the priority sequence of the arbitration result, finally enabling the priorities of the three input request signals to be evenly ordered in multiple simultaneous requests, and realizing fair three-input arbitration.
Second, the present invention is applied to a pixel count of 3×2 N ×3×2 N When the dynamic vision sensor is used, the request signal priority of each pixel is evenly ordered in the pixel processing process, so that the fairness processing of the pixels can be realized.
Drawings
FIG. 1 is a schematic diagram of an arbiter constructed by cascading two-input average arbitration units according to the prior art;
FIG. 2 is a schematic diagram showing a conventional two-input average arbitration unit forming a three-input arbitration circuit;
FIG. 3 is a block diagram of a three-input average arbitration circuit according to the present invention;
FIG. 4 is a schematic diagram of a preselected unit configuration in accordance with the present invention;
FIG. 5 is a schematic diagram of a communication unit according to the present invention;
FIG. 6 is a schematic diagram of a priority selection unit according to the present invention;
FIG. 7 is a simulation waveform of a three-input average arbitration unit circuit according to the present invention.
Detailed Description
Referring to fig. 3, the present example includes a preselection unit 1, a priority selection unit 2, and a communication unit 3, in which:
the inputs of 1 of the preselection unit are three request signals R1, R2 and R3 and three priority selection signals a, b and c, and the outputs are three preselect signals Q1, Q2 and Q3 and three inversion request signals R1b, R2b and R3b;
the inputs of the priority selecting unit 2 are request signals R1, R2 and R3, a previous stage response signal E and three reverse phase request signals R1b, R2b and R3b, and the outputs are three priority control signals a, b and c;
the inputs of the communication unit 3 are three request signals R1, R2, R3, three pre-selection signals Q1, Q2, Q3, a previous stage response signal E, and output as a request signal req to the previous stage and finally three arbitration results RA1, RA2, RA3.
When the three request signals R1, R2 and R3 are simultaneously subjected to preselection, priority selection and communication, and become low and effective at the same time, firstly, a request signal req with low effectiveness at the upper stage is output through the communication unit 3, and a response signal E at the upper stage from high to low is returned after the selection at the upper stage; the priority selecting unit 2 generates three priority selecting signals a, b and c under the combined action of the three request signals R1, R2 and R3 and the three reverse phase request signals R1b, R2b and R3b to the preselection unit 1 after receiving the previous-stage response signal E; the three request signals R1, R2, R3, when passing through the preselection unit 1, generate three preselection signals Q1, Q2, Q3 to the communication unit 3 under the control of the three priority selection signals a, b, c; the three pre-select signals Q1, Q2, Q3, the three request signals R1, R2, R3 and the previous level reply signal E cooperate to produce the final three arbitration results A1, A2, A3.
Referring to fig. 4, the preselection unit 1 includes a three-input RS flip-flop, six inverters, and nine NMOS transistors. Every two inverters are in a group, each group is respectively connected with each input end of the three-input RS trigger, every three NMOS are in a group to form three groups of controllers, and the three groups of controllers are correspondingly connected with three output ends of the three-input RS trigger; among three NMOS tubes in each group of controllers, the connection relation is as follows: after the second NMOS tube is connected in parallel with the third NMOS tube, one end of the second NMOS tube is connected in series with one end of the first NMOS tube, the other end of the second NMOS tube is grounded, and the other end of the first NMOS tube is connected with the output end of the three-input RS trigger.
The three request signals R1, R2 and R3 respectively generate opposite-phase request signals R1b, R2b and R3b through a first phase inverter, respectively generate in-phase request signals RS1, RS2 and RS3 through a second phase inverter to the three-input RS trigger, and the three priority selection signals a, b and c are respectively connected with the first NMOS tube to control the three-input RS trigger to generate three preselected signals Q1, Q2 and Q3, wherein the control relation is as follows:
the preselected signal state changes when three request signals R1, R2, R3 are simultaneously active low:
if three priority select signals a=0 and b=c=1, then the first preselected signal Q1 is in an active high state;
if the priority selection signal b=0 and a=c=1, the second preselected signal Q2 is in an active high state;
if the priority selection signal c=0 and a=b=1, the third preselected signal Q3 is in an active high state.
The preselected signal state changes when the first request signal R1 and the second request signal R2 are active low simultaneously, and the third request signal R3 is high:
if a=0 and b=1, then the first preselected signal Q1 is active high;
if a=1 and b=0, then the second preselected signal Q2 is active high;
the preselected signal state changes when the first request signal R1 and the third request signal R3 are active low simultaneously, and the second request signal R2 is high:
if a=0 and c=1, then the first preselected signal Q1 is active high;
if a=1 and c=0, then the third preselected signal Q3 is active high;
the preselected signal state changes when the second request signal R2 and the third request signal R3 are both active low and the first request signal R1 is high:
if b=0 and c=1, then the second preselected signal Q2 is active high;
if b=1 and c=0, the third preselected signal Q3 is active high.
Referring to fig. 5, the priority selecting unit 2 includes four three-input nor gates, eight inverters, eight two-input nor gates, one shift register, three D flip-flops, fifteen transfer gates; the output ends of the four three-input NOR gates are respectively connected with one inverter and then one input end of the two-input NOR gate to form four parallel inputs, one of which is connected with the shift register, and the other three of which are respectively connected with three D triggers to form four pre-priority signal generating circuits; the first three transmission gates are connected in parallel and then connected with one end of a fourth transmission gate, one end of the fifth transmission gate is grounded, and the other end of the fifth transmission gate is connected with the other end of the fourth transmission gate to form three groups of priority selection circuits; the four two-input NOR gate outputs are respectively and correspondingly connected with the four inverters to form a control transmission circuit;
the four paths of pre-priority signal generating circuits have the following signal transmission relation and state change:
when three request signals R1, R2, R3 are simultaneously active low at a time, the three request signals R1, R2, R3 generate an active high first path control signal Xb through a three-input nor gate, and generate an active low first path inversion control signal X through an inverter of the first path, and the inversion control signal X and the previous-stage response signal E output three pre-priority control signals a1, b1, c1 through a shift register with three bits controlled by a nor gate, and the states of the three pre-priority control signals a1, b1, c1 change from 110-011-101 in sequence at a time.
When the first request signal R1 and the second request signal R2 are simultaneously active low and the third request signal R3 is active high each time, the two request signals R1, R2 and the inverted request signal R3b of the third request signal generate an active second control signal Yb through a three-input nor gate, and then generate an active second inverted control signal Y through an inverter of the second channel, the inverted control signal Y and the previous response signal E output two pre-priority control signals a2, b2 through a nor gate control D trigger, and the states of the two pre-priority control signals a2, b2 change from 01 to 10 in sequence each time.
When the second request signal R2 and the third request signal R3 are simultaneously active low and the first request signal R1 is active high each time, the two request signals R2, R3 and the inverted request signal R1b of the first request signal generate an active third-path control signal Zb through a three-input nor gate, and then generate an active third-path inverted control signal Z through an inverter of the third path, the inverted control signal Z and the previous-stage response signal E output pre-priority control signals b3, c2 through a nor gate control D trigger, and the states of the two pre-priority control signals b3, c2 change from 01 to 10 in sequence each time.
When the first request signal R1 and the third request signal R3 are simultaneously active low and the second request signal R2 is active high each time, the two request signals R1, R3 and the inverted request signal R2b of the second request signal generate an active fourth control signal Wb through a three-input nor gate, and then generate an active fourth inverted control signal W through an inverter of the fourth path, the inverted control signal W and the previous response signal E output two pre-priority control signals a3, c3 through a nor gate control D flip-flop, and the states of the two pre-priority control signals a3, c3 change from 10-01 in sequence each time.
The signal transmission relation and state change of the control transmission circuit are as follows:
the three request signals R1, R2 and R3 respectively generate three second control signals R1b, R2b and R3b with the upper-stage response signal E through NOR gates, and the three second control signals respectively generate three opposite-phase second control signals R1, R2 and R3 through an inverter;
when the request signal and the upper-level response signal E are both low and effective, the generated second control signal is high and effective, and the inverted second control signal is low and effective;
when the request signal is high, the generated second control signal is low and the inverted second control signal is high.
The three sets of priority selection circuits have the following signal transmission relation and state change:
the first group of three pre-priority control signals a1, a2 and a3 are respectively controlled by three inverted control signals X, Y, W, a first control signal Xb, a second control signal Yb and a fourth control signal Wb, firstly pass through the transmission gates of the first section of the first group, and then generate a first priority selection signal a through the transmission gates of the second section of the first group under the control of a second control signal r1b and an inverted second control signal r 1;
the three pre-priority control signals b1, b2 and b3 of the second group are respectively controlled by three inverted control signals X, Y, Z, a first control signal Xb, a second control signal Yb and a third control signal Zb, firstly pass through the transmission gates of the first section of the second group, and then generate a second priority selection signal b through the transmission gates of the second section of the second group under the control of the second control signal r2b and the inverted second control signal r 2;
the third group of three pre-priority control signals c1, c2 and c3 are respectively controlled by three inverted control signals X, Z, W, a first control signal Xb, a third control signal Zb and a fourth control signal Wb, firstly pass through the transmission gates of the third group of first sections, and then generate a third priority selection signal c through the transmission gates of the third group of second sections under the control of a second control signal r3b and an inverted second control signal r3;
when the three request signals R1, R2, R3 are all high, the states of the three priority selection signals a, b, c are all low under the control of the three second control signals R1b, R2b, R3b and the three inverted second control signals R1, R2, R3.
Referring to fig. 6, the communication unit 3 includes a three-input and gate, three-input or gates, and three inverters; the three request signals R1, R2 and R3 are input into a three-input AND gate to generate a request signal req of the previous stage, and when any one request signal is valid low, the generated request signal req of the previous stage is low; at the same time, the three request signals R1, R2, R3 are correspondingly connected to the first input ends of the three-input or gates, the three preselected signals Q1, Q2, Q3 are respectively connected to the second input ends of the three-input or gates after passing through an inverter, the low-effective upper-stage response signal E is simultaneously connected to the third input end of each three-input or gate, finally, arbitration result signals A1, A2, A3 are generated, the state of the arbitration result changes according to the change of the three preselected signals Q1, Q2, Q3, but only one arbitration result is low and the other two arbitration results are high at a time. For example, when the pre-select signals q1=1 and q2=q3=0, the corresponding arbitration result is a1=0 being active low, the pixel corresponding to the request signal R1 is selected, a2=a3=1 being high, i.e. the pixels corresponding to the request signals R2 and R3 are not selected.
The effect of the invention is further illustrated by the following simulations:
simulation conditions
The three input request signals R1, R2 and R3 of the three input average arbitration circuit are set to be low and valid for a plurality of times, and the corresponding request signals are reset to be high after the arbitration result is obtained.
Simulation content and results
Under the above conditions, the three-input average arbitration circuit of the present invention is used to simulate the waveforms of the final arbitration result signals A1, A2, A3 generated when the request signals are valid for a plurality of times, and the result is shown in fig. 7, wherein the abscissa in fig. 7 is the time axis, the ordinate is the high-low state of each curve, the upper three curves are respectively three request signals R1, R2, R3, the middle three curves are respectively three priority control signals a, b, c, and the lower three curves are respectively three arbitration result signals A1, A2, A3.
From the arbitration result of fig. 7, the change of the arbitration priority sequence according to the change of the request signal can be obtained, as shown in table 1.
Table 1 arbitration priority order when three inputs of a three-input average arbitration circuit are simultaneously requested multiple times
As can be seen from Table 1, after the number of simultaneous requests exceeds 6, the priority starts to be circularly ordered, wherein the number of times the priorities of the three arbitration results A1, A2, A3 at the respective positions are the same when the first three and the last three simultaneous requests are the same, which is a fair ordering, and only when any two input request signals are low, the priorities of the two signals are rotated every two simultaneous requests, such as when A1 is invalid, the priorities of A2 and A3 are rotated every two simultaneous requests in the order of A2-A3 and A3-A2.
The result can verify that the priority ordering of the three-input average arbitration circuit is average when the three-input average arbitration circuit requests for a plurality of times, thereby realizing fair three-input arbitration.
Claims (4)
1. A three-input average arbitration unit circuit for a dynamic vision sensor, comprising a preselection unit (1), a priority selection unit (2) and a communication unit (3), characterized in that:
the preselection unit (1) inputs three request signals R1, R2 and R3 and three priority selection signals a, b and c, and outputs three preselection signals Q1, Q2 and Q3 and three inversion request signals R1b, R2b and R3b;
the priority selecting unit (2) inputs three request signals R1, R2 and R3, a previous stage response signal E and three opposite-phase request signals R1b, R2b and R3b, and outputs three priority selecting signals a, b and c;
the communication unit (3) inputs three request signals R1, R2 and R3, three pre-selection signals Q1, Q2 and Q3 and a previous-stage response signal E, and outputs a previous-stage request signal req and three final arbitration results A1, A2 and A3;
three request signals R1, R2, R3 are simultaneously subjected to three units of preselection, priority selection and communication, and a request signal req of the previous stage is firstly generated in a communication unit (3); the priority selecting unit (2) generates three priority selecting signals a, b and c to the preselection unit (1) after receiving the previous-stage response signal E; the preselection unit (1) generates three preselection signals Q1, Q2, Q3 to the communication unit (3) based on the three priority selection signals a, b, c; the communication unit (3) generates final three arbitration results A1, A2, A3 according to the three pre-selected signals Q1, Q2, Q3;
the priority selection unit (2) comprises four three-input NOR gates, seven inverters, seven two-input NOR gates, a shift register, three D flip-flops and fifteen transmission gates;
the output ends of the four three-input NOR gates are respectively connected with an inverter and then connected with one input end of a two-input NOR gate to form four parallel inputs, the output end of the two-input NOR gate is connected with a shift register, and the output ends of the three two-input NOR gates are respectively connected with three D triggers to form a three-way pre-priority signal generating circuit; the remaining three two-input NOR gate outputs are respectively and correspondingly connected with the three inverters to form a control transmission circuit;
five transmission gates in the fifteen transmission gates are in a group, the first three transmission gates are connected in parallel and then are connected with one end of a fourth transmission gate, one end of the fifth transmission gate is grounded, and the other end of the fifth transmission gate is connected with the other end of the fourth transmission gate, so that three groups of priority selection circuits are formed;
the three paths of pre-priority signal generating circuits have the following signal transmission relations:
the three request signals R1, R2 and R3 generate a control signal Xb through a three-input NOR gate, and generate an inversion control signal X through an inverter, and the inversion control signal X and the upper-stage response signal E output pre-priority control signals a1, b1 and c1 through a shift register with three bits controlled by the NOR gate;
the two request signals R1 and R2 and the inverted request signal R3b generate a control signal Yb through a three-input NOR gate, and then generate an inverted control signal Y through an inverter, and the inverted control signal Y and the upper-level response signal E output pre-priority control signals a2 and b2 through a NOR gate control D trigger;
the two request signals R2 and R3 and the inverted request signal R1b generate a control signal Zb through a three-input NOR gate, and then generate an inverted control signal Z through an inverter, and the inverted control signal Z and the upper-level response signal E output pre-priority control signals b3 and c2 through a NOR gate control D trigger;
the two request signals R1 and R3 and the inverted request signal R2b generate a control signal Wb through a three-input NOR gate, and then generate an inverted control signal W through an inverter, and the inverted control signal W and the upper-level response signal E output pre-priority control signals a3 and c3 through a NOR gate control D trigger;
the three groups of priority selection circuits have the following signal transmission relations:
the pre-priority control signals a1, a2 and a3 respectively pass through transmission gates under the control of an inverted control signal X, Y, W and control signals Xb, yb and Wb, and then generate a priority selection signal a through a second transmission gate under the control of a second control signal r1b and an inverted second control signal r 1;
the pre-priority control signals b1, b2 and b3 respectively pass through the transmission gates under the control of the inverted control signal X, Y, Z and the control signals Xb, yb and Zb, and then generate the priority selection signal b through the second transmission gate under the control of the second control signal r2b and the inverted second control signal r 2;
the pre-priority control signals c1, c2 and c3 respectively pass through transmission gates under the control of the inverted control signal X, Z, W and the control signals Xb, zb and Wb, and then generate a priority selection signal c through a second transmission gate under the control of the second control signal r3b and the inverted second control signal r3;
the three request signals R1, R2 and R3 respectively generate opposite-phase request signals R1b, R2b and R3b through a first phase inverter, respectively generate in-phase request signals RS1, RS2 and RS3 through a second phase inverter to the three-input RS trigger, and the RS1, RS2 and RS3 are loaded at the input ends of the three-input trigger; the three priority selection signals a, b and c are respectively connected with the grid electrode of the first NMOS tube, and the three input RS trigger is controlled to generate three preselected signals Q1, Q2 and Q3;
three request signals R1, R2 and R3 are input to the three-input and gate to generate a request signal req to the previous stage, the three request signals R1, R2 and R3 are respectively connected to the first input of each three-input or gate, the three pre-selected signals Q1, Q2 and Q3 are respectively connected to the second input of each three-input or gate after passing through an inverter, the previous stage response signal E is simultaneously connected to the third input of each three-input or gate, and finally arbitration result signals A1, A2 and A3 are generated.
2. The circuit according to claim 1, wherein the preselection unit (1) is composed of a three-input RS flip-flop, the three-input RS flip-flop is composed of three nor gates, the input end of each nor gate is connected with two inverters, the output end of each nor gate is connected with a group of controllers, each group of controllers is composed of three NMOS tubes, namely, after the second NMOS tube is connected in parallel with the third NMOS tube, one end of each controller is connected in series with the first NMOS tube, and the other end of each controller is grounded.
3. The circuit of claim 1, wherein the control transmission circuit has a signal transmission relationship as follows:
the three request signals R1, R2 and R3 respectively generate second control signals R1b, R2b and R3b with the previous stage response signals through NOR gates, and respectively generate inverted second control signals R1, R2 and R3 through an inverter.
4. The circuit according to claim 1, characterized in that the communication unit (3) comprises: a three-input AND gate, three-input OR gates, three inverters; wherein three inverters are respectively connected to the second input of each three-input or gate.
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