CN111211775A - Three-input average arbitration circuit for dynamic vision sensor - Google Patents
Three-input average arbitration circuit for dynamic vision sensor Download PDFInfo
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Abstract
The invention discloses a three-input average arbitration circuit for a dynamic vision sensor, which mainly solves the problem that fair arbitration cannot be realized when three input request signals cannot be realized in the prior art. It includes pre-selecting unit, priority selecting unit and communication unit, three request signals R1, R2, R3 pass through these three units at the same time, and the communication unit generates the request signal to the upper level; the priority selection unit generates three priority selection signals to the preselection unit after receiving the response signal of the previous stage; the preselection unit generates three preselection signals to the communication unit according to the three priority selection signals; the communication unit generates the final three arbitration results a1, a2, A3 according to the three preselected signals. The invention controls the pull-down capability of the output end of the three-input RS trigger by using the change of the priority control signal, so that the priorities of the three input request signals are evenly ordered in multiple simultaneous requests, and a fair arbitration result is realized. Can be used for dynamic vision sensors.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a three-input average arbitration circuit which can be used for a dynamic vision sensor.
Background
Most of the current dynamic vision sensors adopt an asynchronous processing mode, when a plurality of pixels need to be processed simultaneously, an arbiter is needed to determine the priority order of pixel request signals, and the fairness of the ordering is crucial.
For the number of pixels is 2N1×2N2The dynamic vision sensor uses an arbiter formed by cascading a plurality of two-input average arbitration units, as shown in FIG. 1, wherein N1 and N2 are integers, N1 is greater than or equal to 1, N2 is greater than or equal to 1, and when the input is 2NWhen and the arbiter is at 2NSub 2NWhen the request signals simultaneously generate requests, the arbiter can realize the rotation priority of each request signal, wherein N is an integer and is more than or equal to 1.
For the above-mentioned arbitrator formed by cascade-connecting several two-input average arbitrating units, the number of pixels used is 3X 2N×3×2NWhen the dynamic vision sensor is used, the number of the final cascaded arbitration units is 3, that is, the number of the requests of the previous-stage arbitration unit is 3, and when the 3 request signals continue to request the previous-stage arbitration unit, two-input arbitration units are required to be cascaded, as shown in fig. 2. In this configuration, the request signal alone passing through one two-input arbitration unit is R3, while the two request signals passing through the other two-input arbitration unit are R1 and R2, and the number of times that the request signal R3 appears high in priority among the simultaneous requests for a plurality of times is twice the number of times that the request signal R1 and the request signal R2 appear high in priority, such priority ordering is unfair, which results in the request signal with low priority being in an unanswered state all the time, and affects the sensing of the light intensity change by the low-priority pixels.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned shortcomings in the prior art, and providing a three-input average arbitration circuit for a dynamic vision sensor, so that after 6 times of 3-input simultaneous requests, the priority of the request signals is circularly ordered, and when 3 times of 3-input simultaneous requests, the priority ordering of each input request signal is averaged, and fair three-input arbitration is realized.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. a three-input average arbitration unit circuit for a dynamic vision sensor, comprising a preselection unit 1, a priority selection unit 2, and a communication unit 3, characterized in that:
the preselection unit 1 inputs three request signals R1, R2 and R3 and three priority selection signals a, b and c and outputs three preselection signals Q1, Q2 and Q3;
the priority selection unit 2, its input is three request signals R1, R2, R3 and upper level answer signal E, the output is three priority selection signals a, b, c;
the communication unit 3 inputs three request signals R1, R2, R3, three preselected signals Q1, Q2, Q3 and a previous-stage answer signal E and outputs three arbitration results A1, A2 and A3 to the previous-stage request signal req and the final arbitration results;
the three request signals R1, R2, R3 pass through the three units of preselection, priority selection and communication at the same time, and first generate a request signal req to the upper stage at the communication unit 3; the priority selection unit 2 generates three priority selection signals a, b and c to the preselection unit 1 after receiving the upper-level response signal E; the preselection unit 1 generates three preselection signals Q1, Q2, Q3 to the communication unit 3 according to the three priority selection signals a, b, c; the communication unit 3 generates the final three arbitration results a1, a2, A3 from the three preselected signals Q1, Q2, Q3.
Furthermore, the preselection unit is composed of a three-input RS trigger, the input end of the preselection unit is respectively connected with two inverters, the output end of the preselection unit is respectively connected with three NMOS tubes, namely, after the second NMOS tube is connected with the third NMOS tube in parallel, one end of the preselection unit is connected with the first NMOS tube in series, and the other end of the preselection unit is grounded;
the three request signals R1, R2 and R3 respectively generate anti-phase request signals R1b, R2b and R3b through a first inverter, and then respectively generate in-phase request signals RS1, RS2 and RS3 through a second inverter to the three-input RS flip-flop, the three priority selection signals a, b and c are respectively connected with the first NMOS tube, and the three-input RS flip-flop is controlled to generate three preselection signals Q1, Q2 and Q3.
Further, the priority selection unit comprises four three-input NOR gates, eight inverters, eight two-input NOR gates, a shift register, three D flip-flops and fifteen transmission gates;
the output ends of the four three-input NOR gates are respectively connected with an inverter and then connected with an input end of a two-input NOR gate to form parallel four-way input, wherein one way is connected with the shift register, and the other three ways are respectively connected with three D triggers to form a four-way pre-priority signal generating circuit;
the five transmission gates are in a group, the first three transmission gates are connected in parallel and then connected with one end of a fourth transmission gate, one end of the fifth transmission gate is grounded, and the other end of the fifth transmission gate is connected with the other end of the fourth transmission gate, so that three groups of priority selection circuits are formed;
the four two-input NOR gate outputs are respectively and correspondingly connected with the four inverters to form a control transmission circuit;
further, the communication unit includes: the three-input AND gate, the three-input OR gate and the three inverters are connected; wherein the three inverters are respectively connected to the second input end of each three-input OR gate;
three request signals R1, R2 and R3 are inputted to a three-input AND gate to generate a request signal req to a previous stage, three request signals R1, R2 and R3 are respectively connected to a first input of each three-input OR gate, three preselected signals Q1, Q2 and Q3 are respectively connected to a second input of each three-input OR gate after passing through an inverter, a previous stage answer signal E is simultaneously connected to a third input of each three-input OR gate, and finally arbitration result signals A1, A2 and A3 are generated.
Compared with the prior art, the invention has the following advantages:
firstly, the invention uses the three-input average arbitration unit circuit to control whether the NMOS tube at the output end of the three-input RS trigger is conducted or not by using the change of the priority control signals a, b and c, so that the pull-down capacities of the preselection signals Q1, Q2 and Q3 are different, thereby controlling the priority sequence of the arbitration result, finally, the priorities of the three input request signals are evenly ordered in a plurality of simultaneous requests, and the fair three-input arbitration is realized.
Second, the present invention is applied to a pixel number of 3 × 2N×3×2NIn the dynamic vision sensor of (1), since the request signal priorities of each pixel are evenly sorted in the process of processing the pixels for a plurality of times, the pixels can be fairly processed.
Drawings
FIG. 1 is a block diagram of an arbiter formed by cascading two-input average arbiter units;
FIG. 2 is a schematic diagram of a conventional two-input average arbitration unit forming a three-input arbitration circuit;
FIG. 3 is a block diagram of a three-input average arbitration circuit according to the present invention;
FIG. 4 is a schematic diagram of a preselected cell configuration in accordance with the present invention;
FIG. 5 is a diagram illustrating a priority selection unit according to the present invention;
FIG. 6 is a schematic diagram of a communication unit according to the present invention;
FIG. 7 is a simulation waveform of the three-input average arbitration unit circuit according to the present invention.
Detailed Description
Referring to fig. 3, the present example includes a preselection unit 1, a priority selection unit 2, and a communication unit 3, in which:
the input of 1 of the preselection unit is three request signals R1, R2, R3 and three priority selection signals a, b, c, and the output is three preselection signals Q1, Q2, Q3 and three inversion request signals R1b, R2b, R3 b;
the priority selection unit 2 has inputs of request signals R1, R2, R3, a previous-stage response signal E and three inverted request signals R1b, R2b, R3b, and outputs of three priority control signals a, b, c;
the communication unit 3 has inputs of three request signals R1, R2, R3, three preselection signals Q1, Q2, Q3, and a previous-stage response signal E, and outputs of a request signal req to a previous stage and final three arbitration results RA1, RA2, RA 3.
The three request signals R1, R2 and R3 pass through three units of preselection, priority selection and communication at the same time, when the signals are simultaneously low and effective, firstly, the signals pass through the communication unit 3 to output a request signal req which is low and effective to the upper level, and after the signals are selected by the upper level, a response signal E which is low and high is returned; the priority selection unit 2 generates three priority selection signals a, b and c to the preselection unit 1 under the combined action of three request signals R1, R2 and R3 and three inverse request signals R1b, R2b and R3b after receiving the response signal E of the previous stage; the three request signals R1, R2, R3, when passing through the preselection unit 1, generate three preselection signals Q1, Q2, Q3 to the communication unit 3 under the control of the three priority selection signals a, b, c; the three preselection signals Q1, Q2, Q3, the three request signals R1, R2, R3 and the previous-stage acknowledge signal E cooperate to produce the final three arbitration results a1, a2, A3.
Referring to fig. 4, the preselection unit 1 includes a three-input RS flip-flop, six inverters, and nine NMOS transistors. Every two inverters are in one group, every one group is respectively connected with every input end of the three-input RS trigger, every three NMOSs are in one group to form a three-group controller, and the three-group controller is correspondingly connected with three output ends of the three-input RS trigger; in three NMOS transistors in each group of controllers, the connection relationship is as follows: after the second NMOS tube and the third NMOS tube are connected in parallel, one end of the second NMOS tube is connected with one end of the first NMOS tube in series, the other end of the second NMOS tube is grounded, and the other end of the first NMOS tube is connected with the output end of the three-input RS trigger.
Three request signals R1, R2 and R3 respectively generate anti-phase request signals R1b, R2b and R3b through a first inverter, and then respectively generate in-phase request signals RS1, RS2 and RS3 through a second inverter to a three-input RS flip-flop, three priority selection signals a, b and c are respectively connected with a first NMOS pipe, and the three-input RS flip-flop is controlled to generate three preselected signals Q1, Q2 and Q3, and the control relationship is as follows:
preselected signal state changes when the three request signals R1, R2, R3 are active low at the same time:
if the three priority selection signals a is 0 and b is 1, the first preselection signal Q1 is in a high active state;
if the priority selection signal b is 0 and a is 1, the second preselection signal Q2 is in a high active state;
if the priority selection signal c is 0 and a is 1, the third preselection signal Q3 is in an active high state.
The preselected signal state changes when the first request signal R1 and the second request signal R2 are both active low and the third request signal R3 is high:
if a is 0 and b is 1, the first preselected signal Q1 is in a high active state;
if a is 1 and b is 0, the second preselected signal Q2 is in a high active state;
the preselected signal state changes when the first request signal R1 and the third request signal R3 are both active low, and the second request signal R2 is high:
if a is 0 and c is 1, the first preselected signal Q1 is in a high active state;
if a is 1 and c is 0, the third preselected signal Q3 is in a high active state;
the preselected signal state changes when the second request signal R2 and the third request signal R3 are both active low and the first request signal R1 is high:
if b is 0 and c is 1, the second preselected signal Q2 is in a high active state;
if b is equal to 1 and c is equal to 0, the third preselected signal Q3 is in an active high state.
Referring to fig. 5, the priority selecting unit 2 includes four three-input nor gates, eight inverters, eight two-input nor gates, one shift register, three D flip-flops, fifteen transmission gates; the output ends of the four three-input NOR gates are respectively connected with an inverter and then connected with an input end of the two-input NOR gate to form parallel four-path input, wherein one path is connected with the shift register, and the other three paths are respectively connected with three D triggers to form a four-path pre-priority signal generating circuit; the five transmission gates are in a group, the first three transmission gates are connected in parallel and then connected with one end of the fourth transmission gate, one end of the fifth transmission gate is grounded, and the other end of the fifth transmission gate is connected with the other end of the fourth transmission gate, so that three groups of priority selection circuits are formed; the outputs of the four two-input NOR gates are respectively and correspondingly connected with the four inverters to form a control transmission circuit;
the four-channel pre-priority signal generation circuit has the following signal transmission relationship and state change:
when the three request signals R1, R2, R3 are active low at the same time, the three request signals R1, R2, R3 generate the first way control signal Xb active high through the three-input nor gate, and then generate the first way inverted control signal X active low through one inverter of the first way, the inverted control signal X and the response signal E of the previous stage output three pre-priority control signals a1, b1, c1 through the shift register of the nor gate controlling three bits, and the states of the three pre-priority control signals a1, b1, c1 change from 110-.
When the first request signal R1 and the second request signal R2 are active low at the same time and the third request signal R3 is active high at a time, the two request signals R1, R2 and the inverted request signal R3b of the third request signal generate the second way control signal Yb which is active high through a three-input nor gate, and generate the second way inverted control signal Y which is active low through an inverter of the second way, the inverted control signal Y and the previous order answer signal E output two pre-priority control signals a2, b2 through a nor gate control D flip-flop, and the states of the two priority control signals a2, b2 change from 01 to 10 in turn each time.
When the second request signal R2 and the third request signal R3 are active low at the same time and the first request signal R1 is active high each time, the two request signals R2, R3 and the inverse request signal R1b of the first request signal generate an active high third control signal Zb through a three-input nor gate, and generate an active low third inverse control signal Z through an inverter of the third path, the inverse control signal Z and the previous response signal E output the pre-priority control signals b3, c2 through a nor gate control D flip-flop, and the states of the two pre-priority control signals b3, c2 change from 01 to 10 in turn each time.
When the first request signal R1 and the third request signal R3 are active low at the same time and the second request signal R2 is active high at the same time, the two request signals R1, R3 and the inverse request signal R2b of the second request signal generate an active high fourth control signal Wb through a three-input nor gate, and then generate an active low fourth inverse control signal W through an inverter of the fourth channel, the inverse control signal W and the previous response signal E output two pre-priority control signals a3, c3 through a nor gate control D flip-flop, and the states of the two pre-priority control signals a3, c3 change from 10-01 at each time in sequence.
The control transmission circuit has the following signal transmission relationship and state change:
the three request signals R1, R2 and R3 respectively generate three second control signals R1b, R2b and R3b with the response signal E of the previous stage through a NOR gate, and the three second control signals respectively generate three inverted second control signals R1, R2 and R3 through an inverter;
when the request signal and the upper-stage response signal E are both low-effective, the generated second control signal is high-effective, and the reverse phase second control signal is low-effective;
when the request signal is high, the generated second control signal is low and the inverted second control signal is high.
The signal transmission relationship and the state change of the three groups of priority selection circuits are as follows:
under the control of three inverted control signals X, Y, W, a first control signal Xb, a second control signal Yb and a fourth control signal Wb, the first group of three pre-priority control signals a1, a2 and a3 first pass through the transmission gates of the first segment of the first group, and then under the control of a second control signal r1b and an inverted second control signal r1, the first group of three pre-priority control signals a1, a2 and a3 generate a first priority selection signal a through the transmission gates of the second segment of the first group;
the second group of three pre-priority control signals b1, b2 and b3 respectively pass through the transmission gates of the first section of the second group under the control of the three reverse phase control signal X, Y, Z, the first path of control signal Xb, the second path of control signal Yb and the third path of control signal Zb, and then pass through the transmission gates of the second section of the second group under the control of the second control signal r2b and the reverse phase second control signal r2 to generate a second priority selection signal b;
the third group of three pre-priority control signals c1, c2 and c3 respectively pass through the transmission gate of the first section of the third group under the control of the three inverted control signal X, Z, W, the first control signal Xb, the third control signal Zb and the fourth control signal Wb, and then pass through the transmission gate of the second section of the third group under the control of the second control signal r3b and the inverted second control signal r3 to generate a third priority selection signal c;
when the three request signals R1, R2, R3 are all high, the states of the three priority selection signals a, b, c are all low under the control of the three second control signals R1b, R2b, R3b and the three inverted second control signals R1, R2, R3.
Referring to fig. 6, the communication unit 3 includes a three-input and gate, three-input or gates, and three inverters; three request signals R1, R2 and R3 are input into a three-input AND gate to generate a request signal req for the previous stage, and when any one request signal is low and effective, the generated request signal req for the previous stage is low; the three request signals R1, R2 and R3 are correspondingly connected to the first input ends of three-input OR gates, three preselection signals Q1, Q2 and Q3 are respectively connected to the second input ends of the three-input OR gates after passing through an inverter, the lower effective upper-level response signal E is simultaneously connected to the third input end of each three-input OR gate, and finally arbitration result signals A1, A2 and A3 are generated, the state of the arbitration result is changed according to the change of the three preselection signals Q1, Q2 and Q3, but only one arbitration result is low effective at each time, and the other two arbitration results are high. For example, when the preselection signal Q1 is 1 and Q2 is Q3 is 0, the arbitration result is that a1 is active low and the pixel corresponding to the request signal R1 is selected, and a2 is active high and A3 is high, that is, the pixels corresponding to the request signals R2 and R3 are not selected.
The effects of the present invention are further illustrated by the following simulations:
simulation conditions
Let the three input request signals R1, R2, R3 of the three-input average arbitration circuit go active low at the same time a plurality of times and reset their corresponding request signals high after the arbitration result is obtained.
Second, simulation content and result
Under the above conditions, the three-input average arbitration circuit of the present invention is used to perform simulation when the request signals are asserted for multiple times, and the final arbitration result signals a1, a2, A3 waveforms are generated, and the result is shown in fig. 7, where the abscissa in fig. 7 is the time axis, the ordinate is the high-low state of each curve, the upper three curves are three request signals R1, R2, R3, the middle three curves are three priority control signals a, b, c, and the lower three curves are three arbitration result signals a1, a2, A3.
The arbitration result in FIG. 7 shows the variation of the arbitration priority sequence with the variation of the request signal, as shown in Table 1.
TABLE 1 arbitration priority sequence for three-input average arbitration circuit when three-input requests are made simultaneously
As can be seen from table 1, after the number of simultaneous requests exceeds 6, the priorities begin to be circularly ordered, wherein the priorities of the three arbitration results a1, a2 and A3 at the first three and the last three simultaneous requests are the same at each position, which is a fair ordering, and only when any two input request signals are low and active, the priorities of the two signals are rotated at every two simultaneous requests, for example, when a1 is inactive, a2 and A3 are rotated at every two simultaneous requests, and the priorities of the two signals are rotated in the two orders of a2-A3 and A3-a 2.
The above results can verify that the priority of the three-input average arbitration circuit of the present invention is even when multiple simultaneous requests are made, and fair three-input arbitration is realized.
Claims (7)
1. A three-input average arbitration unit circuit for a dynamic vision sensor, comprising a pre-selection unit (1), a priority selection unit (2) and a communication unit (3), characterized in that:
the preselection unit (1) inputs three request signals R1, R2, R3 and three priority selection signals a, b and c and outputs three preselection signals Q1, Q2, Q3 and three inversion request signals R1b, R2b and R3 b;
the priority selection unit (2) has three request signals R1, R2, R3, a previous-stage response signal E and three inverted request signals R1b, R2b and R3b as input and has three priority selection signals a, b and c as output;
the communication unit (3) inputs three request signals R1, R2, R3, three preselected signals Q1, Q2, Q3 and a previous-stage answer signal E and outputs three arbitration results A1, A2 and A3 to the previous-stage request signal req and the final three arbitration results;
the three request signals R1, R2, R3 pass through the three units of preselection, priority selection and communication at the same time, and first a request signal req to the upper stage is generated at the communication unit (3); the priority selection unit (2) generates three priority selection signals a, b and c to the preselection unit (1) after receiving the response signal E of the previous stage; the preselection unit (1) generates three preselection signals Q1, Q2, Q3 to the communication unit (3) in dependence on the three priority selection signals a, b, c; the communication unit (3) generates the final three arbitration results a1, a2, A3 from the three preselected signals Q1, Q2, Q3.
2. The method according to claim 1, characterized in that the preselection unit (1) is formed by a three-input RS flip-flop, each input terminal is connected with two inverters, each output terminal is connected with a group controller, each group controller is formed by connecting three NMOS transistors, namely, after the second NMOS transistor is connected with the third NMOS transistor in parallel, one end of the second NMOS transistor is connected with the first NMOS transistor in series, and the other end of the second NMOS transistor is grounded;
the three request signals R1, R2 and R3 respectively generate anti-phase request signals R1b, R2b and R3b through a first inverter, and then respectively generate in-phase request signals RS1, RS2 and RS3 through a second inverter to the three-input RS flip-flop, the three priority selection signals a, b and c are respectively connected with the first NMOS tube, and the three-input RS flip-flop is controlled to generate three preselection signals Q1, Q2 and Q3.
3. The method according to claim 1, wherein the priority selection unit (2) comprises four three-input nor gates, eight inverters, eight two-input nor gates, one shift register, three D flip-flops, fifteen transmission gates;
the output ends of the four three-input NOR gates are respectively connected with an inverter and then connected with an input end of a two-input NOR gate to form parallel four-way input, wherein one way is connected with the shift register, and the other three ways are respectively connected with three D triggers to form a four-way pre-priority signal generating circuit;
the five transmission gates are in a group, the first three transmission gates are connected in parallel and then connected with one end of a fourth transmission gate, one end of the fifth transmission gate is grounded, and the other end of the fifth transmission gate is connected with the other end of the fourth transmission gate, so that three groups of priority selection circuits are formed;
the four two-input NOR gate outputs are respectively and correspondingly connected with the four inverters to form a control transmission circuit.
4. The method of claim 3, wherein the four-way pre-priority signal generation circuit has the following signal transmission relationship:
the three request signals R1, R2 and R3 generate a control signal Xb through a three-input NOR gate, then generate an inverted control signal X through an inverter, and the inverted control signal X and the previous-stage response signal E output pre-priority control signals a1, b1 and c1 through a shift register which controls three bits through the NOR gate;
the two request signals R1 and R2 and the inverted request signal R3b generate a control signal Yb through a three-input NOR gate, and then generate an inverted control signal Y through an inverter, and the inverted control signal Y and the previous-stage response signal E output pre-priority control signals a2 and b2 through a NOR gate control D flip-flop;
the two request signals R2 and R3 and the inverted request signal R1b generate a control signal Zb through a three-input NOR gate, and then generate an inverted control signal Z through an inverter, and the inverted control signal Z and the upper-stage response signal E output pre-priority control signals b3 and c2 through a NOR gate control D flip-flop;
the two request signals R1 and R3 and the inverted request signal R2b generate a control signal Wb through a three-input nor gate, and then generate an inverted control signal W through an inverter, and the inverted control signal W and the previous stage acknowledge signal E output pre-priority control signals a3 and c3 through a nor gate control D flip-flop.
5. The method of claim 3, wherein the three sets of priority selection circuits are signaled as follows:
the pre-priority control signals a1, a2, a3 pass through the transmission gates under the control of the inverted control signal X, Y, W and the control signals Xb, Yb, Wb, respectively, and then pass through the second transmission gate to generate the priority selection signal a under the control of the second control signal r1b and the inverted second control signal r 1;
the pre-priority control signals b1, b2, b3 pass through the transmission gates under the control of the inverted control signal X, Y, Z and the control signals Xb, Yb, Zb, respectively, and then pass through the second transmission gate to generate the priority selection signal b under the control of the second control signal r2b and the inverted second control signal r 2;
the pre-priority control signals c1, c2, c3 pass through transfer gates under the control of the inverted control signal X, Z, W and the control signals Xb, Zb, Wb, respectively, and then pass through a second transfer gate under the control of the second control signal r3b and the inverted second control signal r3 to generate the priority select signal c.
6. The method of claim 3, wherein the control transmission circuit has the following signal transmission relationship:
the three request signals R1, R2 and R3 respectively generate the second control signals R1b, R2b and R3b with the answer signal of the previous stage through a nor gate, and generate the inverted second control signals R1, R2 and R3 through an inverter respectively.
7. The method according to claim 1, characterized in that the communication unit (3) comprises: the three-input AND gate, the three-input OR gate and the three inverters are connected; wherein the three inverters are respectively connected to the second input end of each three-input OR gate;
three request signals R1, R2 and R3 are inputted to a three-input AND gate to generate a request signal req to a previous stage, three request signals R1, R2 and R3 are respectively connected to a first input of each three-input OR gate, three preselected signals Q1, Q2 and Q3 are respectively connected to a second input of each three-input OR gate after passing through an inverter, a previous stage answer signal E is simultaneously connected to a third input of each three-input OR gate, and finally arbitration result signals A1, A2 and A3 are generated.
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| CN115473521A (en) * | 2022-11-02 | 2022-12-13 | 深圳大学 | Ultra-low power consumption strong physics unclonable function circuit structure based on novel arbiter |
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| CN111211775B (en) | 2023-05-30 |
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