CN107220564B - PUF circuit capable of realizing multi-path switching and serial number output circuit - Google Patents
PUF circuit capable of realizing multi-path switching and serial number output circuit Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuits, in particular to a multi-path switchable PUF circuit and a serial number output circuit, which comprise: the delay switching circuit selects the same pulse signal input from different signal input ends, converts the pulse signal into delay signals with different rates, and outputs the delay signals in sequence through different signal output ends, the input end of the decoding circuit is correspondingly connected with a plurality of signal output ends of the delay switching circuit, and according to the sequence of the delay signals output by the signal output ends reaching the decoding circuit, the delay signal which reaches first is processed to generate a two-bit output value, so that the random, unique and reliability index value of the manufactured chip is more ideal, and the risk of the flow sheet is reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a multi-path switchable PUF circuit and a serial number output circuit.
Background
In the field of integrated circuits, wafers and chips produced need to be marked with special unique serial numbers to distinguish the wafers or the chips, in the technical field, the method for distinguishing the serial numbers of the wafers and the chips is to write a special serial number in an EEPROM or an EFLASH of the chips so as to achieve the purpose of distinguishing, but the serial numbers stored in the chips by the method are easy to modify or erase and easy to read, so that the chips are easy to crack by a cracking technology.
In response to this situation, PUF technology has come to be used, which uses the unique physical properties of silicon wafers and the variability of IC manufacturing processes to identify individual chips and thereby determine the authenticity of the chips. In the existing PUF technology, a PUF introduces a natural random source, an algorithm which can hardly be predicted and copied is generated, the system security is increased, and a serial number stored in a chip can not be modified, erased and read randomly. However, many chips manufactured by PUF technology have poor reliability and are prone to tape-out failure. If the arbiter PUF generates a multi-bit output value by combining a single PUF circuit in parallel, but each delay path cannot or is less communicated, if a large error occurs in one delay path, which is different from other delay paths, the output of the chip may be a fixed value which does not change according to the input, so that the Reliability (Reliability) and Uniqueness (Uniqueness) indexes of the chip are not ideal, and the commercial possibility is low and the risk is high.
Therefore, it is important to design a PUF circuit with high randomness, high reliability, and high uniqueness.
Disclosure of Invention
The invention aims to provide a multi-path switchable PUF circuit and a serial number output circuit, which can disperse large errors generated during tape-out by mixing a plurality of delay paths, thereby improving the reliability and the randomness of a chip.
In order to solve the technical problems, the invention adopts the following technical scheme:
a switchable PUF circuit, comprising:
the time delay switching circuit is provided with a key input end, a plurality of signal input ends and a plurality of signal output ends, wherein the key input end correspondingly inputs a two-bit key, the signal input ends are connected with the same external pulse signal, the time delay switching circuit selects the same pulse signal input from different signal input ends, converts the pulse signal into time delay signals with different rates and sequentially outputs the time delay signals through different signal output ends;
and the input end of the decoding circuit is correspondingly connected with the plurality of signal output ends of the delay switching circuit, and the delay signal which arrives firstly is processed to generate a two-bit output value according to the sequence of the delay signals output by the signal output ends and arriving at the decoding circuit.
In some embodiments of the invention, the signal input terminal and the signal output terminal of n of the delay switching circuits are connected in series in sequence, so that n of the series connected delay switching circuits support the input of 2 n-bit keys.
In some embodiments of the present invention, the key is input to the key input terminal of the corresponding delay switching circuit from left to right in the connection order of the delay switching circuits, and one unit is input to every two bits from the least significant bit to the most significant bit of the key.
In some embodiments of the present invention, the delay switching circuit includes a plurality of data selectors, data input terminals of the data selectors are respectively connected in parallel to form a signal input terminal of the delay switching circuit, output terminals of the data selectors respectively form a signal output terminal of the delay switching circuit, address input terminals of the data selectors are respectively connected in parallel to form a key input terminal of the delay switching circuit, and the data selectors correspondingly select the delay signals according to keys input by the address input terminals and send the delay signals to the output terminals of the data selectors.
In some embodiments of the invention, the delay switching circuit comprises a first data selector, a second data selector, a third data selector and a fourth data selector which are all 4-to-1 data selectors,
the first data input end of the first data selector is connected with the second data input end of the second data selector, the third data input end of the third data selector and the fourth data input end of the fourth data selector in parallel to form a first signal input end of the delay switching circuit;
the second data input end of the first data selector is connected in parallel with the first data input end of the second data selector, the fourth data input end of the third data selector and the third data input end of the fourth data selector to form a second signal input end of the delay switching circuit;
the third data input end of the first data selector is connected in parallel with the fourth data input end of the second data selector, the first data input end of the third data selector and the second data input end of the fourth data selector to form a third signal input end of the delay switching circuit;
the fourth data input end of the first data selector is connected in parallel with the third data input end of the second data selector, the second data input end of the third data selector and the first data input end of the fourth data selector to form a fourth signal input end of the delay switching circuit;
the output ends of the first data selector, the second data selector, the third data selector and the fourth data selector respectively form a first signal output end, a second signal output end, a third signal output end and a fourth signal output end of the time delay switching circuit,
the first address input ends of the first data selector, the second data selector, the third data selector and the fourth data selector are connected in parallel to form a first key input end of the delay switching circuit;
and second address input ends of the first data selector, the second data selector, the third data selector and the fourth data selector are connected in parallel to form a second key input end of the time delay switching circuit.
In some embodiments of the present invention, the decoding circuit includes an arbiter and a combinational logic circuit, an input end of the arbiter is connected to a signal output end of the delay switching circuit, every two delay signals output by the delay switching circuit are randomly combined and input to the arbiter in parallel, the arbiter arbitrates according to the order of input of the delay signals, the delay signals input to the arbiter first are output, an output end of the arbiter is connected to an input end of the combinational logic circuit, and the combinational logic circuit performs combinational logic processing on the delay signals output by the arbiter and outputs a two-bit output value.
In some embodiments of the invention, the decoding circuit comprises 6 identical arbiters, wherein,
the input signal end of the first arbiter is respectively connected with the first signal output end and the second signal output end of the delay switching circuit,
the input signal end of the second arbiter is respectively connected with the first signal output end and the third signal output end of the delay switching circuit,
the input signal end of the third arbiter is respectively connected with the first signal output end and the fourth signal output end of the delay switching circuit,
the input signal end of the fourth arbiter is respectively connected with the second signal output end and the third signal output end of the delay switching circuit,
the input signal end of the fifth arbiter is respectively connected with the second signal output end and the fourth signal output end of the delay switching circuit,
the input signal end of the sixth arbiter is respectively connected with the third signal output end and the fourth signal output end of the delay switching circuit,
the output signal ends of the first arbiter, the second arbiter, the third arbiter, the fourth arbiter, the fifth arbiter and the sixth arbiter are connected with the input end of the combinational logic circuit.
In some embodiments of the present invention, the combinational logic circuit comprises 8 and gates, 2 exclusive or gates,
the input end of the first AND gate is respectively connected with the output ends of the first arbiter, the second arbiter and the third arbiter,
the input end of the second AND gate is respectively connected with the output ends of the first arbiter, the fourth arbiter and the fifth arbiter,
the input end of the third AND gate is respectively connected with the output ends of the second arbiter, the fourth arbiter and the sixth arbiter,
the input end of the fourth AND gate is respectively connected with the output ends of the third arbiter, the fifth arbiter and the sixth arbiter,
the input end of the fifth AND gate is respectively connected with the output ends of the first AND gate and the third AND gate, the input end of the sixth AND gate is respectively connected with the output ends of the first AND gate and the second AND gate,
the input end of the first exclusive-OR gate is respectively connected with the output ends of the second and-gate and the fourth and-gate, the input end of the second exclusive-OR gate is respectively connected with the output ends of the third and-gate and the fourth and-gate,
the input end of the seventh AND gate is respectively connected with the output end of the fifth AND gate and the output end of the first exclusive-OR gate, the input end of the eighth AND gate is respectively connected with the output end of the sixth AND gate and the output end of the second exclusive-OR gate, and the output ends of the seventh AND gate and the eighth AND gate respectively output two-bit output values.
The invention also provides a serial number output circuit which comprises the PUF circuit, wherein a plurality of groups of PUF circuits are sequentially connected in parallel to form the serial number output circuit of which the serial number is determined by the PUF circuits.
In some embodiments of the present invention, the serial number output circuit includes m groups of PUF circuits connected in parallel, each PUF circuit outputs two bit output values, so that the m groups of output two bit output values are sequentially arranged to form a 2 m-bit serial number.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
1. the PUF circuit provided by the invention is mixed into a multi-path delay path through the delay switching circuit and the decoding circuit, so that a larger error which may occur when a single-path delay path is directly connected in parallel is avoided, the index values of the randomness, the uniqueness and the reliability of a chip manufactured by the PUF circuit are more ideal, and the risk of chip flow is reduced;
the PUF circuit utilizes the process error in the production of the integrated circuit, and the pulse signals are randomly selected and combined through the delay switching circuit and the decoding circuit, so that output values have unpredictable natural randomness, even if chips produced through the same circuit and process are unique and can not be copied;
3. the PUF circuit provided by the invention can be used for a serial number output circuit, and because the output value generated by the PUF circuit is random, the correspondingly generated serial number is also random and cannot be predicted and calculated, once the chip is produced, the serial number cannot be changed, and is not easy to modify and erase;
4. the serial number output circuit provided by the invention has the functions of hiding and protecting the serial number, the correct serial number can be obtained only by inputting the correct key, and the serial number generation process of the chip cannot be copied even if the circuit is completely disclosed.
Drawings
Fig. 1 is a schematic connection diagram of a multi-switchable PUF circuit in embodiment 1 of the present invention;
fig. 2 is a schematic connection diagram of the delay switching circuit in embodiment 1 of the present invention;
FIG. 3 is a schematic diagram showing the connection of a decoding circuit in embodiment 1 of the present invention;
fig. 4 is a schematic connection diagram of a multi-switchable PUF circuit in embodiment 2 of the present invention;
fig. 5 is a schematic connection diagram of the delay switching circuit in embodiment 2 of the present invention;
FIG. 6 is a schematic diagram showing the connection of a decoding circuit in embodiment 2 of the present invention;
FIG. 7 is a schematic diagram of the internal structure of an arbiter in embodiment 2 of the present invention;
fig. 8 is a schematic connection diagram of a multi-switchable PUF circuit in embodiment 3 of the present invention;
fig. 9 is a schematic connection diagram of a serial number generation circuit in embodiment 3 of the present invention.
Detailed Description
The technical solution proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention.
The invention utilizes the random sources of process errors during the production of integrated circuits, such as doping concentration, slight difference of the length and width of a transistor and the like, carries out random selection and combination on pulse signals through a delay switching circuit and a decoding circuit, and mixes a plurality of delay paths so as to solve the problem of larger error of the traditional PUF circuit. The principles of the present invention will now be described with reference to the drawings and specific embodiments.
Example 1
This embodiment describes in detail a structure and a principle of a multi-way switchable PUF circuit provided by the present invention, referring to fig. 1, which is a connection schematic diagram of the PUF circuit, where input terminals and output terminals in the diagram are only used for illustrating a connection relationship between a delay switching circuit and a decoding circuit, specific numbers of the input terminals and the output terminals are not subject to the drawing, and the PUF circuit mainly includes:
the time delay switching circuit is provided with a key input end, a plurality of signal input ends and a plurality of signal output ends, wherein two-bit keys are correspondingly input into the key input end, the signal input ends are connected with the same external pulse signals, the time delay switching circuit selects the same pulse signals input from the different signal input ends, converts the pulse signals into time delay signals with different rates, and sequentially outputs the time delay signals through the different signal output ends. In order to realize randomness, the number of signal input ends needs to be 2 or more, and the number is particularly based on the number actually needed.
And the input end of the decoding circuit is correspondingly connected with the plurality of signal output ends of the delay switching circuit, and the delay signal which arrives firstly is processed to generate a two-bit output value according to the sequence of the delay signals output by the signal output ends and arriving at the decoding circuit.
The delay switching circuit specifically includes a plurality of data selectors, referring to fig. 2, which illustrates four data selectors as an example, it should be noted that the input terminals and the output terminals in the figure are only used for illustrating the connection relationship between the data selectors, and the specific numbers of the input terminals and the output terminals and the specific connections of the input terminals are not subject to the drawing. The data input ends of the data selectors are respectively connected in parallel to form a signal input end of the delay switching circuit, the output ends of the data selectors respectively form a signal output end of the delay switching circuit, the address input ends of the data selectors are respectively connected in parallel to form a key input end of the delay switching circuit, and the data selectors correspondingly select delay signals according to keys input by the address input ends and send the delay signals to the output ends of the data selectors. The data selector may select the data selector of types such as 2 to 1, 4 to 1, 8 to 1, 16 to 1, and the like according to actual requirements, which is not limited herein.
The decoding circuit mainly includes an arbiter and a combinational logic circuit, referring to fig. 3, the input and output terminals in the figure are only used for illustrating the connection relationship between the arbiter and the combinational logic circuit, and the specific number of the input and output terminals is not subject to the figure. The input end of the arbiter is respectively connected with the signal output end of the delay switching circuit, every two delay signals output by the delay switching circuit are randomly combined and input into the arbiter (the delay signals of the combined parallel input arbiter need to be ensured not to be combined), the arbiter arbitrates according to the sequence of the input of the delay signals, the delay signals input into the arbiter firstly are output, the output end of the arbiter is connected with the input end of the combined logic circuit, and the combined logic circuit performs combined logic processing on the delay signals output by the arbiter and outputs a two-bit output value. The specific circuit connection structure of the combinational logic circuit is not limited, and the delay signal output by the random combination arbiter can be realized.
The same pulse signal is added to the signal input end of the delay switching circuit, and the key is correspondingly input to the key input end of the delay switching circuit, the key is input from the lowest bit to the highest bit in the input process, the pulse signal input to the delay switching circuit can be propagated through a certain path respectively due to the physical characteristics and variability of the integrated circuit, then the speed changes, so that delay signals with different speeds are formed, the delay signals with different speeds are selected according to the speed of reaching the output end of the delay switching circuit, the delay signals are correspondingly selected according to the key of the key input end and are sequentially output from the signal output ends of the delay switching circuit respectively, the delay signals which arrive firstly and quickly are judged by an arbiter in a decoding circuit behind the delay switching circuit, and then the signals which arrive firstly are subjected to random logic processing through a combinational logic circuit in the decoding circuit, and finally, random two-bit output values R0 and R1 are obtained. Because the invention adopts the mode of mixing the multi-path delay paths, the larger error which may occur when the single-path delay paths are directly connected in parallel is avoided, the index values of the randomness, the uniqueness and the reliability of the manufactured chip are more ideal, and the risk of the flow sheet is reduced.
Example 2
This embodiment describes in detail a PUF circuit that realizes 4 delay paths using four data selectors based on the contents described in embodiment 1, and the PUF circuit in this embodiment can switch between each other according to the input, and disperse a large error generated during stream slicing inside the circuit, thereby improving randomness, reliability, and uniqueness.
The connection relationship between the delay switching circuit and the decoding circuit is described in detail in embodiment 1, and based on embodiment 1, the delay switching circuit in this embodiment is formed by selecting four 4-to-1 data selectors, see fig. 4, and the principles of the data selectors of types such as 2-to-1, 8-to-1, 16-to-1, and the like are similar, and are not described herein again. For convenience of description, four data selectors are respectively named as a first data selector, a second data selector, a third data selector and a fourth data selector from top to bottom, and data input terminals of the data selectors are respectively named as a first data input terminal to a fourth data input terminal according to the sequence of pin 0, pin 1, pin 2 and pin 3 of the data selectors in the figure, see fig. 5, wherein,
the first data input end of the first data selector is connected with the second data input end of the second data selector, the third data input end of the third data selector and the fourth data input end of the fourth data selector in parallel to form a first signal input end i0 of the delay switching circuit;
the second data input end of the first data selector is connected with the first data input end of the second data selector, the fourth data input end of the third data selector and the third data input end of the fourth data selector in parallel to form a second signal input end i1 of the delay switching circuit;
the third data input end of the first data selector is connected with the fourth data input end of the second data selector, the first data input end of the third data selector and the second data input end of the fourth data selector in parallel to form a third signal input end i2 of the delay switching circuit;
the fourth data input end of the first data selector is connected with the third data input end of the second data selector, the second data input end of the third data selector and the first data input end of the fourth data selector in parallel to form a fourth signal input end i3 of the delay switching circuit;
because of the need to generate randomness, four signal input terminals must be provided with four signal output terminals, and the output terminals of the first data selector, the second data selector, the third data selector and the fourth data selector respectively form the first signal output terminal O0, the second signal output terminal O1, the third signal output terminal O2 and the fourth signal output terminal O3 of the delay switching circuit,
for the key input end of the delay switching circuit, the first address input ends of the first data selector, the second data selector, the third data selector and the fourth data selector are connected in parallel to form a first key input end s0 of the delay switching circuit; the key input end of the delay switching circuit, and the second address input ends of the first data selector, the second data selector, the third data selector and the fourth data selector are connected in parallel to form a second key input end s1 of the delay switching circuit;
therefore, the delay switching circuit in the embodiment correspondingly has four signal input terminals i0/i1/i2/i3, four signal output terminals O0/O1/O2/O3 and two key input terminals s0/s 1.
The four signal output ends of the delay switching circuit are correspondingly connected, in order to perform pairwise non-repeated combined parallel input on the delays of the four signal output ends, the input end of the decoding circuit should be composed of 6 identical arbiters, the circuit connection schematic diagram of the decoding circuit is shown in fig. 6, a 2-input arbiter is selected as the arbiter, and the design standard of the arbiter should meet the minimum precision for identifying the speed of 4 paths of delay signals, wherein the 2-output arbiter is shown in fig. 7, and the principle of the 2-output arbiter is not repeated herein. The arbitrators in fig. 6 are named as a first arbitrator, a second arbitrator, a third arbitrator, a fourth arbitrator, a fifth arbitrator and a sixth arbitrator sequentially from top to bottom, wherein O0-O3 at the input end of the arbitrators represents the delay signals output by the delay switching circuit, the input signal end of the first arbitrator is respectively connected with the first signal output end and the second signal output end of the delay switching circuit, the input signal end of the second arbitrator is respectively connected with the first signal output end and the third signal output end of the delay switching circuit, the input signal end of the third arbitrator is respectively connected with the first signal output end and the fourth signal output end of the delay switching circuit, the input signal end of the fourth arbitrator is respectively connected with the second signal output end and the third signal output end of the delay switching circuit, the input signal end of the fifth arbitrator is respectively connected with the second signal output end and the fourth signal output end of the delay switching circuit, the input signal end of the sixth arbiter is respectively connected with the third signal output end and the fourth signal output end of the delay switching circuit, and the output signal ends of the first arbiter, the second arbiter, the third arbiter, the fourth arbiter, the fifth arbiter and the sixth arbiter are connected with the input end of the combinational logic circuit.
In order to make the data more random, the combinational logic circuit of the present invention can be specifically designed based on the above, see the right half of fig. 6, which is a specific connection schematic diagram of the combinational logic circuit in the present embodiment, as shown in fig. 6, the combinational logic circuit includes 8 and gates (labeled as 1-8 in the figure), 2 xor gates (labeled as 1 ' -2 in the figure), and the 8 and gates are respectively named as a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, a sixth and gate, a seventh and gate, and an eighth and gate according to the numerical labels in the figure, while for the two xor gates, the one labeled as 1 ' is a first xor gate, the other labeled as 2 ' is a second xor gate, the input terminal of the first and gate is respectively connected with the output terminals of the first arbiter, the second arbiter, the input terminal of the second and gate is respectively connected with the first arbiter, the second arbiter, the input terminal of the second and gate is respectively, The output ends of the fourth arbiter and the fifth arbiter, the input end of the third AND gate are respectively connected with the second arbiter and the fourth arbiter, the input end of the sixth and gate is respectively connected with the output ends of the third, fifth and sixth arbiters, the input end of the fifth and gate is respectively connected with the output ends of the first and gate and the third and gate, the input end of the sixth and gate is respectively connected with the output ends of the first and gate and the second and gate, the input end of the first exclusive or gate is respectively connected with the output ends of the second and gate and the fourth and gate, the input end of the second exclusive or gate is respectively connected with the output ends of the third and gate and the fourth and gate, the input end of the seventh and gate is respectively connected with the output end of the fifth and gate and the output end of the first exclusive or gate, the input end of the eighth and gate is respectively connected with the output end of the sixth and gate and the output end of the second exclusive or gate, and output values of the seventh and gate and the eighth and gate are respectively output two.
Thus, the same pulse signal is applied to the first signal input terminal, the second signal input terminal, the third signal input terminal and the fourth signal input terminal of the delay switching circuit, after the delay signals i0-i3 are input in parallel to the data selector through the first data selector, the second data selector, the third data selector and the fourth data selector in fig. 5, the first data selector, the second data selector, the third data selector and the fourth data selector output respective output signals in parallel, O0-O3 is formed, these signals are output in two-by-two combination to respective input terminals of the first arbiter, the second arbiter, the third arbiter, the fourth arbiter, the fifth arbiter and the sixth arbiter of fig. 6, the first arbiter receives O0 and O1 signals, the second arbiter receives O0 and O2 signals, the third arbiter receives O0 and O3 signals, the fourth arbiter receives signals of O1 and O2, the fifth arbiter receives signals of O1 and O3, the sixth arbiter receives signals of O2 and O3, each arbiter takes the data coming first in arbitration as an output signal, after the 6-path arbiters output in parallel, the output signals are input into the first AND gate, the second AND gate, the third AND gate and the fourth AND gate in parallel in three paths, the first AND gate, the second AND gate, the third AND gate and the fourth AND gate output the output signals to the fifth AND gate, the sixth AND gate, the first XOR gate and the second XOR gate, logic non-overlapping is achieved, finally the output signals are input into the seventh AND gate and the eighth AND gate, and two random output values R0 and R1 are finally generated.
Example 3
In order to further increase the randomness of the PUF circuit in the present invention, based on embodiments 1 and 2, the signal input terminals and the signal output terminals of n delay switching circuits may be sequentially connected in series, as shown in fig. 8, each delay switching circuit corresponds to 2-bit input of the secret key, and then the n series-connected delay switching circuits support input of the 2 n-bit secret key, it should be noted that the input secret key needs to be input to the key input terminal of the corresponding delay switching circuit from left to right according to the connection sequence of the delay switching circuits, and one unit is input to each two bits from the lowest bit to the highest bit of the secret key.
The specific structures of the delay switching circuit and the decoding circuit in this embodiment have been specifically stated in embodiment 1 and embodiment 2, and are not described herein again. In embodiment 3, compared with embodiments 1 and 2, the number of delay switching circuits is increased, and signal input terminals and signal output terminals of a plurality of delay switching circuits are sequentially connected in series, so that on one hand, the propagation length of a delay path is increased for a pulse signal input from a signal input terminal, and on the other hand, a PUF circuit can support input of a 2 n-bit key. When the same pulse signal is applied to the signal input terminal of the first delay switching circuit (four delay paths are taken as an example in the figure), the key is simultaneously input to the corresponding delay switching circuit input terminal, namely the key input terminals B1, B2 … Bn (n is the bit number of the key), B1, B2 … Bn are input from left to right according to the connection sequence of the delay switching circuits, the key is input to the corresponding delay switching circuit from the lowest bit to the highest bit by one unit of every two bits, the four pulse signals are respectively transmitted from the signal input terminal of the first delay switching circuit to the signal output terminal of the last delay switching circuit after being transmitted through a certain path, the input of the data selector is controlled by B1, B2 … Bn, the data selector outputs corresponding logic level (0 or 1) according to the signals of B1, B2 … Bn, the decoding circuit selects the sequence of the delay signals output by the data selector, and performing random mixed logic calculation on the path of signal reaching the fastest speed, and outputting a final two-bit output value.
Example 4
This embodiment specifically details a serial number output circuit additionally provided in the present invention, and this serial number output circuit is implemented based on the PUF circuit described above, and specifically, the serial number output circuit includes the PUF circuit described in embodiments 1 to 3 described above, and naturally, includes a modified embodiment based on embodiments 1 to 3.
Because a set of PUF circuit can produce 2 bit outputs, more sets of PUF circuits can be added as required to be used in parallel, specifically, the multiple sets of PUF circuits are connected in parallel in sequence, so that a serial number output circuit with the serial number determined by the PUF circuits is formed, m sets of PUF circuits can be connected in parallel according to the length of the serial number, as shown in fig. 9, each PUF circuit outputs two bit output values respectively, and the m sets of output two bit output values can be arranged in sequence to form the 2 m-bit serial number.
If a 16-bit serial number output needs to be generated and 8-bit secret key reading is carried out, 8 groups of PUF circuits are used in total, the design of each PUF circuit is kept to be completely the same, the fine error of each PUF circuit only comes from an unpredictable natural random source during production, output values are made to have unpredictable natural randomness, namely chips produced through the same circuit and the same process are unique and cannot be copied, so that the serial number generation process of the chips cannot be copied even if the circuits of the chips are completely disclosed, the chips cannot be erased and modified like a method of writing serial numbers in flash, and the circuits further have a serial number protection function, and correct serial numbers can be obtained only when correct secret keys are input.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A switchable PUF circuit, comprising:
the time delay switching circuit is provided with a key input end, a plurality of signal input ends and a plurality of signal output ends, wherein the key input end correspondingly inputs a two-bit key, the signal input ends are connected with the same external pulse signal, the time delay switching circuit selects the same pulse signal input from different signal input ends, converts the pulse signal into time delay signals with different rates and sequentially outputs the time delay signals through different signal output ends;
the input end of the decoding circuit is correspondingly connected with the plurality of signal output ends of the delay switching circuit, and according to the sequence of the delay signals output by the signal output ends reaching the decoding circuit, the delay signals which arrive at the first time are processed to generate two-bit output values;
the decoding circuit comprises an arbiter and a combinational logic circuit, wherein the input end of the arbiter is respectively connected with the signal output end of the delay switching circuit, delay signals output by the delay switching circuit are randomly combined in pairs and input into the arbiter in parallel, the arbiter arbitrates according to the sequence of input of the delay signals and outputs the delay signals input into the arbiter first, the output end of the arbiter is connected with the input end of the combinational logic circuit, and the combinational logic circuit performs combinational logic processing on the delay signals output by the arbiter and outputs two-bit output values.
2. A switchable PUF circuit according to claim 1, wherein the signal inputs and signal outputs of n of the delay switching circuits are connected in series in sequence, such that the n series connected delay switching circuits support the input of a 2 n-bit key.
3. The switchable PUF circuit of claim 2, wherein the secret key is input to the key input terminal of the corresponding delay switching circuit from left to right in the connection order of the delay switching circuits, and one unit for every two bits from the least significant bit to the most significant bit of the secret key.
4. A switchable PUF circuit according to claim 1 or 2, wherein the delay switching circuit comprises a plurality of data selectors, the data inputs of the data selectors are connected in parallel to form the signal inputs of the delay switching circuit, the outputs of the data selectors form the signal outputs of the delay switching circuit, the address inputs of the data selectors are connected in parallel to form the key inputs of the delay switching circuit, and the data selectors select the delay signals according to the keys input at the address inputs and send the delay signals to the outputs of the data selectors.
5. A switchable PUF circuit according to claim 4, wherein the delay switching circuit comprises a first data selector, a second data selector, a third data selector and a fourth data selector, all being 4-to-1 data selectors,
the first data input end of the first data selector is connected with the second data input end of the second data selector, the third data input end of the third data selector and the fourth data input end of the fourth data selector in parallel to form a first signal input end of the delay switching circuit;
the second data input end of the first data selector is connected in parallel with the first data input end of the second data selector, the fourth data input end of the third data selector and the third data input end of the fourth data selector to form a second signal input end of the delay switching circuit;
the third data input end of the first data selector is connected in parallel with the fourth data input end of the second data selector, the first data input end of the third data selector and the second data input end of the fourth data selector to form a third signal input end of the delay switching circuit;
the fourth data input end of the first data selector is connected in parallel with the third data input end of the second data selector, the second data input end of the third data selector and the first data input end of the fourth data selector to form a fourth signal input end of the delay switching circuit;
the output ends of the first data selector, the second data selector, the third data selector and the fourth data selector respectively form a first signal output end, a second signal output end, a third signal output end and a fourth signal output end of the time delay switching circuit,
the first address input ends of the first data selector, the second data selector, the third data selector and the fourth data selector are connected in parallel to form a first key input end of the delay switching circuit;
and second address input ends of the first data selector, the second data selector, the third data selector and the fourth data selector are connected in parallel to form a second key input end of the time delay switching circuit.
6. A switchable PUF circuit according to claim 5, characterized in that said decoding circuit comprises 6 identical arbiters, wherein,
the input signal end of the first arbiter is respectively connected with the first signal output end and the second signal output end of the delay switching circuit,
the input signal end of the second arbiter is respectively connected with the first signal output end and the third signal output end of the delay switching circuit,
the input signal end of the third arbiter is respectively connected with the first signal output end and the fourth signal output end of the delay switching circuit,
the input signal end of the fourth arbiter is respectively connected with the second signal output end and the third signal output end of the delay switching circuit,
the input signal end of the fifth arbiter is respectively connected with the second signal output end and the fourth signal output end of the delay switching circuit,
the input signal end of the sixth arbiter is respectively connected with the third signal output end and the fourth signal output end of the delay switching circuit,
the output signal ends of the first arbiter, the second arbiter, the third arbiter, the fourth arbiter, the fifth arbiter and the sixth arbiter are connected with the input end of the combinational logic circuit.
7. A switchable PUF circuit according to claim 6, wherein the combinational logic circuit comprises 8 AND gates, 2 XOR gates,
the input end of the first AND gate is respectively connected with the output ends of the first arbiter, the second arbiter and the third arbiter,
the input end of the second AND gate is respectively connected with the output ends of the first arbiter, the fourth arbiter and the fifth arbiter,
the input end of the third AND gate is respectively connected with the output ends of the second arbiter, the fourth arbiter and the sixth arbiter,
the input end of the fourth AND gate is respectively connected with the output ends of the third arbiter, the fifth arbiter and the sixth arbiter,
the input end of the fifth AND gate is respectively connected with the output ends of the first AND gate and the third AND gate, the input end of the sixth AND gate is respectively connected with the output ends of the first AND gate and the second AND gate,
the input end of the first exclusive-OR gate is respectively connected with the output ends of the second and-gate and the fourth and-gate, the input end of the second exclusive-OR gate is respectively connected with the output ends of the third and-gate and the fourth and-gate,
the input end of the seventh AND gate is respectively connected with the output end of the fifth AND gate and the output end of the first exclusive-OR gate, the input end of the eighth AND gate is respectively connected with the output end of the sixth AND gate and the output end of the second exclusive-OR gate, and the output ends of the seventh AND gate and the eighth AND gate respectively output two-bit output values.
8. A serial number output circuit comprising the PUF circuit according to any one of claims 1 to 7, wherein a plurality of sets of the PUF circuits are connected in parallel in series to constitute the serial number output circuit whose serial number is determined by the PUF circuit.
9. The serial number output circuit according to claim 8, wherein the serial number output circuit comprises m groups of PUF circuits connected in parallel, each PUF circuit outputs two-bit output values, so that the m groups of two-bit output values are sequentially arranged to form a 2 m-bit serial number.
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