CN117010032B - SRAM physical unclonable function circuit capable of automatically reading and clearing and equipment - Google Patents

Abstract

The application relates to an SRAM physical unclonable function circuit capable of automatically reading and clearing and equipment. The system comprises a logic gate module, a counting module, a data selecting module and an SRAM memory. By setting the initial value of the counting module, the output data of the counting module is changed along with the continuous accumulation of the counting module at the rising edge of each clock, so that the value of the address port is changed, and the automatic reading operation of the SRAM memory on different addresses is realized. After a specific clock period, the read-write enabling signal received by the SRAM memory is changed into write operation, and the counting module continuously accumulates along with the rising edge of each clock, so that the automatic zero clearing operation of the SRAM memory on different addresses is realized. The overall security of the integrated circuit is improved.

Description

SRAM physical unclonable function circuit capable of automatically reading and clearing and equipment

Technical Field

The application relates to the fields of electric digital data processing and information security, in particular to an SRAM physical unclonable function circuit and equipment capable of automatically reading and clearing.

Background

The physical unclonable function (Physically Unclonable Functions, PUF) is a hardware function implementation circuit which depends on chip characteristics and can be applied to the field of chip security. Because of the process variations in silicon-based integrated circuit processing technology, each integrated circuit produced is physically distinct. Between different integrated circuits, the circuit units which have the same domain area and are expressed by the process fluctuation have different path delays, transistor threshold voltages, voltage gains and the like. Although these variations are random between different integrated circuits, once the integrated circuits are manufactured, the physical differences on each integrated circuit are deterministic, and the random output value resulting from these physical differences is also deterministic and repeatable, so that the random output value of each integrated circuit can be used as its identification code. PUF technology exploits this inherent variation in integrated circuit manufacturing processes to generate a unique random output value for each integrated circuit that can be used for encryption.

PUF technology based on Static Random-Access Memory (SRAM) is a hardware security technology that utilizes SRAM Memory banks in integrated circuits to construct PUFs. The technique uses the power-on initial value of the SRAM unit as the unique random output value of the integrated circuit. In principle, each SRAM cell has two stable states representing 1 or 0, respectively. When a unit is powered on, the final power-up state is unpredictable. However, because of process variations in the integrated circuit during fabrication, random differences between transistors in the cells tend to occur at either 0 or 1 for each cell. For a block of SRAM cells, this produces a random array and can be a unique, unclonable output value for each integrated circuit. The random output value in the SRAM physically unclonable function circuit is determined upon power-up and no further change occurs. However, conventional SRAM physically unclonable function circuits are susceptible to intrusive attacks.

Disclosure of Invention

Based on this, it is necessary to provide an SRAM physically unclonable function circuit that is automatically read and cleared, and a data processing apparatus.

In order to achieve the above object, the embodiment of the present application adopts the following technical scheme:

on one hand, an SRAM physical unclonable function circuit capable of automatically reading and resetting is provided, which comprises a logic gate module, a counting module, a data selection module and an SRAM memory;

the first input end of the logic gate module is used for accessing external data, the second input end of the logic gate module is used for accessing a PUF control signal, and the output end of the logic gate module is connected with a data input port of the SRAM; the first input end of the counting module is used for accessing the PUF control signal, and the second input end of the counting module is used for accessing the clock signal;

the first input end of the data selection module is used for accessing a chip selection enabling signal, the second input end of the data selection module is used for accessing a read-write enabling signal, the third input end of the data selection module is used for accessing an address signal, the fourth input end of the data selection module is connected with the output end of the counting module, and the selection end of the data selection module is used for accessing a PUF control signal; the clock port of the SRAM memory is used for accessing a clock signal, the chip selection enabling port of the SRAM memory is connected with the first output end of the data selection module, the read-write enabling port of the SRAM memory is connected with the second output end of the data selection module, and the address port of the SRAM memory is connected with the third output end of the data selection module;

the logic gate module is used for shielding external data or writing the external data into the SRAM according to the PUF control signal; the counting module is used for outputting a counter signal according to the PUF control signal and the clock signal; the data selection module is used for selecting and outputting a counter signal or a peripheral control signal according to the PUF control signal; the SRAM memory is used for generating or resetting a physical unclonable random value according to the clock signal and the output of the data selection module; the counter signal includes a count signal or an initial value signal, and the peripheral control signal includes a chip select enable signal, a read/write enable signal, and an address signal.

In one embodiment, the logic gate module comprises a plurality of first inverters and a plurality of AND gates in one-to-one correspondence; the input end of each first inverter is respectively used for accessing the PUF control signal, and the output end of each first inverter is respectively connected with the first input end of each AND gate; the second input end of each AND gate is used for accessing external data respectively, and the output end of each AND gate is connected with the data input port of the SRAM memory respectively; the number of AND gates is equal to the data bit width of the SRAM memory.

In one embodiment, the counting module is a register, the bit width of the register is equal to n+2, and N is the address bit width of the SRAM memory; the counter signal includes the most significant bit, the next most significant bit, and the remaining bits.

In one embodiment, the initial value in the counting module is determined by the chip select enable polarity of the SRAM memory and the number of addresses to be read.

In one embodiment, the data selection module includes a first data selector, a second data selector, and a third data selector; the first input end of the first data selector is used for accessing a chip selection enabling signal, the second input end of the first data selector is used for accessing the highest bit of the counter signal, and the selection end of the first data selector is used for accessing the PUF control signal; the first input end of the second data selector is used for accessing the read-write enabling signal, the second input end of the second data selector is used for accessing the next highest order of the counter signal, and the selection end of the second data selector is used for accessing the PUF control signal; the third data selectors comprise N, the first input ends of the third data selectors are respectively used for accessing address signals, the second input ends of the third data selectors are respectively used for accessing N rest bits of the counter signals, and the selection ends of the third data selectors are respectively used for accessing PUF control signals; the output end of the first data selector is connected with a chip selection enabling port of the SRAM memory, the output end of the second data selector is connected with a read-write enabling port of the SRAM memory, and the output end of the third data selector is connected with an address port of the SRAM memory.

In one embodiment, the data selection module includes a first data selector, a second inverter, a second data selector, and a third data selector; the first input end of the first data selector is used for accessing a chip selection enabling signal, the second input end of the first data selector is used for accessing the highest bit of the counter signal, and the selection end of the first data selector is used for accessing the PUF control signal; the input end of the second inverter is used for accessing the next-highest bit transmission of the counter signal; the first input end of the second data selector is used for accessing the read-write enabling signal, the second input end of the second data selector is connected with the output end of the second inverter, and the selection end of the second data selector is used for accessing the PUF control signal; the third data selectors comprise N, the first input ends of the third data selectors are respectively used for accessing address signals, the second input ends of the third data selectors are respectively used for accessing N rest bits of the counter signals, and the selection ends of the third data selectors are respectively used for accessing PUF control signals; the output end of the first data selector is connected with a chip selection enabling port of the SRAM memory, the output end of the second data selector is connected with a read-write enabling port of the SRAM memory, and the output end of the third data selector is connected with an address port of the SRAM memory.

On the other hand, the data processing equipment is provided with the SRAM physical unclonable function circuit capable of automatically reading and clearing.

One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:

according to the SRAM physical unclonable function circuit and the equipment capable of automatically reading and clearing, the initial value of the counting module is set, the output data of the counting module is changed along with the continuous accumulation of the counting module at the rising edge of each clock, so that the value of an address port is changed, and the automatic reading operation of the SRAM memory on different addresses is realized. After a specific clock period, the next-higher output of the counting module is changed, the read-write enabling signal received by the SRAM memory is changed into write operation, and as the counting module continuously accumulates along with the rising edge of each clock, the output data of the counting module is continuously changed, so that the value of an address port is changed, and the automatic zero clearing operation of the SRAM memory on different addresses is further realized. Therefore, after the integrated circuit is powered on, the random value reading and resetting operation can be automatically completed, the probability of an invasive attack program to acquire the random value of the SRAM is reduced, and the overall safety of the integrated circuit is improved.

The logic gate module controls the writing and shielding of external data, when the PUF control signal is invalid, the circuit is equivalent to a common SRAM memory circuit, and a user can perform normal reading and writing operation on the SRAM memory, so that the resource utilization rate is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a first schematic diagram of a structure of an SRAM physical unclonable function circuit that is automatically read and cleared in one embodiment;

FIG. 2 is a second schematic diagram of the architecture of an SRAM physical unclonable function circuit that is automatically read and cleared in one embodiment;

FIG. 3 is a third schematic diagram of a structure of an SRAM physical unclonable function circuit that is automatically read and cleared in one embodiment;

FIG. 4 is a fourth schematic diagram of a structure of an SRAM physical unclonable function circuit that is automatically read and cleared in one embodiment;

FIG. 5 is a fifth schematic diagram of a structure of an SRAM physical unclonable function circuit that is automatically read and cleared in one embodiment;

FIG. 6 is a sixth schematic diagram of an SRAM physical unclonable function circuit that is automatically read and cleared in one embodiment.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element.

It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

In the process of researching and implementing the application, the inventor finds that a chip attacker performs invasive attack on all SRAMs in the integrated circuit after power-on, reads data values stored in the SRAMs and obtains random output values of the integrated circuit, and the random output values can threaten the safety of the integrated circuit.

Based on the above, the application provides an SRAM physical unclonable function circuit and equipment capable of automatically reading and clearing, by setting the initial value of the counting module, the output data of the counting module is changed along with the continuous accumulation of the counting module at the rising edge of each clock, thereby changing the value of an address port and further realizing the automatic reading operation of an SRAM memory on different addresses. After a specific clock period, the next-higher output of the counting module is changed, the read-write enabling signal received by the SRAM memory is changed into write operation, and as the counting module continuously accumulates along with the rising edge of each clock, the output data of the counting module is continuously changed, so that the value of an address port is changed, and the automatic zero clearing operation of the SRAM memory on different addresses is further realized. Therefore, after the integrated circuit is powered on, the random value reading and resetting operation can be automatically completed, the probability of an invasive attack program to acquire the random value of the SRAM is reduced, and the overall safety of the integrated circuit is improved. The logic gate module is used for controlling writing and shielding of external data, when the PUF control signal is 0, the circuit is equivalent to a common SRAM memory circuit, and a user can perform normal reading and writing operation on the SRAM memory, so that the resource utilization rate is improved.

Embodiments of the present application will be described in detail below with reference to the attached drawings in the drawings of the embodiments of the present application.

In one embodiment, as shown in fig. 1, an embodiment of the present application provides an SRAM physical unclonable function circuit 100 for automatic reading and clearing, which includes a logic gate module 11, a counting module 13, a data selecting module 15, and an SRAM memory 17.

The first input terminal of the logic gate module 11 is used for accessing external data, the second input terminal of the logic gate module 11 is used for accessing PUF control signals, and the output terminal of the logic gate module 11 is connected with the data input port of the SRAM memory 17. A first input of the counting module 13 is for accessing the PUF control signal and a second input of the counting module 13 is for accessing the clock signal.

The first input end of the data selection module 15 is used for accessing a chip selection enabling signal, the second input end of the data selection module 15 is used for accessing a read-write enabling signal, the third input end of the data selection module 15 is used for accessing an address signal, the fourth input end of the data selection module 15 is connected with the output end of the counting module 13, and the selection end of the data selection module 15 is used for accessing a PUF control signal. The clock port of the SRAM memory 17 is used for accessing a clock signal, the chip selection enabling port of the SRAM memory 17 is connected with the first output terminal of the data selecting module 15, the read-write enabling port of the SRAM memory 17 is connected with the second output terminal of the data selecting module 15, and the address port of the SRAM memory 17 is connected with the third output terminal of the data selecting module 15.

The logic gate module 11 is used for shielding external data or writing the external data into the SRAM memory 17 according to the PUF control signal; the counting module 13 is used for outputting a counter signal according to the PUF control signal and the clock signal; the data selecting module 15 is configured to select and output a counter signal or a peripheral control signal according to the PUF control signal; the SRAM memory 17 is used to generate or zero out a random value that is physically unclonable according to the clock signal and the output of the data selection module 15; the counter signal includes a count signal or an initial value signal, and the peripheral control signal includes a chip select enable signal, a read/write enable signal, and an address signal.

It will be appreciated that the logic gate module 11 may be constructed using various basic logic gates existing in the art, so long as it can determine whether to output external data to the SRAM memory 17 according to the input PUF control signal. The counting module 13 includes, but is not limited to, the use of registers or latches, as long as the up-counting and the restoration of the initial value can be performed according to the PUF control signal and the clock signal. The data selection module 15 may be implemented using a two-way, one-way, or one-way selector, or may be implemented using a two-way switch, so long as the selected input source is transferred to the SRAM memory by selecting and outputting between the plurality of input sources according to the PUF control signal.

Specifically, when the PUF control signal is valid (for example, a high level 1 or a low level 0 may be used to indicate that the signal is valid in this embodiment and the following description take a high level 1 as an example), the logic gate module 11 masks external data, the count module 13 continuously increases the count value along with each rising edge of the clock, the count signal output by the count module 13 changes, and the data selection module 15 selects to output the count signal, that is, the value of the count signal that is continuously changed, so as to change the value of the address port of the SRAM memory 17 accordingly, and further realize automatic reading operation of the SRAM memory 17 on different addresses, so that the SRAM memory 17 automatically generates a physical unclonable random value. After a specific clock period, the next-higher output of the counting signal of the counting module 13 is changed, the read-write enabling signal received by the SRAM memory 17 is changed into a write operation state, and the counting module 13 continuously increases the count value along with the rising edge of each clock, so that the output data of the counting module 13 is continuously changed, the value of the address port of the SRAM memory 17 is changed, the automatic zero clearing operation of the SRAM memory 17 on different addresses is further realized, and the SRAM memory 17 automatically clears the physical unclonable random value.

When the PUF control signal is 0, the logic gate module 11 writes external data into the SRAM memory 17, the counting module 13 does not count, the data selecting module 15 outputs an initial value signal (i.e., reset) of the counting module 13, the data selecting module 15 outputs a peripheral control signal, the peripheral control signal includes a chip select enable signal, a read/write enable signal and an address signal, the SRAM memory 17 reads or writes according to the peripheral control signal, at this time, the circuit is equivalent to a common SRAM memory circuit, and a user can perform normal read/write operation on the SRAM memory 17.

Because the random value reading and resetting operation can be automatically completed after the integrated circuit is powered on, the probability of an invasive attack program to acquire the random value of the SRAM 17 is reduced, and the overall safety of the integrated circuit is improved. The logic gate module 11 controls writing and shielding of external data, when the PUF control signal is 0, the circuit is equivalent to a common SRAM memory circuit, and a user can perform normal reading and writing operation on the SRAM memory 17, so that the resource utilization rate is improved.

In one embodiment, as shown in fig. 2, the logic gate module 11 includes a plurality of first inverters 111 and a plurality of and gates 113 in one-to-one correspondence.

The input end of each first inverter 111 is used for accessing PUF control signals respectively, and the output end of each first inverter 111 is connected with the first input end of each and gate 113 respectively; the second input end of each and gate 113 is used for accessing external data, and the output end of each and gate 113 is connected with the data input port of the SRAM memory 17; the number of and gates 113 is equal to the data bit width of the SRAM memory 17.

It will be appreciated that since the logic gate module 11 needs to choose whether or not to write external data to the SRAM memory 17 based on the PUF control signal, the data bit width of the SRAM memory 17 determines the number of bits of external data that it can accept at a time. To enable the logic gate module 11 to fully control the masking or writing of all data of the SRAM memory 17, the number of and gates 113 needs to be set equal to the data bit width of the SRAM memory 17. The circuit connection relationship between each pair of first inverters 111 and their corresponding and gates 113 can be understood in the same way.

When the PUF control signal is 1, the signal is inverted by the first inverter 111 and then output 0, and the signal is further inverted by the and gate 113 and a bit of external data signal, so that the and gate 113 outputs 0, and one bit of external data can be masked. Such a plurality of and gates 113 and inverters 111, which are one-to-one, can mask all external data.

When the PUF control signal is 0, the signal is inverted by the first inverter 111 and then output 1, and the signal is further inverted by the and gate 113 and a bit of external data signal, so that the and gate 113 outputs a value equal to the bit of external data. Thus, a plurality of and gates 113 and inverters 111, which are one-to-one, can write all external data into the SRAM memory 17.

The logic gate module 11 of the scheme can shield external data according to the PUF signals or write the data into the SRAM 17, so that the design is concise, and the cost and the design difficulty are effectively reduced while the function is ensured.

In one embodiment, as shown in fig. 3, the counting module 13 is a register, the bit width of the register is equal to n+2, and N is the address bit width of the SRAM memory 17; the counter signal includes the most significant bit, the next most significant bit, and the remaining bits.

It will be appreciated that the register has a counting function, the stored data of which can be added 1 by a clock signal, the output of the register can be restored to an initial value by a control signal, and the register is an ideal choice for the counting module 13.

The counter signal comprises three parts: the most significant bit, the next most significant bit, and the remaining bits. The most significant bit is used to provide the other input of the chip select enable signal to the data selecting module 15, the next most significant bit is used to provide the other input of the read/write enable signal to the data selecting module 15, the remaining bits are used to provide the other input of the address signal to the data selecting module 15, and if the address bit width of the SRAM memory 17 is N, the register has N remaining bits. For the SRAM memory 17 of N-bit address width, the total bit width of the register of the counting module 13 is the sum of the most significant bit, the next most significant bit, and N remaining bits, and the calculation result is n+2 bits.

In this embodiment, a chip select enable signal, a read-write enable signal and an address signal can be generated by using an n+2-bit wide register, so that the SRAM memory 17 is controlled in all directions, the circuit design is simplified, and the system cost is reduced.

In one embodiment, the initial value in the counting module 13 is determined by the chip select enable polarity of the SRAM memory 17 and the number of addresses that need to be read.

Specifically, when the chip select enable is 1, the n+2th bit initial value of the counting module 13 is set to 1, and when the chip select enable is 0, the n+2th bit initial value of the counting module 13 is set to 0. The n+1th bit of the counting module 13 has an initial value of 0. The initial values of the N-th bit to the 1-th bit of the counting module 13 are determined by the number of addresses to be read, and if the data in the K addresses need to be read, the initial values of the N-th bit to the 1-th bit of the counting module 13 are N-K.

By setting the initial value of the counting module 13, the initial values from the nth bit to the 1 st bit of the counting module 13 are continuously accumulated along with the rising of each clock, so that the value of the address port is changed, and the automatic reading operation of the SRAM 17 on different addresses is realized. Because the initial value from the nth bit to the 1 st bit of the counting module 13 is N-K, after K clock cycles, the n+1st bit of the counting module 13 is changed, the read-write enabling signal received by the SRAM memory 17 is changed into writing operation, and the initial value from the nth bit to the 1 st bit of the counting module 13 is continuously accumulated along with the rising edge of each clock, so that the value of an address port is changed, and further, the automatic zero clearing operation of the SRAM memory 17 on different addresses is realized. Therefore, the random value reading and resetting operation can be automatically completed after the integrated circuit is powered on, the probability of the random value of the SRAM 17 obtained by an invasive attack program is reduced, and the overall safety of the integrated circuit is improved.

In one embodiment, as shown in fig. 4, the data selection module 15 includes a first data selector 151, a second data selector 153, and a third data selector 155.

A first input of the first data selector 151 is for accessing the chip select enable signal, a second input of the first data selector 151 is for accessing the most significant bit of the counter signal, and a select of the first data selector 151 is for accessing the PUF control signal. The first input of the second data selector 153 is for accessing the read-write enable signal, the second input of the second data selector 153 is for accessing the next highest order of the counter signal, and the select of the second data selector 153 is for accessing the PUF control signal. The third data selectors 155 include N, the first input terminal of each third data selector 155 is used for accessing an address signal, the second input terminal of each third data selector 155 is used for accessing N remaining bits of the counter signal, and the selection terminal of each third data selector 155 is used for accessing a PUF control signal.

An output terminal of the first data selector 151 is connected to a chip select enable port of the SRAM memory 17, an output terminal of the second data selector 153 is connected to a read/write enable port of the SRAM memory 17, and an output terminal of the third data selector 155 is connected to an address port of the SRAM memory 17.

It will be appreciated that the data selector performs selection output between the counter signal and the peripheral control signal, and may be an alternative data selector.

Specifically, when the PUF control signal is 1, the first data selector 151 selects the highest bit of the output count signal for outputting as a chip select enable signal to the chip select enable port of the SRAM memory 17, the second data selector 153 selects the next highest bit of the output count signal for outputting as a read/write enable signal to the read/write enable port of the SRAM memory 17, and each third data selector 155 selects the remaining bits of the output count signal for outputting as an address signal to the address port of the SRAM memory 17.

The read operation is effectively performed when the read/write enable polarity of the SRAM memory 17 is set to 0, and the write operation is effectively performed when 1. The rising edge count signal of each clock is changed continuously, the address signal at the lower level is changed firstly, and the SRAM memory 17 performs read operation because the initial value of the next higher level is set to 0, so that the automatic read operation of the SRAM memory 17 on different addresses is realized. After a certain clock period, the next higher order bit becomes 1, and as the count signal continues to change with each clock rising edge, the address signal at the lower order bit also changes, and since the next higher order bit has become 1, the sram memory 17 will perform an automatic zero clearing operation. Thus, under the action of the control signal, the automatic reading and clearing of the SRAM memory 17 is controlled according to the counting signal.

Therefore, the random value reading and resetting operation can be automatically completed after the integrated circuit is powered on, the probability of the random value of the SRAM 17 obtained by an invasive attack program is reduced, and the overall safety of the integrated circuit is improved.

In one embodiment, as shown in fig. 5, the data selection module 15 includes a first data selector 151, a second inverter 152, a second data selector 153, and a third data selector 155.

A first input of the first data selector 151 is for accessing the chip select enable signal, a second input of the first data selector 151 is for accessing the most significant bit of the counter signal, and a select of the first data selector 151 is for accessing the PUF control signal. The input of the second inverter 152 is used to access the next highest bit of the counter signal. The first input terminal of the second data selector 153 is for accessing the read-write enable signal, the second input terminal of the second data selector 153 is connected to the output terminal of the second inverter 152, and the selection terminal of the second data selector 153 is for accessing the PUF control signal. The third data selectors 155 include N, the first input terminal of each third data selector 155 is used for accessing an address signal, the second input terminal of each third data selector 155 is used for accessing N remaining bits of the counter signal, and the selection terminal of each third data selector 155 is used for accessing a PUF control signal.

An output terminal of the first data selector 151 is connected to a chip select enable port of the SRAM memory 17, an output terminal of the second data selector 153 is connected to a read/write enable port of the SRAM memory 17, and an output terminal of the third data selector 155 is connected to an address port of the SRAM memory 17.

It will be appreciated that the data selector performs selection output between the counter signal and the peripheral control signal, and may be an alternative data selector.

Specifically, when the PUF control signal is 1, the first data selector 151 selects the highest bit of the output count signal to be used as the chip select enable signal to be output to the chip select enable port of the SRAM memory 17, the second data selector 153 selects the next highest bit of the count signal inverted by the second inverter to be output to the read/write enable port of the SRAM memory 17, and each of the third data selectors 155 selects the remaining bits of the output count signal to be output to the address port of the SRAM memory 17.

The read operation is effectively performed when the read/write enable polarity of the SRAM memory 17 is set to 1, and the write operation is effectively performed when 0. The rising edge count signal of each clock is changed continuously, the address signal at the lower position is changed firstly, and the next-higher initial value is set to 0, and then is changed to 1 after being inverted by the second inverter 152, and the SRAM 17 performs the read operation, so that the automatic read operation of the SRAM 17 on different addresses is realized. After a certain clock period, the next higher order bit becomes 1, the address signal at the lower order bit also changes as the count signal continues to change at each clock rising edge, and since the next higher order bit has become 1, it is inverted by the inverter 152 and then becomes 0, and the sram memory 17 will perform an automatic zero clearing operation. Thus, under the action of the control signal, the automatic reading and clearing of the SRAM memory 17 is controlled according to the counting signal.

Therefore, the random value reading and resetting operation can be automatically completed after the integrated circuit is powered on, the probability of the random value of the SRAM 17 obtained by an invasive attack program is reduced, and the overall safety of the integrated circuit is improved.

In some embodiments, in order to more intuitively and fully describe the above-described SRAM physically unclonable function circuit that is automatically read and cleared, the following is an application example of the SRAM physically unclonable function circuit that is automatically read and cleared. It should be noted that, the embodiments given in the present specification are only illustrative, and not the only limitation of the specific embodiments of the present application, and those skilled in the art may use the SRAM physical unclonable function circuit capable of automatically reading and clearing as described above to improve the overall security of the integrated circuit under the illustration of the embodiments provided by the present application.

As shown in fig. 6, a single-port SRAM memory circuit having a capacity of 64×256 is selected, which includes 256-bit data input terminals D (for accessing external data), 256-bit data output terminals Q, 1-bit chip enable input terminals CEN (for accessing chip enable signals), 1-bit read/write enable input terminals WEN (for accessing read/write enable signals), 1-bit clock input terminals CLK (for clock signals), and 6-bit address input terminals a (for inputting address signals).

An 8-bit wide counter is selected. The main function of the counter is that the counter is incremented by 1 along with the rising edge of the clock when the control signal is 1, and the counter is restored to the initial value when the control signal is 0. Since the chip select enable terminal CEN of the single-port SRAM memory circuit is valid to 0, the initial value of the 8 th bit of the counter is 0. In this embodiment, since 30 addresses need to be read, the initial values of the 6 th to 1 st bits of the counter are 34 (64-30=34), and the binary value is 100010. Thus, the binary initial value of the 8-bit wide counter is determined to be 00100010.

256 AND gate standard cells and 256 inverter cells are selected. The output end of the AND gate unit is connected with the data input end D of the single-port SRAM memory circuit. The input end A of the AND gate unit is connected with the data input end D of the top-layer circuit, the input end B of the AND gate unit is connected with the output end of the inverter, and the input end of the inverter is connected with the PUF control signal.

1 alternative unit is selected, the output end of the alternative unit is connected with the chip selection enabling end CEN of the single-port SRAM circuit, the 0 input end of the alternative unit is connected with the chip selection enabling port of the top layer, and the 1 input end of the alternative unit is connected with the 8 th bit output end of the counter circuit. The selection end of the alternative unit is connected with the PUF control signal.

1 alternative unit is selected, the output end of the alternative unit is connected with the read-write enabling end WEN of the single-port SRAM circuit, and the 0 input end of the alternative unit is connected with the read-write enabling port of the top layer. Since the read operation is performed when the read-write enable of the SRAM circuit is 1, the write operation is performed when it is 0. Therefore, an inverter unit needs to be additionally arranged in front of the 1 input end of the alternative unit. The 1 input end of the alternative unit is connected with the output end of the inverter unit, and the input end of the inverter unit is connected with the 7 th bit output end of the counter circuit. The selection end of the alternative unit is connected with the PUF control signal.

And 6 alternative units are selected, the output end of each alternative unit is connected with the address port A of the single-port SRAM circuit, and the 0 input end of each alternative unit is connected with the address port on the top layer of the SRAM PUF circuit. The 1 input end of the alternative unit is sequentially connected with the N-bit to 1-bit output end of the counter circuit. The selection end of the alternative unit is connected with the PUF control signal.

When the PUF control signal is 0, the SRAM PUF circuit in this embodiment is equivalent to a common single-port SRAM memory circuit, and a user can perform normal read/write operation on the SRAM memory. When the PUF control signal is 1 after the chip is powered on, the SRAM PUF circuit in this embodiment starts to perform a read operation and a clear operation. After the PUF control signal is 1, the data input D of the single-port SRAM circuit is set to 0. The output end of the counter circuit is connected to a chip selection enable signal CEN, a read-write enable signal WEN and an address signal a of the single-port SRAM circuit through a one-out-of-two unit. The counter bit 8 output sets the CEN of the single port SRAM circuit to 0, at which time the SRAM chip select enable signal is active. After the 7 th bit output terminal passes through the inverter, the WEN terminal of the single-port SRAM circuit is set to 1, and at this time, a read operation is performed. Along with the continuous 1-adding of each clock rising edge counter, the output data of the counter circuit is changed, the value of the address end A is changed, and the automatic reading operation of different addresses is realized. After 30 clock cycles, the 7 th bit output terminal becomes 1, and the WEN signal of the single port SRAM circuit is set to 0 after passing through the inverter, at which time the write operation is performed. Along with the continuous 1-adding of each clock rising edge counter, the output data of the counter circuit is continuously changed, the value of the address port A is changed, and the automatic zero clearing operation of different addresses is realized. After 64 clock cycles, the PUF control signal is set to 0, and the circuit completes automatic reading and zero clearing operations.

In one embodiment, the present application provides a data processing apparatus, including an SRAM physically unclonable function circuit that is automatically read and cleared as provided in any of the embodiments above.

It will be appreciated that, regarding the circuit structure in each embodiment of the data processing apparatus, the same will be understood with reference to the corresponding circuit structure in each embodiment of the SRAM physical unclonable function circuit that is automatically read and cleared, and the detailed description will not be repeated here and hereinafter.

In particular, the data processing device may be, but is not limited to, a server, a computer, a cell phone, and an cryptocurrency device. It will be appreciated by those skilled in the art that the data processing apparatus may include other necessary components not described in addition to the SRAM physically unclonable function circuit for automatic reading and clearing, and in particular, the data processing apparatus may be understood by referring to the existing components of various data processing apparatuses in the art.

The random value reading and resetting operation can be automatically completed after the data processing equipment is powered on, so that the probability of the random value of the data processing equipment of the invasive attack program is reduced, and the safety of the data processing equipment is improved.

In the device processor, when the PUF control signal is 0, the SRAM physical unclonable function circuit which is automatically read and cleared is equivalent to a common SRAM memory circuit, and a user can perform normal read-write operation on the SRAM memory, thereby improving the resource utilization rate.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (7)

1. An SRAM physical unclonable function circuit capable of automatically reading and resetting is characterized by comprising a logic gate module, a counting module, a data selection module and an SRAM memory;

the first input end of the logic gate module is used for accessing external data, the second input end of the logic gate module is used for accessing a PUF control signal, and the output end of the logic gate module is connected with the data input port of the SRAM; the first input end of the counting module is used for accessing the PUF control signal, and the second input end of the counting module is used for accessing a clock signal;

the first input end of the data selection module is used for accessing a chip selection enabling signal, the second input end of the data selection module is used for accessing a read-write enabling signal, the third input end of the data selection module is used for accessing an address signal, the fourth input end of the data selection module is connected with the output end of the counting module, and the selection end of the data selection module is used for accessing the PUF control signal; the clock port of the SRAM memory is used for accessing the clock signal, the chip selection enabling port of the SRAM memory is connected with the first output end of the data selection module, the read-write enabling port of the SRAM memory is connected with the second output end of the data selection module, and the address port of the SRAM memory is connected with the third output end of the data selection module;

the logic gate module is used for shielding the external data or writing the external data into the SRAM according to the PUF control signal; the counting module is used for outputting a counting signal according to the PUF control signal and the clock signal; the data selection module is used for selecting and outputting a counter signal or a peripheral control signal according to the PUF control signal; the SRAM memory is used for generating or resetting a physical unclonable random value according to the clock signal and the output of the data selection module; when the PUF control signal is valid, the counting signal output by the counting module is increased according to the clock signal, the data selecting module selects to output the counting signal, the SRAM memory automatically reads different addresses according to the clock signal and the increased counting signal, a physical unclonable random value is automatically generated, after a clock period is set, the next-higher bit of the counting signal output by the counting module is changed, the SRAM memory performs a writing operation, the counting signal is continuously increased according to the clock signal, the data selecting module selects to output the counting signal, the SRAM memory automatically clears different addresses according to the clock signal and the increased counting signal, and the physical unclonable random value is automatically cleared; the counter signal includes the count signal or an initial value signal, and the peripheral control signal includes the chip select enable signal, the read-write enable signal, and the address signal.

2. The automatic read and clear SRAM physically unclonable function circuit of claim 1, wherein the logic gate module comprises a plurality of first inverters and a plurality of and gates in one-to-one correspondence;

the input end of each first inverter is respectively used for accessing the PUF control signal, and the output end of each first inverter is respectively connected with the first input end of each AND gate; the second input end of each AND gate is respectively used for accessing the external data, and the output end of each AND gate is respectively connected with the data input port of the SRAM; the number of AND gates is equal to the data bit width of the SRAM memory.

3. The automatic read and clear SRAM physical unclonable function of claim 1 or 2, wherein the counting module is a register having a bit width equal to n+2, N being an address bit width of the SRAM memory; the counter signal includes a most significant bit, a next most significant bit, and a remaining bit.

4. The automatic read and clear SRAM physically unclonable function of claim 3, wherein the initial value in the count module is determined by the chip select enable polarity of the SRAM memory and the number of addresses to be read.

5. The auto-read and clear SRAM physical unclonable function circuit of claim 4, wherein the data selection module comprises a first data selector, a second data selector, and a third data selector;

the first input end of the first data selector is used for accessing the chip selection enabling signal, the second input end of the first data selector is used for accessing the highest bit of the counter signal, and the selection end of the first data selector is used for accessing the PUF control signal;

the first input end of the second data selector is used for accessing the read-write enabling signal, the second input end of the second data selector is used for accessing the next highest bit of the counter signal, and the selection end of the second data selector is used for accessing the PUF control signal;

the third data selectors comprise N, the first input end of each third data selector is used for being connected with the address signal, the second input end of each third data selector is used for being connected with N rest bits of the counter signal, and the selection end of each third data selector is used for being connected with the PUF control signal;

the output end of the first data selector is connected with a chip selection enabling port of the SRAM, the output end of the second data selector is connected with a read-write enabling port of the SRAM, and the output end of the third data selector is connected with an address port of the SRAM.

6. The automatic read and clear SRAM physical unclonable function circuit of claim 4, wherein the data selection module comprises a first data selector, a second inverter, a second data selector, and a third data selector;

the first input end of the first data selector is used for accessing the chip selection enabling signal, the second input end of the first data selector is used for accessing the highest bit of the counter signal, and the selection end of the first data selector is used for accessing the PUF control signal;

the input end of the second inverter is used for accessing the next-highest bit transmission of the counter signal;

the first input end of the second data selector is used for accessing the read-write enabling signal, the second input end of the second data selector is connected with the output end of the second inverter, and the selection end of the second data selector is used for accessing the PUF control signal;

the third data selectors comprise N, the first input end of each third data selector is used for being connected with the address signal, the second input end of each third data selector is used for being connected with N rest bits of the counter signal, and the selection end of each third data selector is used for being connected with the PUF control signal;

the output end of the first data selector is connected with a chip selection enabling port of the SRAM, the output end of the second data selector is connected with a read-write enabling port of the SRAM, and the output end of the third data selector is connected with an address port of the SRAM.

7. A data processing device comprising an SRAM physically unclonable function circuit for automatic reading and clearing according to any of claims 1-6.