CN109495272A - A kind of strong PUF circuit based on memristor - Google Patents
A kind of strong PUF circuit based on memristor Download PDFInfo
- Publication number
- CN109495272A CN109495272A CN201811289819.9A CN201811289819A CN109495272A CN 109495272 A CN109495272 A CN 109495272A CN 201811289819 A CN201811289819 A CN 201811289819A CN 109495272 A CN109495272 A CN 109495272A
- Authority
- CN
- China
- Prior art keywords
- module
- puf
- column
- row
- address generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Abstract
The invention belongs to field of information security technology, specially a kind of strong physics based on memristor does not clone function (PUF) circuit.PUF circuit of the invention includes: non-volatile storage array and 2T2R basic unit, for generating the row address generation module of row selects signal and column selection signal, column address generation module, comparing address generation module, it is responsible for the PUF column selector of address decoding, PUF line decoder, compares electric current column selection module, for generating the readings of reading and writing, comparison signal, set module and comparing, reseting module, and the reading circuit module for reading circuit, for the Mbit register & counter module of temporary store results, and improve the multiple exclusive or module of anti-modeling attack.The invention also provides a set of operating processes for improving memristor strong PUF area utilization and randomness.The strong PUF circuit of memristor proposed by the present invention possesses area utilization height, and the feature that can configure and reuse has excellent randomness and anti-modeling attacking ability.
Description
Technical field
The invention belongs to field of information security technology, and in particular to a kind of strong physics based on memristor does not clone function
(Physically Unclonable Function, PUF) circuit.
Background technique
With the rapid development of electronic technology, the rise of technology of Internet of things, people's lives increasingly be unable to do without electronics and produce
While product, also have in face of an increasingly serious problem, the i.e. safety certification and privacy problem of hardware, especially in private
People and military field.Physics does not clone function (Physically Unclonable Function, PUF) and traditional password
Authentication mode is compared, it does not need to save password, but passes through the physics such as fluctuation and difference of the circuit devcie in manufacture craft
Feature forms excitation response pair (Challenge and Response Pairs, CRPs), each input motivates
(Challenge) by, according to its distinctive physical characteristic output response (Response), there is superior safety after a PUF
Property, therefore have wide application prospects in digital authenticating and area of security.Weak PUF and strong can be divided into according to the quantity of excitation response pair
PUF, weak PUF only have a small amount of CRPs, and strong PUF has sufficient CRPs and its circuit area exponent function relation, and strong PUF is to CRP
Access there is no limit, manufacturers to select specific CRPs for subsequent applications after hardware completes manufacture.With weak PUF phase
Than strong PUF is widely used in authentication circuit.For strong PUF due to the CRPs of its exponential relationship, each CRP can be disposable simultaneously,
To avoid a small amount of CRP leakage that code key is caused to be cracked.Current strong PUF is mainly made of cmos circuit, such as moderator PUF
It is the strong PUF of CMOS a kind of, it generates random response, different excitations by comparing the delay on the similar sub- road of two-strip structure
Determine that the component for constituting two strip roads is different, but the type PUF safety is poor, in order to improve its safety and response
Digit, moderator PUF are extended to: the hybrid circuit of SRAM and moderator, light-type PUF etc..The other kinds of strong PUF of CMOS
There are also ring oscillator PUF, bistable state annular (Bistable Ring) PUF.But the PUF circuit based on CMOS, often have
There is the attack that randomness is poor, area efficiency is low, can not resist machine learning.
The performance of PUF is often related with the entropy source of selection, based on the memory of novel memristor, such as resistance-variable storing device,
Magnetic storage, ferroelectric memory, phase transition storage etc., when external electric field or magnetic field strength reach certain threshold value, the resistance of device
Value can convert between high resistant and low-resistance.Due to the dispersibility of its natural threshold value randomness and high low resistance, novel memristor
Memory can be used as good PUF entropy source.They are low with operation voltage, structure is simple, storage density is high, power consumption
Small, the features such as read or write speed is fast.The randomness of its entropy source not only can be improved also using novel memristor memory device production PUF
Safety can be improved.
United States Patent (USP) US8938069B2 proposes a kind of strong PUF structure based on transistor threshold voltage fluctuation, the program
An output is obtained by comparing the size of the output voltage of two identical structural circuits generations.Defect existing for the program
It is, when needing to obtain a large amount of CRPs, large number of CMOS tube to be needed to connect, it is therefore desirable to very high supply voltage, in reality
It cannot achieve in the application of border.
Chinese patent CN105760786 proposes the strong PUF system of CPU+FPGA a kind of, by converting pumping signal to
Configuration information is sent to CPU, then does not clone functional circuit to physics on FPGA in a manner of partial reconfigurable and configure, most
The response of generation is returned into certification end afterwards to complete to authenticate, such as Fig. 1.Although program safety is higher, with high costs,
Circuit is complicated, still there is certain gap apart from large-scale application.
RekhaGovindaraj team is in paper (A Strong Arbiter PUF using Resistive RAM
Within 1T-1R Memory Architecture, 2016) a kind of resistance-variable storing device array (Resistive is proposed in
Random Access Memory, RRAM) circuit structure that combines of array and moderator, according to given RRAM array address
Read response obtains an output, such as Fig. 2, but circuit design RRAM array and secondary as the input of CMOS arbiter circuit
Device PUF is cut out, circuit area is too big, is not suitable for embedded integration application.
Daniel Arumi et al. is in paper (RRAM Based Random Bit Generation for Hardware
Security Applications) in propose a kind of tandom number generator, during set, allow transistor to be in half and be connected
State, when memristor in parallel have one by first set at low-resistance when, all-in resistance decline in parallel, according to the most of electricity of voltage divider principle
Transistor both ends are connected to half in pressure drop, and memristor both end voltage declines therewith, another memristor is prevented to be set to low-resistance immediately, and
Receipts or other documents in duplicate member forms one high and one low resistance value, such as Fig. 3, finally extracts the resistance value of left side memristor as random number.But program face
The characteristics of the problem of facing is: twice of needs or more of memristor set and resetting voltage, is unable to satisfy memristor low-power consumption；And
The program belongs to random number and weak PUF, can not form a large amount of CRPs, can not achieve strong PUF.
Elena IoanaVatajelu et al. paper (STT-MRAM-Based Strong PUF Architecture,
2015 IEEE Computer Society Annual Symposium on VLSI) in propose using high-impedance state resistance
Random distribution, by the combination of multiple row RRAM array, comparison combination electric current and referential array total current export one and respond, and by
The input stimulus of user determines the combinations of different lines, and such as Fig. 4, referential array is identical with RRAM array area, their rows
Column decoder is identical, compares that electric current is bigger, and the fuzzy state that can not compare is also just less.If columns is total 2n, the program can
With the n times side of generation 2 to CRP, but the program is disadvantageous in that: when full column selection and single-row selection, comparing electric current column
Select size variation very big, and when in full column selection, power consumption is big；Program area is bigger than normal simultaneously cannot but effectively improve solution sky
Between, double area is needed, for needing the application field of large capacity CRPs, area will be difficult to receive.While the program is simultaneously
Any scheme for improving its anti-modeling attack, under deep neural network and the attack of integrated study scheduling algorithm, safety are not proposed
It is insufficient.
Therefore, it is necessary to propose a kind of there is high area efficiency and high randomness, structure be simple, anti-modeling is attacked
Novel strong PUF structure.
Summary of the invention
It is an object of the invention to propose that a kind of novel strong PUF(physics based on memristor does not clone function) circuit,
The characteristics of making it have high area efficiency, high randomness, exponential solution space, anti-modeling attack, and can be mutually simultaneous with logic process
Hold.
Strong PUF circuit proposed by the present invention based on memristor, structure chart are as shown in Figure 5, comprising: 2T2R is substantially single
Member, the non-volatile storage array of PUF are read and set module 301, PUF column selector 302, column address generation module 303, row address
Generation module 304, PUF line decoder 305 compare address generation module 306, compare electric current column selection module 307, compare, is multiple
Position module 308, reading circuit module 309, multiple exclusive or module 310, Mbit register & counter module 311；Wherein:
(1) the 2T2R basic unit (401 to 406 ..., 40A, 40B), the unit including two 1T1R, or including two
1D1R unit；Wherein R is memristor, is resistance-variable storing device, magnetic storage, ferroelectric memory or phase transition storage；T is crystal
Pipe, D is diode, which allows it to be in fully conducting state or portion by transistor wordline/diode level control
Divide on state (resistance of conducting left or right), in the case where connecting voltage divider principle or parallel shunt principle, resistance value
In one high and one low state, or it is in the full low state of overall height；
2T2R can be PUF resistance-variable storing device, phase transition storage, EEPEOM or Flash by the basic of floating gate charge storage
Unit.The unit can be form in parallel, and the write current provided is by parallel shunt by resistance set at one high and one low shape
State.It is also possible to concatenated form, what is provided writes voltage by series connection partial pressure, and resistance is reset to one high and one low state.
(2) the non-volatile storage array of the PUF is made of M*N basic unit of storage, shares M row N column；It generates every time
Before key, which is initialized, columns and rows are scanned respectively, successively control each storage unit, provided twice and set
Position signal, by each storage unit set at the state of one low-resistance of a high resistant；With the storage unit in a line by two words
Line traffic control, or controlled by a plurality of wordline；
The wordline (LEFT, WL2_1, WL3_1, WLM_1) of every all left side transistors of row 2T2R unit is connected, the right word transistor
Line (RIGHT, WL2_2, WL3_2, WLM_2) is all connected, and when wordline (WL series) is high level, represents selected (conducting),
Such as RIGHT wordline, when being high level, transistor all gates on the right of the first row.All 2T2R units of every row can simultaneously by
Its whole is chosen, and can also partially choose: simultaneously turning on the transistor (all choosing) on a line left side and the right, or is only connected
The transistor on the left side or the transistor (partially choosing) on the right in a line.It can be by the left side wordline phase of a line 2T2R unit
Even, the right wordline, which is connected, or each transistor individually the methods of is controlled with decoder can realize that part is chosen and Quan Xuan
Middle 2T2R unit.
(3) reading and set module 301 are respectively the non-volatile storage array of PUF and reference electricity during read operation
It hinders array and identical read signal is provided；During set, double write signal is provided to corresponding storage unit, is formed it into
One high and one low distribution of resistance；
Specifically, according to it in read operation and set operation, different size of current or voltage is provided to PUF and stores battle array
Column.When input terminal set signal (WRITE signal) is 1, the reading, the output of set module 301 write-operation current from 0 to twice
The current signal gradually increased, when input terminal read signal (READ signal) is 1, the reading, set module 301 export reading respectively
Signal is to the referential array in PUF storage array and reading circuit module 309.Different according to structure in 2T2R, the physical attribute of R is not
Together, set signal, which can be, writes voltage and is also possible to write current, according to voltage divider principle or shunting principle, two resistance due to from
Body physical difference can be set to one high and one low mode, such as concatenated 2T2R structure can be used for RRAM, use two
Write operation set signal again can for magnetic RAM (Magnetic Random Access Memory, MRAM)
Using 2T2R structure in parallel, twice of write-operation current is used.It is described read, set module 301 may include feed circuit with
Output signal is closed in time.
(4) the PUF line decoder 305 has the function of successively choosing every row entirely, that is, sequentially turns on every row 2T2R unit
All transistors；PUF line decoder 305 also has the function of successively partially choosing every row, that is, sequentially turns on each 2T2R of every row
The function of one of R of unit, for example every row left side transistor can be sequentially turned on；PUF line decoder 305 also has simultaneously
The 2T2R unit part of all rows is chosen, for example simultaneously chooses upper half branch 2T2R unit left side R, lower half branch
R chooses on the right of 2T2R unit；PUF line decoder 305 has the function of configurable modes, it can the random full conducting of selection or portion
The different mode of point conducting X row, such as can arbitrarily select wherein X row for M*N array, their left sides or the right is all connected
Or whole 2T2R unit, therefore by the way that its solution space can be significantly expanded；PUF line decoder 305 can also be in set-reset
During choose multiple storage units simultaneously, while carrying out write operation, improve efficiency.
(5) the column address generation module 303, output are the input of PUF column selector 302, PUF column selector 302
Output signal controls PUF storage array.
(6) the row address generation module 304 is connected with PUF line decoder 305, the output of row address generation module 304
As the input of PUF line decoder 305, the output of PUF line decoder 305 is as the defeated of the non-volatile storage array of PUF (30MN)
Enter；
The column address generation module 303 and row address generation module 304, when work, row address generation module/column address is generated
Module is write, comparison signal generates row address/column address, and is transferred to corresponding PUF according to clock, user's input, reading
Row/column decoder.
(7) the PUF column selector 302 has the function of successively choosing each column, is also inputted according to user and choose PUF non-
A certain particular column in the N column of volatilization storage array.
(8) the relatively address generation module 306, for generating any two column in the column of N in the non-volatile storage array of PUF
Address is inputted as electric current column selection module 307 is compared.
(9) the relatively electric current column selection module 307, according to two in the non-volatile storage array of user input selection PUF
Column or multiple row, make it be connected with reading circuit module, carry out size of current comparison；It can also be no more than in curent change and size and read
Under conditions of the critical value of circuit, multiple row (more than 2 column) progress total current or all-in resistance is selected to compare；
Compare address generation module 306 and compare the co-operation of electric current column selection module 307, comparing address generation module 306 can
To generate the address of any two column in N column, is inputted as electric current column selection module 307 is compared, gate the non-volatile storage array of PUF
(30MN) two is arranged.
(10) comparison, reseting module 308, provide resetting voltage, provide read signal in relatively size of current, are setting
When position, corresponding line is all grounded, set operation requirement is met；The comparison, reseting module 308 in read operation or are set
When bit manipulation, it is grounded all SL from the non-volatile storage array of PUF (30MN), when comparison signal (COMP signal) is 1,
Comparison voltage is provided, when reset signal (RESET signal) is 1, provides resetting voltage or electric current to 30MN.
(11) the reading circuit module 309, multiple selector including RRAM referential array and reading circuit inside modules and
Sense amplifier, reading circuit module 309 respectively with compare electric current column selection module 307, PUF column selector 302 and M bit and post
Storage & counter module 311 is connected；In first time readout, the reference voltage and PUF column selector 302 of referential array
Read voltage be compared to obtain a response deposit Mbit register & counter module 311, operation M times is executed, by Mbit
Response is all stored in Mbit register & counter module 311；When comparison signal (COMP signal) is 1, i.e. second of reading
When, the two column electric currents that electric current column selection module 307 provides will be compared and be compared, using comparison result as output, described in deposit
In the multidigit output module of multiple exclusive or module 310；Referential array module is made of in series and parallel multiple non-volatile memory resistors, function
The median of high low resistance, fights technological fluctuation when can be to generate nonvolatile memory cell work；Sense amplifier is according to two-way
Input signal, which amplifies, to be compared, and is exported and is read result to multiple exclusive or module 310 or Mbit register & counter module 311；
The reading circuit module 309, sense amplifier therein can be voltage difference amplifier, that is, compare two input terminal voltages
Size is also possible to current differential amplifier, that is, compares the size of two electric currents.
(12) the M bit register & counter module 311 is connected with row address generation module 304, due to there is M row
2T2R unit, so the register size in M bit register counter module 311 is also M bit, counter is calculated to M times
When, first time read operation is completed.By the M bit data transmission in register to row address generation module 304, read as second
Input out.Similar mode of operation can will read data and be written in new static memory, can also will read data and write
It returns in novel memory devices PUF array, is read again when comparison signal (COMP signal) is 1 as row address generation module
304 input；The result that the Mbit register counter module 11 reads first time saves in a register, and remembers
Corresponding number is recorded, using register result as the input of row address generation module when meeting counts；The Mbit deposit
Device counter module is also possible to certain some storage unit in the PUF storage array, by the content of every secondary deposit register
It is written in partial memory cell, is read again when needs.Alternatively, being that static memory SRAM replaces register.
(13) the multiple exclusive or module 310 is connected with Mbit register & counter module 311, reads for the second time
Cheng Zhong, output result will be stored in multiple exclusive or module 310, at this time can be by the multidigit result in multiple exclusive or module 310
Progress 2 times or more xor operations obtain an output, effectively improve the anti-modeling attacking ability of PUF.
The operating method of the present invention also provides the described strong PUF circuit based on memristor, is shown in Fig. 6, the specific steps are as follows:
Step 401: registration phase 1: enabling reset operation signal (RESET) is 1, is compared, reseting module 308 is started to work；Row ground
Location generation module 304 and column address generation module 303 sequentially generate address, make PUF column selector 302 and PUF line decoder 305
Each unit is chosen respectively, is compared, the offer reset signal of reseting module 308, is successively resetted all 2T2R units；
Step 402: registration phase 2: set operation signal (WRITE signal) is 1, is read, set module 301 provides twice of set
Signal, successively by each unit set at one high and one low form.(can also disposable set-reset multiple units)；
Step 403: reading for the first time: being arranged according to user input selection one, there is M unit, and be successively read according to input each
A resistance in 2T2R saves and reads data Mbit in 311；
Step 404: second of reading 1: inputting according to user, compares two column of the selection of electric current column selection module 307, often shows M
Unit reads input of the content as 304 modules according to step 403, while choosing a resistance in each 2T2R, compares two
The total current of column；
Step 405: second reads 2: in step 404, the mode of electric current is compared according to user input selection, i.e., according to
Family input can allow in a column any X resistance to be involved in total current to compare that (not make curent change excessive, X is usually no more than
M/4) total current is participated in compare；
Step 406: multidigit output being obtained according to clock, and multiple exclusive or obtains an output in 310 modules by output.
The advantage of circuit structure and operating process proposed by the invention is: strong PUF is improved under minimum area
Solution space, the operation repeatedly for realizing PUF storage array utilize, and complicated randomness can resist modeling attack well.
Detailed description of the invention
Fig. 1 is the strong PUF schematic block circuit diagram of CPU+FPGA in the prior art a kind of.
Fig. 2 is that one kind passes through RRAM array and COMS moderator strong PUF circuit in combination in the prior art.
Fig. 3 is a kind of 2T2R random number generator in the prior art.
Fig. 4 is a kind of PUF circuit exported by comparing column electric current in the prior art.
Fig. 5 is that the present invention is based on the structural schematic diagrams of the strong PUF circuit of memory device.
Fig. 6 is that the present invention is based on the operational flowcharts of the strong PUF circuit of memory device.
Fig. 7 is a kind of structural schematic diagram (embodiment) of the strong PUF circuit proposed by the present invention based on memory device.
Fig. 8 is a kind of operational flowchart (embodiment) of the strong PUF circuit proposed by the present invention based on memory device.
Fig. 9 is PUF line decoder proposed by the present invention (a kind of embodiment).
Specific embodiment
The detailed description of a step is done to a specific embodiment of the invention below with reference to embodiment and attached drawing, Fig. 7 is this hair
A kind of specific embodiment of bright proposition.This embodiment is served only for explaining the present invention, does not limit the present invention.In Fig. 7: including: base
Quasi- current module A01, column address generation module A02, PUF column selector A03, row address generation module A04, PUF line decoder
A05, row participate in modules A 0X, compare electric current column selection modules A 0Y, PUF storage array M row N column A06, comparison voltage module and
RESET voltage modules A 07, SA modules A 08, Mbit register & counter module A10, multiple exclusive or modules A 09.2T2R is basic
Unit T01 to T0B.Wherein:
(1) transistor T01, T03, T05, T0A bit line is LEFT in the first row, similar, and T02, T04, T06, T0B bit line are connected
For RIGHT.The bit line of each 2T2R unit is on-state in column decoder, such as: if column selector selects first row,
The bit line of transistor 401 and 402 is selected.When column decoder chooses a column, line decoder chooses the left and right wordline of a line
When, corresponding 2T2R unit is selected entirely；It is right when column decoder chooses a column, and line decoder chooses the left or right wordline of a line
Answer 2T2R unit part selected.Such as column1 chooses, when LEFT chooses, transistor T01 is selected, that is to say that 2T2R is mono-
First part is selected, and when LEFT and RIGHT chooses simultaneously, T01 and T02 transistor is selected simultaneously, that is to say first
2T2R unit is selected entirely.
(2) in PUF storage array, M row N column be using a 2T2R as basic unit for, actually PUF line decoder
The line that A03 is drawn has 2M root, and the lead of PUF column selector has 2N root.
(3) the row address generation module A04 can successively send address information and translate to PUF row when WRITE signal is 1
Code device A05, allows it successively to choose the 2T2R unit of 1,2 ... M rows entirely, that is to say that LEFT and RIGHT choose；
When READ signal is 1, row address generation module is according to input INPUT1 to the INPUTM of user successively by every a line
2T2R unit part is chosen.Such as INPUT1 is 0, INPUT2 when being 1, row address generation module successively allows line decoder to choose
The LEFT of a line 2T2R, the WL2_1 of the second row 2T2R.When COMP signal is 1, the row selection of PUF column decoder participates in 1 by row
Module participates in 4 modules to row and Mbit register & counter module codetermines.
(4) row participates in having X row to participate in module in modules A OX, the value of X being determined according to circuit designers needs,
Each row participates in module control unit branch.Row participate in module multirow 2T2R unit can choose by decoder can be by by them
It chooses, such as 2-4 decoder can choose the conducting of 3 rows, a line does not gate.It can also gate entirely.In the relatively electric current the step of,
Only row participation module in part is working every time, so the only last electric current of part row participation compares every time.Each row participates in mould
Block working condition difference can produce different responses.
(5) the participation module 1,2 and compare electric current column selection modules A 0Y and work together, select N arrange in two column as
Comparison array compares its two column size of current when COMP signal is 1.
(6) the Mbit register & counter module A10 saves the Mbit output read for the first time, when counter reaches M
It is secondary, Mbit is exported into the input as row address generation module A04.
(7) multiple exclusive or modules A 09 saves multidigit output, according to output bit number progress 2 times or more exclusive or, finally
Obtain 1bit output.
Below according to operational flowchart, i.e. Fig. 8, the operating condition of circuit: such as PUF is showed with a specific input
Array size is 16*8, and 4 rows participate in module and control 1-4 row, 5-8 row, 9-12 row, 13-16 row respectively.Input is 01
0000000000000011 00 11 inputs represent the input 01 of first time column address generation module A02, read number for the first time
According to when, PUF line decoder A05 input is 0000000000000011, and it is respectively 00 that lower 4 rows of default mode, which participate in module input,
00 00 00。
Step are as follows:
(1) write signal (WRITE signal) is 1, and reset signal 1, column address generation module A04 sequentially generates every column address, allows
PUF column selector A03 successively selects each column, while PUF line decoder A05 successively chooses every row, i.e. LEFT and RIGHT wordline entirely
It is selected, compare, the reset signal of one times of reseting module A07 offer, all units are reset to high resistant；
(2) write signal (WRITE signal) is 1, and set signal is 1, and column address generation module A02 sequentially generates every column address, allows
PUF column selector A03 successively selects each column, while line decoder successively chooses every row entirely, and reference current modules A 01 provides twice
Write current shunt more electric currents after a resistance is set to low-resistance, another resistance prevented to be set to low-resistance,
Form one high and one low form；
(3) read signal (READ signal) is 1, and column address generation module A02 is according to 0001 output address information of input, column selector
First row is selected, row address generation module sequentially turns on the first row to the 14th row RIGHT according to 0000000000000011 input
Wordline, the 15th, 16 row LEFT wordline of conducting (assuming that 1 is connected for left side wordline) sequential read out 16 outputs (assuming that high resistant is 1
Low-resistance is that 0), data are stored in Mbit register & counter module A10, it is assumed that deposit data are 1111111100000000；
(4) comparison signal (COMP signal) is 1, and participation module inputs 001 110 and allow respectively according to it compares electric current column selection mould
The 1st column of block A0Y conducting and 5 column generate mould as row address according to the data 1111111100000000 read in step 3
The first eight row LEFT wordline is connected for the input of block A04, rear eight rows RIGHT wordline conducting；
(5) row participates in modules A OX work, and 4 inputs are respectively 00 00 00 00, allows a row to participate in module every time and carries out work
Make, compares 1 to 4 rows for the first time, compare 5-8 row for the second time, compare 9-12 row, the 4th comparison 13-16 row, by four times for the third time
Comparison result is stored in multidigit output module；
(6) multiple exclusive or modules A 09 carries out exclusive or, 4 outputs twice and finally obtains an output response.
Possess a large amount of solution spaces based on strong PUF circuit proposed by the present invention.Assuming that a kind of row is only selected to participate in mode, then
For the array of MxN, solution space be can achieve.Assuming that M=16, N=8, row ginseng
There are 4 with module, then total solution space is equal to:
If it is the array (M > 63) of M*N, X row participates in module (X > 3), and it is 4-16 decoder that each row, which participates in module, total
Solution space can also reach:
。
Fig. 9 is a kind of structure for realizing the PUF line decoder A05 function: row address generation module is translated by a 3-8
Code device, can choose any a line in 8 rows, LEFT the and RIGHT word line switch of output end can be chosen with deciding section or
Choose, can also be chosen simultaneously all rows by decoder entirely, 4 rows participate in module can by 2-4 decoder and with door one
Work is played, forbids a line selected, this 4 row can also be allowed selected.A row can be allowed to participate in module work every time, obtained
One output operates 4 times and obtains 4 outputs, carries out exclusive or twice and finally obtains an output.
Claims (6)
1. a kind of strong PUF circuit based on memristor characterized by comprising 2T2R basic unit, the non-volatile storage battle array of PUF
Column are read and set module (301), PUF column selector (302), column address generation module (303), row address generation module
(304), address generation module (306) are compared in PUF line decoder (305), compare electric current column selection module (307), compare, is multiple
Position module (308), reading circuit module (309), multiple exclusive or module (310), Mbit register & counter module (311)；Its
In:
(1) the 2T2R basic unit (401 to 406 ..., 40A, 40B), the unit including two 1T1R, or including two
1D1R unit；Wherein R is memristor, is resistance-variable storing device, magnetic storage, ferroelectric memory or phase transition storage；T is crystal
Pipe, D is diode, which allows it to be in fully conducting state or portion by transistor wordline/diode level control
Divide on state, in the case where connecting voltage divider principle or parallel shunt principle, resistance value is in one high and one low state,
Or it is in the full low state of overall height；
(2) the non-volatile storage array of the PUF is made of M*N basic unit of storage, shares M row N column；Key is generated every time
Before, which is initialized, columns and rows is scanned respectively, successively control each storage unit, twice of set letter is provided
Number, by each storage unit set at the state of one low-resistance of a high resistant；With the storage unit in a line by two wordline controls
System, or controlled by a plurality of wordline；
(3) reading and set module (301) are respectively the non-volatile storage array of PUF and reference resistance during read operation
Array provides identical read signal；During set, double write signal is provided to corresponding storage unit, forms it into one
High one low distribution of resistance；
(4) the PUF line decoder (305) has following function: successively choosing every row entirely, that is, it is mono- to sequentially turn on every row 2T2R
All transistors of member；Every row is successively partially chosen, that is, sequentially turns on the function of one of R of each 2T2R unit of every row；Together
When the 2T2R unit part of all rows is chosen；Configurable modes, it can the random full conducting of selection or partially ON X row are not
Same mode；Multiple storage units are chosen simultaneously during set-reset, while carrying out write operation；
(5) the column address generation module (303), output are the input of PUF column selector (302), PUF column selector
(302) output signal controls PUF storage array；
(6) the row address generation module (304) is connected with PUF line decoder (305), row address generation module (304) it is defeated
Input as PUF line decoder (305) out, the output of PUF line decoder (305) is as the defeated of the non-volatile storage array of PUF
Enter；
The column address generation module (303) and row address generation module (304), when work, row address generation module/column address
Generation module is write, comparison signal generates row address/column address, and is transferred to corresponding according to clock, user's input, reading
PUF row/column decoder；
(7) the PUF column selector (302), has the function of successively choosing each column, also chooses PUF is non-to wave according to user's input
Send out a certain particular column in the N column of storage array；
(8) described to compare address generation module (306), for generating the ground of any two column in N column in the non-volatile storage array of PUF
Location is inputted as electric current column selection module (307) is compared；
(9) described to compare electric current column selection module (307), according to two column in the non-volatile storage array of user input selection PUF
Or multiple row, so that it is connected with reading circuit module, carries out size of current comparison；Or it is no more than reading circuit in curent change and size
Critical value under conditions of, select multiple row to carry out total current or all-in resistance and compare；
Compare address generation module (306) and compare electric current column selection module (307) co-operation, compares address generation module
(306) addresses for generating any two column in N column, as electric current column selection module (307) input is compared, PUF is non-volatile deposits for gating
Array two is stored up to arrange；
(10) comparison, reseting module (308), provide resetting voltage, read signal are provided in relatively size of current, in set
When, corresponding line is all grounded, set operation requirement is met；The comparison, reseting module (308) in read operation or are set
When bit manipulation, all SL from the non-volatile storage array of PUF are grounded, when comparison signal is 1, provide comparison voltage, when
When reset signal is 1, resetting voltage or electric current are provided and give PUF non-volatile storage array；
(11) the reading circuit module (309), multiple selector and spirit including RRAM referential array and reading circuit inside modules
Quick amplifier, reading circuit module (309) respectively with compare electric current column selection module (307), PUF column selector (302) and M
Bit register & counter module (311) is connected；In first time readout, the reference voltage of referential array and PUF column selection
The read voltage for selecting device (302) is compared to obtain response deposit Mbit register & counter module (311), executes the behaviour
Make M times, Mbit is responded into all deposits Mbit register & counter module (311)；When comparison signal is 1, i.e. second of reading
When out, the two column electric currents for comparing electric current column selection module (307) offer are compared, using comparison result as output, deposit
In the multidigit output module of the multiple exclusive or module (310)；Referential array module is series-parallel by multiple non-volatile memory resistors
It constitutes, function is the median of high low resistance when generating nonvolatile memory cell work, fights technological fluctuation；Sense amplifier root
It amplifies and compares according to two-way input signal, export and read result to multiple exclusive or module (310) or Mbit register & counter
Module (311)；
(12) the M bit register & counter module (311) is connected with row address generation module (304), M bit deposit
Register size in device counter module (311) is also M bit, when counter is calculated to M time, first time read operation completion；
Give the M bit data transmission in register to row address generation module (304), the input read as second；Similar behaviour
The mode of work can will read data and be written in new static memory, can also will read data and write back to novel memory devices PUF
In array, the input as row address generation module (304) is read again when comparison signal is 1；The Mbit register &
The result that counter module (11) reads first time saves in a register, and records corresponding number, meets counting time
Using register result as the input of row address generation module when number；The Mbit register counter module (11) can also be with
It is certain some storage unit in the PUF storage array, the content of every secondary deposit register is written to partial memory cell
In, it is read again when needs；
(13) the multiple exclusive or module (310) is connected with Mbit register & counter module (311), reads for the second time
Cheng Zhong, output result will be stored in multiple exclusive or module (310), at this point, by the multidigit result in multiple exclusive or module (310)
Progress 2 times or more xor operations obtain an output, effectively improve the anti-modeling attacking ability of PUF.
2. the strong PUF circuit according to claim 1 based on memristor, which is characterized in that the 2T2R is PUF resistive
Memory, phase transition storage, EEPEOM or Flash rely on the basic unit of floating gate charge storage；The unit is in parallel or string
Connection form, when being parallel form, the write current provided is by parallel shunt by resistance set at one high and one low state；For series connection
When form, what is provided writes voltage by series connection partial pressure, and resistance is reset to one high and one low state.
3. the strong PUF circuit according to claim 1 based on memristor, which is characterized in that every all left sides of row 2T2R unit
The wordline (LEFT, WL2_1, WL3_1, WLM_1) of side transistor is connected, the right transistor wordline (RIGHT, WL2_2, WL3_2,
WLM_2) all it is connected, when wordline is high level, represents selected；All 2T2R units of every row simultaneously choose its whole,
Or part choose, that is, simultaneously turn on the transistor on a line left side and the right, or only be connected a line in the left side transistor or
The transistor on the right；The left side wordline of a line 2T2R unit can be connected, the right wordline is connected or each transistor is single
Private decoder control method achievement unit sorting neutralizes chooses 2T2R unit entirely.
4. the strong PUF circuit according to claim 1 based on memristor, which is characterized in that the reading and set module
(301) in, according to it in read operation and set operation different conditions, different size of current or voltage is provided to PUF and stores battle array
Column；When input terminal set signal is 1, the reading, set module (301) output write-operation current from 0 to twice are gradually increased
Current signal, when input terminal read signal be 1 when, it is described read, set module (301) export respectively read signal give PUF storage battle array
Referential array in column and reading circuit module (309)；Different according to structure in 2T2R, the physical attribute of R is different, and set signal can
To be to write voltage to be also possible to write current, according to voltage divider principle or shunting principle, two resistance are due to own physical difference meeting
It is set to one high and one low mode；The reading, set module (301) also comprising feed circuit to close output signal in time.
5. the strong PUF circuit according to claim 1 based on memristor, which is characterized in that the reading circuit module (309)
In sense amplifier be voltage difference amplifier, that is, compare two input terminal voltages size or current-differencing amplification
Device compares the size of two electric currents.
6. a kind of operating method of the strong PUF circuit based on memristor as described in one of claim 1-5, which is characterized in that
Specific step is as follows:
Step 401: registration phase 1: enabling reset operation signal is 1, is compared, reseting module (308) is started to work；Row address is raw
Address is sequentially generated at module (304) and column address generation module (303), makes PUF column selector (302) and PUF line decoder
(305) each unit is chosen respectively, is compared, reseting module (308) offer reset signal, is successively resetted all 2T2R units；
Step 402: registration phase 2: set operation signal is 1, is read, set module (301) twice of set signal of offer, successively
By each unit set at one high and one low form；
Step 403: reading for the first time: being arranged according to user input selection one, there is M unit, and be successively read according to input each
A resistance in 2T2R saves and reads data Mbit in Mbit register & counter module (311)；
Step 404: second of reading 1: inputting according to user, compares two column of electric current column selection module (307) selection, often shows M
A unit reads input of the content as row address generation module (304) according to step 403, while choosing in each 2T2R
One resistance, compares the total current of two column；
Step 405: second reads 2: in step 404, the mode of electric current is compared according to user input selection, i.e., according to
Family input can allow in a column any X resistance to be involved in total current and compare participation total current to compare；
Step 406: multidigit output being obtained according to clock, and output multiple exclusive or in multiple exclusive or module (310) is obtained one
Position output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811289819.9A CN109495272B (en) | 2018-10-31 | 2018-10-31 | Strong PUF circuit based on memristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811289819.9A CN109495272B (en) | 2018-10-31 | 2018-10-31 | Strong PUF circuit based on memristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109495272A true CN109495272A (en) | 2019-03-19 |
| CN109495272B CN109495272B (en) | 2021-04-30 |
Family
ID=65693583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811289819.9A Active CN109495272B (en) | 2018-10-31 | 2018-10-31 | Strong PUF circuit based on memristor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109495272B (en) |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110473580A (en) * | 2019-08-21 | 2019-11-19 | 南京邮电大学 | A kind of programmable circuit minimum unit and its operating method based on memristor chip |
| CN110797063A (en) * | 2019-09-17 | 2020-02-14 | 华中科技大学 | Memristor memory chip and operation method thereof |
| CN111146236A (en) * | 2019-12-18 | 2020-05-12 | 上海集成电路研发中心有限公司 | Resistive random access memory unit and array structure |
| CN111339579A (en) * | 2020-03-26 | 2020-06-26 | 清华大学 | Electronic device and operation method thereof |
| CN111723408A (en) * | 2019-03-21 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Device for generating a PUF signature |
| CN111797438A (en) * | 2020-07-07 | 2020-10-20 | 清华大学 | Method and device for realizing physical unclonable function |
| CN112417523A (en) * | 2020-11-19 | 2021-02-26 | 深圳大学 | Physical unclonable function circuit structure based on silicide removal contact hole |
| CN112511308A (en) * | 2020-11-19 | 2021-03-16 | 深圳大学 | Physical unclonable function circuit structure based on grid overhang modulation |
| WO2021047527A1 (en) * | 2019-09-12 | 2021-03-18 | 杭州未名信科科技有限公司 | Circuit structure for puf, puf data obtaining method, and electronic device |
| CN112837737A (en) * | 2021-01-28 | 2021-05-25 | 翼盾(上海)智能科技有限公司 | PUF circuit having exponential growth type response number and encryption device |
| CN113096709A (en) * | 2021-03-12 | 2021-07-09 | 华中科技大学 | Physical unclonable function circuit and operation method thereof |
| WO2021239910A1 (en) * | 2020-05-29 | 2021-12-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Device and method for generating hardware-based physically non-clonable functions and use thereof |
| CN113783701A (en) * | 2021-09-18 | 2021-12-10 | 澳门大学 | Strong physical unclonable function structure |
| CN113823736A (en) * | 2021-08-25 | 2021-12-21 | 西安电子科技大学 | Volatile memristor type PUF (physical unclonable function) device, preparation method and device thereof and PUF encryption chip |
| WO2023082829A1 (en) * | 2021-11-15 | 2023-05-19 | International Business Machines Corporation | Physically unclonable function based on a phase change material array |
| CN116684105A (en) * | 2023-07-04 | 2023-09-01 | 湖北大学 | Memristor-based dual-mode PUF structure and working method thereof |
| TWI815554B (en) * | 2021-07-16 | 2023-09-11 | 台灣積體電路製造股份有限公司 | Semiconductor device and operation method of same |
| CN117010032A (en) * | 2023-10-07 | 2023-11-07 | 中国人民解放军国防科技大学 | SRAM physical unclonable function circuit capable of automatically reading and clearing and equipment |
| CN117157990A (en) * | 2021-04-12 | 2023-12-01 | 特忆智能科技 | Artificial intelligent pixel sensor based on memristor |
| CN117318955A (en) * | 2023-10-16 | 2023-12-29 | 苏州特思恩科技有限公司 | System and method for generating PUF |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023615A (en) * | 2015-07-16 | 2015-11-04 | 复旦大学 | Reading circuit of non-volatile memory capable of preventing side channel attack |
| CN105245220A (en) * | 2015-09-25 | 2016-01-13 | 深圳大学 | Physical unclonable chip circuit |
| CN105740731A (en) * | 2016-02-02 | 2016-07-06 | 中国科学院计算技术研究所 | High-stability strong physical unclonable function circuit and design method therefor |
| CN105760786A (en) * | 2016-02-06 | 2016-07-13 | 中国科学院计算技术研究所 | Strong PUF authentication method and system of CPU+FPGA integrated chip |
| US20180102163A1 (en) * | 2016-10-07 | 2018-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sram-based authentication circuit |
| CN108694335A (en) * | 2017-04-12 | 2018-10-23 | 恩智浦美国有限公司 | The method of physics unclonable function and generation PUF responses based on SRAM |
| CN108880818A (en) * | 2017-05-16 | 2018-11-23 | 三星电子株式会社 | The unclonable functional circuit of physics, system and integrated circuit with this function |
-
2018
- 2018-10-31 CN CN201811289819.9A patent/CN109495272B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023615A (en) * | 2015-07-16 | 2015-11-04 | 复旦大学 | Reading circuit of non-volatile memory capable of preventing side channel attack |
| CN105245220A (en) * | 2015-09-25 | 2016-01-13 | 深圳大学 | Physical unclonable chip circuit |
| CN105740731A (en) * | 2016-02-02 | 2016-07-06 | 中国科学院计算技术研究所 | High-stability strong physical unclonable function circuit and design method therefor |
| CN105760786A (en) * | 2016-02-06 | 2016-07-13 | 中国科学院计算技术研究所 | Strong PUF authentication method and system of CPU+FPGA integrated chip |
| US20180102163A1 (en) * | 2016-10-07 | 2018-04-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sram-based authentication circuit |
| CN108694335A (en) * | 2017-04-12 | 2018-10-23 | 恩智浦美国有限公司 | The method of physics unclonable function and generation PUF responses based on SRAM |
| CN108880818A (en) * | 2017-05-16 | 2018-11-23 | 三星电子株式会社 | The unclonable functional circuit of physics, system and integrated circuit with this function |
Non-Patent Citations (1)
| Title |
|---|
| REKHA GOVINDARAJ: "A strong arbiter PUF using resistive RAM with 1T-1R memory architecture", 《2016IEEE 34TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN》 * |
Cited By (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111723408A (en) * | 2019-03-21 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Device for generating a PUF signature |
| CN110473580A (en) * | 2019-08-21 | 2019-11-19 | 南京邮电大学 | A kind of programmable circuit minimum unit and its operating method based on memristor chip |
| CN110473580B (en) * | 2019-08-21 | 2021-08-20 | 南京邮电大学 | Programmable circuit minimum unit based on memristor chip and operation method thereof |
| WO2021047527A1 (en) * | 2019-09-12 | 2021-03-18 | 杭州未名信科科技有限公司 | Circuit structure for puf, puf data obtaining method, and electronic device |
| CN110797063A (en) * | 2019-09-17 | 2020-02-14 | 华中科技大学 | Memristor memory chip and operation method thereof |
| CN111146236B (en) * | 2019-12-18 | 2023-09-05 | 上海集成电路研发中心有限公司 | Resistive random access memory unit and array structure |
| CN111146236A (en) * | 2019-12-18 | 2020-05-12 | 上海集成电路研发中心有限公司 | Resistive random access memory unit and array structure |
| CN111339579A (en) * | 2020-03-26 | 2020-06-26 | 清华大学 | Electronic device and operation method thereof |
| WO2021239910A1 (en) * | 2020-05-29 | 2021-12-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Device and method for generating hardware-based physically non-clonable functions and use thereof |
| CN111797438A (en) * | 2020-07-07 | 2020-10-20 | 清华大学 | Method and device for realizing physical unclonable function |
| CN112417523B (en) * | 2020-11-19 | 2022-06-10 | 深圳大学 | Physical unclonable function circuit structure based on silicide removal contact hole |
| CN112417523A (en) * | 2020-11-19 | 2021-02-26 | 深圳大学 | Physical unclonable function circuit structure based on silicide removal contact hole |
| CN112511308A (en) * | 2020-11-19 | 2021-03-16 | 深圳大学 | Physical unclonable function circuit structure based on grid overhang modulation |
| CN112511308B (en) * | 2020-11-19 | 2022-12-16 | 深圳大学 | Physical unclonable function circuit structure based on grid overhang modulation |
| CN112837737B (en) * | 2021-01-28 | 2024-05-10 | 翼盾(上海)智能科技有限公司 | PUF circuit with exponentially increasing number of responses and encryption device |
| CN112837737A (en) * | 2021-01-28 | 2021-05-25 | 翼盾(上海)智能科技有限公司 | PUF circuit having exponential growth type response number and encryption device |
| CN113096709B (en) * | 2021-03-12 | 2022-03-29 | 华中科技大学 | Physical unclonable function circuit and operation method thereof |
| CN113096709A (en) * | 2021-03-12 | 2021-07-09 | 华中科技大学 | Physical unclonable function circuit and operation method thereof |
| CN117157990A (en) * | 2021-04-12 | 2023-12-01 | 特忆智能科技 | Artificial intelligent pixel sensor based on memristor |
| TWI815554B (en) * | 2021-07-16 | 2023-09-11 | 台灣積體電路製造股份有限公司 | Semiconductor device and operation method of same |
| US11967351B2 (en) | 2021-07-16 | 2024-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Physically unclonable function cell and operation method of same |
| CN113823736A (en) * | 2021-08-25 | 2021-12-21 | 西安电子科技大学 | Volatile memristor type PUF (physical unclonable function) device, preparation method and device thereof and PUF encryption chip |
| CN113783701A (en) * | 2021-09-18 | 2021-12-10 | 澳门大学 | Strong physical unclonable function structure |
| WO2023082829A1 (en) * | 2021-11-15 | 2023-05-19 | International Business Machines Corporation | Physically unclonable function based on a phase change material array |
| CN116684105A (en) * | 2023-07-04 | 2023-09-01 | 湖北大学 | Memristor-based dual-mode PUF structure and working method thereof |
| CN116684105B (en) * | 2023-07-04 | 2024-01-16 | 湖北大学 | Memristor-based dual-mode PUF structure and working method thereof |
| CN117010032A (en) * | 2023-10-07 | 2023-11-07 | 中国人民解放军国防科技大学 | SRAM physical unclonable function circuit capable of automatically reading and clearing and equipment |
| CN117010032B (en) * | 2023-10-07 | 2023-12-15 | 中国人民解放军国防科技大学 | SRAM physical unclonable function circuit capable of automatically reading and clearing and equipment |
| CN117318955A (en) * | 2023-10-16 | 2023-12-29 | 苏州特思恩科技有限公司 | System and method for generating PUF |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109495272B (en) | 2021-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109495272A (en) | A kind of strong PUF circuit based on memristor | |
| Cassuto et al. | Sneak-path constraints in memristor crossbar arrays | |
| CN105825885B (en) | Multilevel memory cell, read/write circuit and its operating method based on memristor | |
| CN113096709B (en) | Physical unclonable function circuit and operation method thereof | |
| CN110827898B (en) | Voltage-resistance type reversible logic circuit based on memristor and operation method thereof | |
| CN106796814A (en) | Storage circuit | |
| US11056161B2 (en) | Data processing system and method for generating a digital code with a physically unclonable function | |
| CN109817261B (en) | PUF circuit based on resistive random access memory and control method thereof | |
| US10880101B2 (en) | Method and circuit for de-biasing PUF bits | |
| CN113707201B (en) | Efficient reconfigurable ring oscillator PUF circuit based on RRAM | |
| Kumar et al. | A Novel RRAM-based FPGA architecture with Improved Performance and Optimization Parameters | |
| Madhavan et al. | High-throughput pattern matching with CMOL FPGA circuits: Case for logic-in-memory computing | |
| Cui et al. | Lightweight configurable ring oscillator PUF based on RRAM/CMOS hybrid circuits | |
| Fey et al. | Using memristor technology for multi-value registers in signed-digit arithmetic circuits | |
| Sun et al. | A hardware security architecture: PUFs (physical unclonable functions) using memristor | |
| Luo et al. | Nonvolatile Boolean logic in the one-transistor-one-memristor crossbar array for reconfigurable logic computing | |
| CN109067552A (en) | A kind of weak physics unclonable function circuit using NMOS process deviation | |
| CN105264775B (en) | Multidigit full adder and its operating method based on resistive device | |
| Nagarajan et al. | SHINE: A novel SHA-3 implementation using ReRAM-based in-memory computing | |
| Nemati et al. | A hybrid SRAM/RRAM in-memory computing architecture based on a reconfigurable SRAM sense amplifier | |
| CN106133838B (en) | A kind of expansible configurable FPGA storage organization and FPGA device | |
| CN115459923B (en) | Memristor-based ring oscillator PUF circuit and use method thereof | |
| CN110851882A (en) | Physical unclonable function generation method and system based on SOT effect | |
| CN103631732A (en) | Nonvolatile memory and electronic device | |
| US10192617B2 (en) | Circuit and array circuit for implementing shift operation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |