CN109495272B

CN109495272B - Strong PUF circuit based on memristor

Info

Publication number: CN109495272B
Application number: CN201811289819.9A
Authority: CN
Inventors: 解玉凤; 刘芯见; 孙超; 闫石林
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2018-10-31
Filing date: 2018-10-31
Publication date: 2021-04-30
Anticipated expiration: 2038-10-31
Also published as: CN109495272A

Abstract

The invention belongs to the technical field of information security, and particularly relates to a strong Physical Unclonable Function (PUF) circuit based on a memristor. The PUF circuit of the present invention includes: the nonvolatile memory array comprises a nonvolatile memory array and a 2T2R basic unit, a row address generating module, a column address generating module and a comparison address generating module which are used for generating row selection signals and column selection signals, a PUF column selector, a PUF row decoder and a comparison current column selecting module which are used for address decoding, a reading module, a setting module, a comparison module and a resetting module which are used for generating reading, writing and comparison signals, a reading circuit module used for a reading circuit, an Mbit register and counter module used for temporarily storing results, and a multiple exclusive OR module used for improving the resistance to modeling attack. The invention also provides a set of operation flow for improving the area utilization rate and the randomness of the strong PUF of the memristor. The memristor strong PUF circuit provided by the invention has the characteristics of high area utilization rate, configurability and reutilization, and has excellent randomness and modeling attack resistance.

Description

Strong PUF circuit based on memristor

Technical Field

The invention belongs to the technical field of information security, and particularly relates to a strong Physical Unclonable Function (PUF) circuit based on a memristor.

Background

With the rapid development of electronic technology and the rise of internet of things technology, people have to face a more and more serious problem, namely the safety certification and confidentiality of hardware, particularly in the private and military fields, while the lives of people are more and more independent of electronic products. Compared with the traditional password authentication mode, the Physical Unclonable Function (PUF) does not need to store passwords, but forms excitation and Response Pairs (CRPs) through physical characteristics such as fluctuation and difference of circuit devices in the manufacturing process, and each input, namely excitation (Challenge), outputs the Response (Response) according to the unique physical characteristic after passing through one PUF, so that the PUF has excellent safety and wide application prospect in the fields of digital authentication and confidentiality. According to the number of excitation response pairs, the excitation response pairs can be divided into weak PUFs and strong PUFs, the weak PUFs only have a small number of CRPs, the strong PUFs have sufficient CRPs, the CRPs are exponentially related to the circuit area of the strong PUFs, the strong PUFs have no limitation on CRPs, and manufacturers can select specific CRPs for subsequent application after hardware is manufactured. Strong PUFs are widely used in authentication circuits, compared to weak PUFs. Meanwhile, each CRP of the strong PUF can be used at one time due to the CRPs in exponential relation, so that the key is prevented from being cracked due to leakage of a small number of CRPs. The current strong PUF is mainly composed of CMOS circuits, for example, an arbiter PUF is a CMOS strong PUF, which generates random responses by comparing the delays of two sub-paths with similar structures, different stimuli determine that the components constituting the two sub-paths are different, but the type of PUF has poor security, and in order to improve the security and the response bit number, the arbiter PUF can be expanded to: a hybrid of SRAM and arbiter, a lightweight PUF, etc. Other kinds of CMOS strong PUFs include Ring oscillator PUFs, Bistable Ring (Bistable Ring) PUFs. However, the PUF circuit based on the CMOS often has the disadvantages of poor randomness, low area efficiency, incapability of resisting machine learning attacks, and the like.

The performance of PUF is often related to the selected entropy source, and when an external electric field or magnetic field strength reaches a certain threshold value, the resistance value of a device can be changed between high resistance and low resistance in a memory based on a novel memristor, such as a resistive random access memory, a magnetic memory, a ferroelectric memory, a phase change memory and the like. Due to the natural threshold randomness and the high-low resistance value dispersion, the novel memristor memory can be used as a good PUF entropy source. They have the characteristics of low operating voltage, simple structure, high storage density, low power consumption, high read-write speed and the like. Fabricating PUFs using a novel memristor storage device may not only improve the randomness of its entropy source but also improve security.

US8938069B2 proposes a strong PUF configuration based on transistor threshold voltage fluctuations, which obtains a one-bit output by comparing the magnitude of the output voltage produced by two circuits of the same configuration. The scheme has the defect that when a large number of CRPs are required to be obtained, a large number of CMOS (complementary metal oxide semiconductor) tubes are required to be connected in series, so that a high supply voltage is required, and the scheme cannot be realized in practical application.

Chinese patent CN105760786 proposes a strong PUF system of CPU + FPGA, which converts an excitation signal into configuration information and sends the configuration information to the CPU, then configures a physical unclonable function circuit on the FPGA in a partially reconfigurable manner, and finally returns a generated response to an authentication end to complete authentication, as shown in fig. 1. Although the scheme has high safety, the cost is high, the circuit is complex, and a certain gap is remained between the scheme and large-scale application.

The RekhaGovindaraj group proposed a circuit structure combining a Resistive Random Access Memory (RRAM) array and an Arbiter in an article (A Strong Arbiter PUF using Resistive RAM with 1T-1R Memory Architecture, 2016), and read out a response as an input of a CMOS Arbiter circuit according to a given RRAM array address to obtain a one-bit output, as shown in FIG. 2.

Daniel Arumi et al propose a Random number generator in the paper (RRAM Based Random Bit Generation for hard ware Security Applications), in the setting process, the transistors are in a semi-conducting state, when one of the parallel memristors is set to be low resistance first, the parallel total resistance is reduced, most of the voltage is reduced to two ends of the semi-conducting transistor according to the voltage division principle, the voltage at two ends of the memristor is reduced along with the reduction, the other memristor is prevented from being set to be low resistance immediately, the parallel unit forms a high-low resistance value, as shown in fig. 3, and finally, the resistance value of the left memristor is extracted as a Random number. However, the solution faces the following problems: more than two times of setting and resetting voltages of the memristor are needed, and the characteristic of low power consumption of the memristor cannot be met; moreover, the scheme belongs to random numbers and weak PUFs, a large number of CRPs cannot be formed, and the strong PUFs cannot be realized.

Elena IoanaVatajelu et al, in the STT-MRAM-Based Strong PUF Architecture, 2015 IEEE Computer Society Annual Symposium on VLSI, proposed to use random distribution of high resistance state resistance, by combining multiple columns of RRAM arrays, comparing the combined current with the total current of the reference array to output a one-bit response, and determining the combination of different columns by user input excitation, as shown in FIG. 4, the reference array and RRAM array have the same area, their column and row decoders are identical, the larger the comparison current is, the less fuzzy state can not be compared. If the number of columns is 2n total, this scheme can yield 2n power to CRP, but the disadvantage of this scheme is that: when the whole column selection and the single column selection are carried out, the selection size of the comparison current column is greatly changed, and the electric energy consumption is large when the whole column selection is carried out; meanwhile, the solution space cannot be effectively increased due to the large area of the scheme, double area is needed, and the area of the solution space is unacceptable in the application field requiring high-capacity CRPs. Meanwhile, the scheme does not provide any scheme for improving the modeling attack resistance of the artificial neural network, and the safety is insufficient under algorithm attacks such as deep neural network and ensemble learning.

Therefore, there is a need to provide a new strong PUF structure with features of high area efficiency and randomness, simple structure, and resistance to modeling attack.

Disclosure of Invention

The invention aims to provide a novel strong PUF (physical unclonable function) circuit based on a memristor, so that the circuit has the characteristics of high area efficiency, high randomness, exponential solution space and resistance to modeling attack, and is compatible with a logic process.

The structure diagram of the strong PUF circuit based on the memristor, which is provided by the invention, is shown in fig. 5, and comprises: 2T2R basic cell, PUF non-volatile memory array, read and set module 301, PUF column selector 302, column address generation module 303, row address generation module 304, PUF row decoder 305, comparison address generation module 306, comparison current column selection module 307, comparison and reset module 308, read circuit module 309, multiple exclusive-or module 310, Mbit register & counter module 311; wherein:

(1) the 2T2R basic cell (401 to 406, …, 40A, 40B), comprising two 1T1R cells, or comprising two 1D1R cells; wherein R is a memristor and is a resistive random access memory, a magnetic memory, a ferroelectric memory or a phase change memory; t is a transistor, D is a diode, the memory cell is in a full-conducting state or a partial-conducting state (conducting left or right resistors) through the level control of a transistor word line/diode, and under the condition of a series voltage division principle or a parallel shunt principle, the resistance value of the memory cell is in a high-low state or in a full-high-low state;

the 2T2R can be a basic unit of PUF resistance change memory, phase change memory, EEPEOM or Flash that relies on floating gate charge storage. The cells may be in parallel, with the write current provided to set the resistance to a high-low state by shunting in parallel. Or in series, the write voltage is provided to reset the resistor to a high-low state by dividing the voltage in series.

(2) The PUF nonvolatile storage array is composed of M × N basic storage units and has M rows and N columns in total; before generating a key each time, initializing the array, respectively scanning columns and rows, sequentially controlling each memory cell, providing a double setting signal, and setting each memory cell into a state of high resistance and low resistance; the memory cells in the same row are controlled by two word lines or by a plurality of word lines;

in each row 2T2R, word lines (LEFT, WL2_1, WL3_1, WLM _ 1) of all LEFT transistors of the cells are connected, word lines (RIGHT, WL2_2, WL3_2, WLM _ 2) of all RIGHT transistors are connected, and when the word lines (WL series) are high, the word lines represent selected (conducting), for example, when the RIGHT word lines are high, all RIGHT transistors of the first row are gated. All the 2T2R cells in each row may be selected all at once, or partially: i.e. to turn on both the left and right transistors of a row at the same time (all selected), or to turn on only the left transistor or the right transistor in a row (partially selected). The partially selected and fully selected 2T2R cells may be implemented by connecting the left word line and the right word line of a row of 2T2R cells, or by separately controlling each transistor by a decoder.

(3) The reading and setting module 301 provides the same reading signals for the PUF nonvolatile memory array and the reference resistor array during the reading operation; in the setting process, double write signals are provided for corresponding memory cells to form high-low resistance distribution;

specifically, different magnitudes of current or voltage are provided to the PUF memory array depending on the read operation and the set operation. When the set signal (WRITE signal) at the input terminal is 1, the READ/set module 301 outputs a current signal whose WRITE operation current gradually increases from 0 to twice, and when the READ signal (READ signal) at the input terminal is 1, the READ/set module 301 outputs a READ signal to the reference array in the PUF memory array and the READ circuit module 309, respectively. According to the structure difference in 2T2R, the physical property of R is different, the set signal can be a write voltage or a write current, and according to the voltage division principle or the shunt principle, the two resistors can be set to a high-low mode due to their own physical differences, for example, for RRAM, a 2T2R structure in series can be used, and twice the write set signal can be used, and for Magnetic Random Access Memory (MRAM), a 2T2R structure in parallel can be used, and twice the write current can be used. The read, set block 301 may include a feedback circuit to turn off the output signal in time.

(4) The PUF row decoder 305 has a function of sequentially and fully selecting each row, that is, sequentially turning on all transistors of the 2T2R cell in each row; PUF row decoder 305 also has the function of partially selecting each row in turn, i.e. turning on one of R of each 2T2R cell in turn in each row, e.g. the left transistor in each row can be turned on in turn; the PUF row decoder 305 also has the function of partially selecting all rows of 2T2R cells, for example, simultaneously selecting the left R of the top row 2T2R cell and the right R of the bottom row 2T2R cell; PUF row decoder 305 has the function of configurable patterns, i.e. different patterns that can randomly switch X rows fully on or partially on, for example, X rows can be arbitrarily selected for an M X N array, all of their left or right sides or all of the 2T2R cells are switched on, thus significantly expanding its solution space; the PUF row decoder 305 may also select a plurality of memory cells simultaneously during the set and reset processes, and perform write operations simultaneously, thereby improving efficiency.

(5) The output of the column address generation module 303 is input to the PUF column selector 302, and the PUF column selector 302 outputs a signal to control the PUF memory array.

(6) The row address generating module 304 is connected with the PUF row decoder 305, the output of the row address generating module 304 is used as the input of the PUF row decoder 305, and the output of the PUF row decoder 305 is used as the input of the PUF non-volatile memory array (30 MN);

when the column address generating module 303 and the row address generating module 304 are in operation, the row address generating module/the column address generating module generates a row address/a column address according to a clock, user input, reading, writing and comparison signals, and transmits the row address/the column address to the corresponding PUF row/column decoder.

(7) The PUF column selector 302 has a function of sequentially selecting each column, and selects a specific one of the N columns of the PUF nonvolatile memory array in accordance with a user input.

(8) The comparison address generating module 306 is configured to generate addresses of any two columns of the N columns in the PUF nonvolatile memory array, and the addresses are input to the comparison current column selecting module 307.

(9) The comparison current column selection module 307 selects two or more columns in the PUF nonvolatile memory array according to the input of the user, so that the two or more columns are connected with the reading circuit module to perform current magnitude comparison; or under the condition that the current change and the magnitude do not exceed the critical value of the reading circuit, selecting multiple columns (more than 2 columns) to compare the total current or the total resistance;

the comparison address generation module 306 and the comparison current column selection module 307 work together, and the comparison address generation module 306 can generate addresses of any two columns of the N columns as input of the comparison current column selection module 307 to gate two columns of the PUF non-volatile memory array (30 MN).

(10) The comparing and resetting module 308 provides a resetting voltage, provides a reading signal when comparing the current, and grounds all the corresponding connecting lines when setting to meet the setting operation requirement; the compare-RESET module 308 grounds all SLs from the PUF nonvolatile memory array (30 MN) during a read operation or a set operation, provides a comparison voltage when a comparison signal (COMP signal) is 1, and provides a RESET voltage or current to the PUF at 30MN when a RESET signal (RESET signal) is 1.

(11) The read circuit module 309 comprises an RRAM reference array, and a multiplexer and a sense amplifier inside the read circuit module, and the read circuit module 309 is respectively connected with the comparison current column selection module 307, the PUF column selection device 302, and the M-bit register & counter module 311; in the first reading process, the reference voltage of the reference array is compared with the reading voltage of the PUF column selector 302 to obtain a bit of response, the bit of response is stored in the Mbit register & counter module 311, the operation is performed for M times, and the Mbit response is completely stored in the Mbit register & counter module 311; when the comparison signal (COMP signal) is 1, i.e. the second reading, the two columns of currents provided by the comparison current column selection block 307 are compared, and the comparison result is stored as an output in the multi-bit output block of the xor block 310; the reference array module is formed by connecting a plurality of nonvolatile storage resistors in series and parallel, and has the function of generating a middle value of high and low resistance values when the nonvolatile storage units work to resist process fluctuation; the sense amplifier amplifies and compares the two paths of input signals, and outputs a reading result to the multiple exclusive-or module 310 or the Mbit register & counter module 311; the sense amplifier of the read circuit block 309 may be a differential voltage amplifier, i.e. comparing the voltages at the two input terminals, or a differential current amplifier, i.e. comparing the voltages of the two currents.

(12) The M-bit register & counter module 311 is connected to the row address generating module 304, and since there is an M-row 2T2R unit, the size of the register in the M-bit register & counter module 311 is also M bits, and when the counter counts M times, the first read operation is completed. The M bit data in the register is transferred to the row address generation block 304 as input for the second read. Similar operation can write the read data into the new static memory, or write the read data back into the PUF array of the new memory, and read it out as an input to the row address generation module 304 when the comparison signal (COMP signal) is 1; the Mbit register & counter module 11 stores the result read for the first time in a register, records the corresponding times, and takes the register result as the input of the row address generation module when the counting times are met; the Mbit register & counter module may also be some memory cells in the PUF memory array, and the contents to be stored in the register each time are written into some memory cells and read out when necessary. Alternatively, a static memory SRAM is used instead of the register.

(13) The multiple exclusive-or module 310 is connected with the Mbit register & counter module 311, and in the second reading process, the output result is stored in the multiple exclusive-or module 310, and at this time, the multi-bit result in the multiple exclusive-or module 310 can be subjected to exclusive-or operation for more than 2 times to obtain one-bit output, so that the modeling attack resistance of the PUF is effectively improved.

The invention also provides an operation method of the strong PUF circuit based on the memristor, which is shown in figure 6 and comprises the following specific steps:

step 401, registration phase 1: the RESET operation signal (RESET) is set to 1, and the comparing and resetting module 308 starts to work; the row address generation module 304 and the column address generation module 303 sequentially generate addresses, so that the PUF column selector 302 and the PUF row decoder 305 respectively select each cell, and the comparison and reset module 308 provides a reset signal to sequentially reset all the 2T2R cells;

step 402, registration phase 2: the set operation signal (WRITE signal) is 1, and the read/set block 301 provides twice the set signal, which in turn sets each cell to a high-low pattern. (multiple cells may also be set and reset at once);

step 403, first reading: selecting a column, having M cells, based on user input, and reading one resistor in each 2T2R in sequence based on the input, saving read data Mbit in 311;

step 404, reading 1 for the second time: according to the user input, the comparison current column selection module 307 selects two columns, each column has M units, reads the content as the input of the module 304 according to the step 403, selects one resistor in each 2T2R at the same time, and compares the total current of the two columns;

step 405, second read 2: in step 404, selecting a mode for comparing the currents according to the user input, that is, according to the user input, any X resistors in a column can participate in the total current comparison (in order to prevent the current from changing too much, X generally does not exceed M/4) to participate in the total current comparison;

at step 406, a multi-bit output is obtained according to the clock, and the output is multiply exclusive-ored in block 310 to obtain a single-bit output.

The advantages of the circuit structure and the operation flow provided by the invention are as follows: the solution space of the strong PUF is improved in a very small area, repeated operation and utilization of the PUF storage array are achieved, and the complex randomness of the PUF storage array can well resist modeling attack.

Drawings

Fig. 1 is a schematic block diagram of a strong PUF circuit of a CPU + FPGA in the prior art.

Fig. 2 shows a prior art strong PUF circuit with a RRAM array and a COMS arbiter combined.

Fig. 3 is a 2T2R random number generator in the prior art.

Figure 4 shows a prior art PUF circuit that obtains an output by comparing column currents.

Fig. 5 is a schematic diagram of a strong PUF circuit based on a memory device according to the present invention.

Figure 6 is a flow chart of the operation of the memory device based strong PUF circuit of the present invention.

Fig. 7 is a schematic structural diagram (an embodiment) of a strong PUF circuit based on a memory device according to the present invention.

Fig. 8 is a flow diagram (an embodiment) of the operation of a strong PUF circuit based on a memory device according to the present invention.

Fig. 9 shows a PUF row decoder according to an embodiment of the present invention.

Detailed Description

In the following, a detailed description of an embodiment of the present invention is given with reference to the following embodiments and the accompanying drawings, and fig. 7 shows an embodiment of the present invention. This example is intended to illustrate the invention and not to limit it. In fig. 7: the method comprises the following steps: a reference current module a01, a column address generation module a02, a PUF column selector a03, a row address generation module a04, a PUF row decoder a05, a row participation module A0X, a comparison current column selection module A0Y, a PUF memory array M row N column a06, a comparison voltage module and RESET voltage module a07, an SA module a08, an Mbit register & counter module a10, and a multiple exclusive or module a 09. 2T2R basic cells T01 to T0B. Wherein:

(1) the transistors T01, T03, T05, and T0A in the first row are LEFT, and similarly, the T02, T04, T06, and T0B bit lines are connected to RIGHT. The bit line of each 2T2R cell is on in the column decoder, for example: if the column selector selects the first column, the bit lines of

transistors

401 and 402 are both selected. When a column is selected by the column decoder and the left and right word lines of a row are selected by the row decoder, the corresponding 2T2R cell is fully selected; when a column is selected by the column decoder and a left or right wordline of a row is selected by the row decoder, the corresponding 2T2R cell portion is selected. For example, column1 is selected, when LEFT is selected, the transistor T01 is selected, namely 2T2R cell is partially selected, when LEFT and RIGHT are selected simultaneously, the transistor T01 and T02 are selected simultaneously, namely the first 2T2R cell is selected completely.

(2) In the PUF memory array, M rows and N columns are 2T2R as basic units, and actually, there are 2M lines from the PUF row decoder a03, and 2N leads from the PUF column selector.

(3) When the WRITE signal is 1, the row address generating module a04 sequentially sends address information to the PUF row decoder a05, so that the PUF row decoder sequentially selects the 2T2R units of 1 and 2 … M rows, that is, both LEFT and RIGHT are selected;

when the READ signal is 1, the row address generation module selects each row 2T2R cell portion in turn based on user INPUTs INPUT1 through INPUTM. For example, if INPUT1 is 0 and INPUT2 is 1, the row address generation module sequentially causes the row decoder to select LEFT in row 2T2R and WL2_1 in row 2T 2R. When the COMP signal is 1, the row selection of the PUF column decoder is jointly determined by the row participation 1 module to the row participation 4 module and the Mbit register & counter module.

(4) In the line participation module AOX, X line participation modules exist, the value of X is determined according to the needs of a circuit designer, and each line participation module controls partial lines. The row participation module may select rows of 2T2R cells by the decoder so that they may be selected, for example, 2-4 decoders may select 3 rows to be on and one row not to be on. Full gating is also possible. In the step of comparing the currents, only a portion of the rows participate in the operation of the module each time, so only a portion of the rows participate in the final current comparison each time. Different operating states of each row participating module may generate different responses.

(5) The participating

modules

1 and 2 and the comparison current column selecting module A0Y work together to select two columns of N columns as comparison columns, and when the COMP signal is 1, the currents of the two columns are compared.

(6) The Mbit register & counter block a10 holds the Mbit output read for the first time, and when the counter reaches M times, the Mbit output is used as the input to the row address generation block a 04.

(7) The multiple exclusive-or module a09 stores the multi-bit output, and performs exclusive-or for 2 times or more according to the number of output bits, and finally obtains 1-bit output.

The operation of the circuit is presented below with a specific input according to the operational flow diagram, i.e. fig. 8: for example, the PUF array size is 16 × 8, 4 rows participate in the module controlling 1-4 rows, 5-8 rows, 9-12 rows, and 13-16 rows, respectively. The input is 0100000000000000110011 the input represents the input 01 of the first column address generation module a02, the PUF row decoder a05 input is 0000000000000011 for the first read of data, and the 4 row participating module inputs are 00000000 in the default mode.

The method comprises the following steps:

(1) a WRITE signal (WRITE signal) is 1, a reset signal is 1, the column address generating module a04 sequentially generates each column address, the PUF column selector a03 sequentially selects each column, the PUF row decoder a05 sequentially and fully selects each row, namely, the LEFT word line and the RIGHT word line are both selected, and the comparing and resetting module a07 provides a one-time reset signal to reset all the cells to high impedance;

(2) the WRITE signal (WRITE signal) is 1, the set signal is 1, the column address generating module A02 sequentially generates each column address, the PUF column selector A03 sequentially selects each column, the row decoder sequentially and fully selects each row, the reference current module A01 provides twice WRITE current, and when one resistor is set to be low resistance, more current is shunted, and the other resistor is prevented from being set to be low resistance, so that a high-low mode is formed;

(3) the READ signal (READ signal) is 1, the column address generation module a02 outputs address information according to input 0001, the column selector selects the first column, the row address generation module sequentially turns on the RIGHT word lines from the first row to the 14 th row according to 0000000000000011 input, turns on the LEFT word lines from the 15 th row and the 16 th row (assuming that 1 is LEFT word line on), sequentially READs out 16-bit output (assuming that 1 is high resistance and 0 is low resistance), and stores data into the Mbit register & counter module a10, assuming that 1111111100000000 is stored;

(4) when the comparison signal (COMP signal) is 1, the participating module respectively turns on the 1 st column and the 5 th column of the comparison current column selection module A0Y according to the input 001110 of the participating module, and takes the comparison current column selection module A0Y as the input of the row address generation module a04 according to the data 1111111100000000 read out in step 3, turns on the LEFT word lines of the first eight rows and turns on the RIGHT word lines of the last eight rows;

(5) the line participation module AOX works, 4 inputs are 00000000 respectively, one line participation module works each time, lines 1 to 4 are compared for the first time, lines 5 to 8 are compared for the second time, lines 9 to 12 are compared for the third time, lines 13 to 16 are compared for the fourth time, and the result of the fourth comparison is stored in the multi-bit output module;

(6) the multiple exclusive-or module a09 performs exclusive-or twice, and 4 bits of output finally obtain a one-bit output response.

The strong PUF circuit provided based on the invention has a large solution space. Assuming that only one row participation mode is selected, the solution space is achievable for an MxN array

. Assuming M =16, N =8, and there are 4 line participation modules, then the total solution space is equal to:

in the case of an M X N array (M > 63), X number of row participation modules (X > 3), each of which is a 4-16 decoder, the total solution space can also be achieved:

。

fig. 9 is a structure for implementing the function of the PUF row decoder a 05: the row address generation module can select any one of 8 rows through a 3-8 decoder, the LEFT and RIGHT word line switches at the output end can determine partial selection or full selection, all the rows can be selected simultaneously through the decoder, and 4 row participation modules can work together through the 2-4 decoder and an AND gate to prohibit one row from being selected, and can also enable the 4 rows to be selected. One row can participate in the module work each time to obtain one-bit output, 4-bit output is obtained after 4 times of operation, and one-bit output is obtained after two times of XOR.

Claims

1. A strong PUF circuit based on a memristor, comprising: 2T2R basic unit, PUF non-volatile memory array, reading and setting module (301), PUF column selector (302), column address generating module (303), row address generating module (304), PUF row decoder (305), comparison address generating module (306), comparison current column selecting module (307), comparing and resetting module (308), reading circuit module (309), multiple exclusive-or module (310) and Mbit register & counter module (311); wherein:

(1) the 2T2R basic cell (401 to 406, …, 40A, 40B), comprising two 1T1R cells, or comprising two 1D1R cells; wherein R is a memristor and is a resistive random access memory, a magnetic memory, a ferroelectric memory or a phase change memory; t is a transistor, D is a diode, the memory cell is controlled to be in a full-conducting state or a partial-conducting state through the level of a transistor word line/diode, and under the condition of a series voltage division principle or a parallel shunt principle, the resistance value of the memory cell is in a high-low state or in a full-high-low state;

(3) the reading and setting module (301) is used for respectively providing the same reading signals for the PUF non-volatile storage array and the reference resistor array in the reading operation process; in the setting process, double write signals are provided for corresponding memory cells to form high-low resistance distribution;

(4) the PUF row decoder (305) has the following functions: all the transistors of each row are selected in sequence, namely all the transistors of the 2T2R cells of each row are turned on in sequence; partially selecting each row in turn, namely turning on the function of one R of each 2T2R unit in each row in turn; all rows of 2T2R cells are partially selected at the same time; the configurable mode is that different modes of randomly conducting all or partially conducting X rows can be selected; selecting a plurality of storage units simultaneously in the process of setting and resetting, and simultaneously performing write operation;

(5) the output of the column address generation module (303) is the input of a PUF column selector (302), and the PUF column selector (302) outputs a signal to control a PUF storage array;

(6) the row address generation module (304) is connected with the PUF row decoder (305), the output of the row address generation module (304) is used as the input of the PUF row decoder (305), and the output of the PUF row decoder (305) is used as the input of the PUF non-volatile storage array;

the column address generating module (303) and the row address generating module (304) are used for generating row addresses/column addresses according to a clock, user input, reading, writing and comparison signals and transmitting the row addresses/column addresses to corresponding PUF (physical unclonable function) row/column decoders when in work;

(7) the PUF column selector (302) has the function of sequentially selecting each column and selects a specific column in the N columns of the PUF nonvolatile memory array according to the input of a user;

(8) the comparison address generation module (306) is used for generating addresses of any two columns in the N columns in the PUF non-volatile memory array and used as the input of the comparison current column selection module (307);

(9) the comparison current column selection module (307) selects two or more columns in the PUF nonvolatile storage array according to the input of a user, so that the two or more columns are connected with the reading circuit module to perform current magnitude comparison; or under the condition that the current change and the magnitude do not exceed the critical value of the reading circuit, selecting multiple columns to compare the total current or the total resistance;

the comparison address generation module (306) and the comparison current column selection module (307) work together, the comparison address generation module (306) generates addresses of any two columns in the N columns, the addresses serve as the input of the comparison current column selection module (307), and two columns of the PUF nonvolatile storage array are gated;

(10) the comparison and reset module (308) provides reset voltage, provides a reading signal when comparing the current, and grounds all the corresponding connecting lines when setting to meet the setting operation requirement; the comparison and reset module (308) enables all SLs from the PUF nonvolatile memory array to be grounded in the read operation or the set operation, provides comparison voltage when the comparison signal is 1, and provides reset voltage or current to the PUF nonvolatile memory array when the reset signal is 1;

(11) the reading circuit module (309) comprises an RRAM reference array, a multiplexer and a sensitive amplifier which are arranged in the reading circuit module, and the reading circuit module (309) is respectively connected with the comparison current column selection module (307), the PUF column selection device (302) and the M bit register & counter module (311); in the first reading process, the reference voltage of the reference array is compared with the reading voltage of the PUF column selector (302) to obtain a bit response, the bit response is stored in an Mbit register & counter module (311), the operation is executed for M times, and the Mbit response is completely stored in the Mbit register & counter module (311); when the comparison signal is 1, namely the second reading, comparing the two columns of currents provided by the comparison current column selection module (307), and storing the comparison result as an output into a multi-bit output module of the multiple exclusive-or module (310); the reference array module is formed by connecting a plurality of nonvolatile storage resistors in series and parallel, and has the function of generating a middle value of high and low resistance values when the nonvolatile storage units work to resist process fluctuation; the sensitive amplifier amplifies and compares the two paths of input signals and outputs a reading result to the multiple exclusive-or module (310) or the Mbit register & counter module (311);

(12) the M-bit register & counter module (311) is connected with the row address generation module (304), the size of a register in the M-bit register & counter module (311) is also M bits, and when the counter counts M times, the first read operation is completed; transmitting the M bit data in the register to a row address generation module (304) as the input of the second reading; in a similar operation mode, read data can be written into a new static memory or written back into a PUF array of the novel memory, and read out as the input of a row address generation module (304) when a comparison signal is 1; the Mbit register & counter module (11) stores the result read for the first time in a register, records corresponding times, and takes the register result as the input of the row address generation module when the counting times are met; the Mbit register and counter module (11) can also be some storage units in the PUF storage array, and the content to be stored in the register each time is written into partial storage units and read out when needed;

(13) the multiple exclusive-or module (310) is connected with the Mbit register and counter module (311), in the second reading process, the output result is stored in the multiple exclusive-or module (310), at the moment, the multi-bit result in the multiple exclusive-or module (310) is subjected to exclusive-or operation for more than 2 times to obtain one-bit output, and the modeling attack resistance of the PUF is effectively improved.

2. The strong PUF circuit based on the memristor according to claim 1, wherein the 2T2R is a basic unit of PUF resistance change memory, phase change memory, EEPEOM or Flash that relies on floating gate charge storage; the unit is in a parallel or series connection mode, and when the unit is in the parallel connection mode, the provided write current sets the resistor to be in a high-low state through parallel shunt; in the series mode, the write voltage is provided to reset the resistor to a high-low state by series voltage division.

3. The memristor-based strong PUF circuit of claim 1, wherein the word lines (LEFT, WL2_1, WL3_1, WLM _ 1) of all LEFT transistors of each row of 2T2R cells are connected, the RIGHT transistor word lines (RIGHT, WL2_2, WL3_2, WLM _ 2) are all connected, and when a word line is high, it represents selected; all the 2T2R cells in each row are selected all at the same time, or partially, i.e., the transistors on the left and right of a row are turned on at the same time, or only the transistor on the left or right of a row is turned on; the left word line and the right word line of a row of 2T2R cells may be connected, or each transistor may be individually controlled by a decoder to achieve partially selected and fully selected 2T2R cells.

4. The memristor-based strong PUF circuit according to claim 1, wherein the read and set module (301) supplies currents or voltages of different magnitudes to the PUF memory array according to different states thereof in the read operation and the set operation; when the input end setting signal is 1, the reading and setting module (301) outputs a current signal with gradually increased current from 0 to twice the write operation current, and when the input end reading signal is 1, the reading and setting module (301) respectively outputs a reading signal to a PUF storage array and a reference array in the reading circuit module (309); according to the difference of structures and physical properties of R in 2T2R, a set signal can be write voltage or write current, and according to a voltage division principle or a shunt principle, two resistors can be set into a high-low mode due to self physical difference; the read and set module (301) also includes a feedback circuit to turn off the output signal in time.

5. A strong memristor-based PUF circuit according to claim 1, wherein a sense amplifier in the read circuit block (309) is a voltage differential amplifier, i.e. comparing the magnitude of two input terminal voltages, or a current differential amplifier, i.e. comparing the magnitude of two currents.

6. A method of operating a strong memristor-based PUF circuit according to any one of claims 1-5, comprising the following steps:

step 401, registration phase 1: the reset operation signal is enabled to be 1, and the comparison and reset module (308) starts to work; a row address generation module (304) and a column address generation module (303) sequentially generate addresses, each unit is selected by a PUF column selector (302) and a PUF row decoder (305), a comparison and reset module (308) provides a reset signal, and all 2T2R units are sequentially reset;

step 402, registration phase 2: setting the operation signal to be 1, providing two times of setting signals by the reading and setting module (301), and setting each unit to be in a high-low mode in sequence;

step 403, first reading: selecting a column of M cells based on user input, and reading one resistor in each 2T2R in sequence based on the input, storing the read data Mbit in an Mbit register & counter module (311);

step 404, reading 1 for the second time: according to the user input, a comparison current column selection module (307) selects two columns, each column has M units, the content is read out according to the step 403 to serve as the input of a row address generation module (304), one resistor in each 2T2R is selected at the same time, and the total current of the two columns is compared;

step 405, second read 2: in step 404, selecting a mode for comparing the currents according to the user input, that is, according to the user input, any X resistors in a column can participate in the total current comparison and participate in the total current comparison;

at step 406, a multi-bit output is obtained according to the clock and the output is multiply XOR'd in the multiply XOR module (310) to obtain a single-bit output.