CN105740731A - High-stability strong physical unclonable function circuit and design method therefor - Google Patents

Abstract

The invention is suitable for the fields of information security and integrated circuits, and provides a high-stability strong physical unclonable function circuit and a design method therefor. The physical unclonable function circuit comprises a time delay generation module, a time delay comparison module, a response calculation module and a stability judgment module, wherein the time delay generation module is used for transmitting the same jump through a plurality of time delay paths according to an input stimulus of the strong physical unclonable function circuit and generating a plurality of time delay values; the time delay comparison module is used for selecting out multiple pairs of time delay values from the time delay values, performing time delay difference comparison and dividing the time delay differences of the pairs of time delay values into a plurality of grades according to difference values; the response calculation unit is used for calculating an output response of the strong physical unclonable function circuit according to the time delay difference grade of each pair of time delay values; and the stability judgment module is used for judging whether a stimulus response pair is stable or not according to the time delay difference grade of each pair of time delay values. According to the circuit and the method, while the attack resistance of the strong physical unclonable function circuit is ensured, the time delay difference can be measured online in real time, so that the stability is greatly improved.

Description

The unclonable functional circuit of strong physics of a kind of high stability and method for designing thereof

Technical field

The present invention relates to information security field and integrated circuit fields, belong to a kind of hardware security method for designing, particularly relate to the unclonable functional circuit of strong physics and the method for designing thereof of a kind of high stability.

Background technology

In recent years, along with widely using of electronic equipment, safety and privacy become major issue.Be considered to permanently store and be not hacked the core that the key known to person is traditional cryptography, but, a lot of attack methods can breaking cryptographic keys, this allows for key and is not sufficient to ensure that safety.For efficiently solving safety problem, the unclonable functional circuit of physics (PhysicalUnclonableFunction, PUF) arises at the historic moment, and it is a kind of hardware component, can more effectively tackle safety problem.

When PUF utilizes chip manufacturing, inevitable process deviation produces specific inputoutput pair, also known as excitation response pair (Challenge-ResponsePair, CRP).Even same circuit design, process deviation in the fabrication process makes the PUF of different chip, in the face of identical input stimulus, it is possible to producing different output responses, namely CRP is different.Owing to process deviation itself is difficult to control to and predicts, therefore, these CRP can not be predicted before PUF manufactures, it is also difficult to is replicated after PUF manufactures.This, compared to traditional secrete key, has bigger advantage.This characteristic of PUF makes it be widely applied in security fields, such as intellectual property protection, qualification, certification, identification etc..

PUF is divided into two classes in a broad sense: weak PUF and strong PUF.Here the strong and weak safety height being not necessarily referring to them, but the quantity of CRP, their feature is as follows respectively.

Weak PUF only has minimal amount of CRP, next weak PUF only one of which CRP of most cases.Such as, dielectric particle layer PUF is a kind of weak PUF, and during fabrication, random spreads last layer dielectric particle, and owing to their distribution is difficult to predict, the capacitance size that therefore dielectric particle layer PUF determines according to the random dielectric particle layer covered produces response.And for example, static random access memory (StaticRandomAccessMemory, SRAM) PUF is another kind of weak PUF, impact by process deviation, each sram cell has different electrical characteristics, 0 or 1 can be stored at random and independently between the moment that chip powers on, different sram cells, and naturally form a CRP.Some other memory element such as flash memory, dynamic random access memory, memristor etc. equally also have similar characteristic, thus can be used to construct weak PUF.Owing to only can produce response when powering on based on the weak PUF of memory element, therefore safer compared to the key stored in the nonvolatile memory.

Compared with weak PUF, strong PUF then has a large amount of CRP.Arbitration PUF is a kind of typical strong PUF, it propagates the time delay of saltus step and determines response by comparing two paths, every paths is made up of multiple subpaths, the selection of subpath is determined by excitation, two paths of different excitation structures differ, and their time delay size is also not quite similar, thus creating random response.Arbitration PUF is subject to the serious threat that modeling is attacked, and in order to improve the safety of arbitration PUF, feedforward arbitration PUF, XOR arbitration PUF, the light weight arbitration modified model such as PUF, current mirror PUF arbitration PUF are suggested.Feedforward arbitration PUF instructs the selection of subpath in residual paths by the time delay size in rating unit path；The responses of multiple arbitration PUF are carried out XOR as final response by XOR arbitration PUF；Light weight arbitration PUF still uses XOR gate that the responses of multiple arbitration PUF are carried out XOR calculating, but disposable obtains multiple Response field bit；Current mirror PUF then introduces electric current and replaces time delay to compare.Arbitrating in PUF at these modified models, the XOR arbitration PUF based on a plurality of latency path is considered to have best anti-modeling aggressivity, and especially with increasing of latency path number, its anti-modeling aggressivity is also powerful all the more.

Although the XOR arbitration PUF based on a plurality of latency path can be effective against modeling attack when latency path number is bigger, however as the increase of latency path number, its stability rapid decrease, seriously limit the application of XOR arbitration PUF.

The response of multiple arbitration PUF is carried out XOR as final response by XOR arbitration PUF, and therefore, when odd number arbitrates the response instability of PUF, the response of XOR arbitration PUF will be unstable.Assuming that XOR arbitration PUF contains m arbitration PUF, i.e. 2m bar latency path and the stability of each arbitration PUF altogether, namely responding the probability that will not change is P_SB, then constant probability P is stablized in the response of XOR arbitration PUF_SXTheory is:

$P_{SX}=1-\underset{k=1}{\overset{m}{\mathrm{\Σ}}}\left(\left\{\begin{array}{cc}kisodd:& C_m^k\×{(1-P_{SB})}^k\×P_{SB}^{m-k}\\ kisodd:& 0\end{array}\right.\right)$

Wherein, k indicates that instability occurs in the response of how many arbitration PUF, and k calculates m from 1.If k is even number, then the response of XOR arbitration PUF is maintained to stable；If k position odd number, then in XOR arbitration PUF, the combination of k arbitration PUF response instability hasKind, for each combination, its probability of happening isTable 1 gives at different P_SBUnder value, the stability of XOR arbitration PUF is with the theoretical variation tendency of arbitration PUF number.The stability of arbitration PUF is typically in about 95%, it can be seen that when arbitrating PUF number and reaching 20, and the stability of XOR arbitration PUF only remains 56%.

The stability of table 1 XOR arbitration PUF

Arbitration PUF number	PSB=95%	PSB=96%	PSB=97%
				10	67.43%	71.72%	76.93%
11	65.69%	69.98%	75.32%
				12	64.12%	68.38%	73.80%
13	62.71%	66.91%	72.37%
				14	61.44%	65.56%	71.03%
15	60.30%	64.32%	69.77%
				16	59.27%	63.17%	68.58%
17	58.34%	62.12%	67.46%
				18	57.51%	61.15%	66.42%
19	56.75%	60.26%	65.43%
				20	56.08%	59.44%	64.51%

The reason that arbitration PUF response is unstable, when the strong PUF carrying out high stability studies, is conducted in-depth analysis, it was found that cause two key factors of instability by inventor:

(1) time delay value is the value of distribution in real number field, and PUF response is the two-valued function of 0 or 1, therefore delay inequality being converted in the process of two-valued function, inevitably there is information loss, this information loss is one of major reason causing response instability.

(2) when the time delay value of two latency path closely time, just there will be the phenomenon that response is unstable, this is due to when delay inequality is very little, when the change of working environment such as supply voltage, temperature is easy to cause delay inequality and be just, time be negative, and then when making response and be 0, time be 1.

Inventor is through the further investigation to above-mentioned two reason, it is proposed that overcome brand-new strong PUF structure and the method for designing of the two factor.For first reason, the delay inequality of latency path is mapped to many (more than 2) value logic by real number field, to reduce information loss.For Second Problem, according to time delay extent, give corresponding weight, and then produce more stable response by the voting machine of Weight.

In summary, prior art there will naturally be inconvenience and defect in actual use, it is therefore necessary to improved.

Summary of the invention

For above-mentioned defect, it is an object of the invention to provide the unclonable function of strong physics of a kind of high stability and method for designing thereof, its ensure the unclonable functional circuit attack tolerant of strong physics meanwhile, it is capable to real-time online measuring delay inequality, and then improve stability.

To achieve these goals, the present invention provides the unclonable functional circuit of strong physics of a kind of high stability, including:

Time delay generation module, for the input stimulus according to the unclonable functional circuit of strong physics, is propagated same saltus step by a plurality of latency path, produces multiple time delay value simultaneously；

Time delay comparison module, carries out delay inequality compare for selecting multipair time delay value from the plurality of time delay value, and the delay inequality of each pair of time delay value is divided into multiple grade by size；

RESPONSE CALCULATION module, for the delay inequality grade according to described each pair of time delay value, calculates the output response of the unclonable functional circuit of strong physics；

Stabilizing determination module, for the delay inequality grade according to described each pair of time delay value, it determines whether excitation response pair is stable.

The unclonable functional circuit of strong physics according to the present invention, described time delay generation module includes excitation mapping submodule and multiple latency path submodule, described excitation mapping submodule, for described input stimulus being mapped to each described latency path submodule, determine the composition of time delay subpath in latency path；Described latency path submodule, is used for producing at least one time delay value.

The unclonable functional circuit of strong physics according to the present invention, a plurality of latency path propagating saltus step is independent of one another or interactively with each other, and every latency path all has identical time delay nominal value.

The unclonable functional circuit of strong physics according to the present invention, described input stimulus directly drives each bar latency path or by remapping each bar latency path of driving.

The unclonable functional circuit of strong physics according to the present invention, time delay comparison module includes: time delay value pairing submodule, for the multiple time delay values produced by described time delay generation module, being combined into multiple time delay pair, each time delay value at least occurs once in the plurality of time delay centering；Delay inequality grade classification submodule, for comparing the delay inequality of each time delay pair, and carries out grade classification by delay inequality with default time delay reference value, and each grade represents a time delay interval.

The unclonable functional circuit of strong physics according to the present invention, the delay inequality of each time delay pair described is carried out grade classification by the mode of mould revolution by described delay inequality grade classification submodule.

The unclonable functional circuit of strong physics according to the present invention, RESPONSE CALCULATION module includes: time delay is to delay inequality grade weight calculation submodule, for the corresponding weighted value of delay inequality rating calculation according to each time delay pair described；Weight is added and submodule by time delay, for by all time delays to being divided into delay inequality two classes minus more than zero-sum delay inequality, and calculate respectively two class time delays pair weight and；Weight and comparison sub-module, for relatively described two class time delays pair weight and, and according to comparative result output response.

The unclonable functional circuit of strong physics according to the present invention, the final response of the unclonable functional circuit of physics is produced by the voting machine of Weight.

The unclonable functional circuit of strong physics according to the present invention, described stabilizing determination module according to the weight of described two class time delays pair and, it determines the probability of stability of an excitation response pair.

The present invention provides the method for designing of the unclonable functional circuit of strong physics of a kind of high stability accordingly, including:

Input stimulus according to the unclonable functional circuit of strong physics, is propagated same saltus step by a plurality of latency path, produces multiple time delay value simultaneously；

From the plurality of time delay value, select multipair time delay value carry out delay inequality and compare, and the delay inequality of each pair of time delay value is divided into multiple grade by size；

Delay inequality grade according to described each pair of time delay value, calculates the output response of the unclonable functional circuit of strong physics；

Delay inequality grade according to described each pair of time delay value, it determines whether excitation response pair is stable.

The time delay value that a plurality of latency path produces is selected multipair time delay value by the present invention, the delay inequality of each time delay pair is divided into multiple time delay grade, delay inequality grade according to each pair of time delay value calculates the output response of the unclonable functional circuit of strong physics, also it is mapped to multi valued logic by delay inequality from real number field, utilizes more information to produce stable response.A plurality of latency path is less on the impact of CRP stability, both ensure that and safety in turn ensure that stability.Thus, the present invention ensure the unclonable functional circuit attack tolerant of strong physics meanwhile, it is capable to real-time online measuring delay inequality, and then increase substantially stability.

Preferably, the present invention gives corresponding weight according to the delay inequality grade of each time delay pair, and by all time delays to being divided into delay inequality two classes minus more than zero-sum delay inequality, by belonging to all kinds of time delays, weight is summed up respectively, relatively two class time delays pair weight and, and according to comparative result output response.Thus the present invention produces more stable response by the voting machine of Weight, the overall stability of CRP can not only be improved, the selection to stable CRP can also be instructed to use in the application, make while improving the unclonable functional circuit CRP general stability of physics, also ensure that application process occurring, the situation of instability is less.

Accompanying drawing explanation

Fig. 1 is the theory diagram of the unclonable functional circuit of strong physics of a kind of high stability of the present invention；

Fig. 2 is the schematic diagram of time delay generation module in an embodiment of the present invention；

Fig. 3 is the schematic diagram of time delay comparison module in an embodiment of the present invention；

Fig. 4 is the schematic diagram of RESPONSE CALCULATION module and stabilizing determination module in an embodiment of the present invention；

Fig. 5 is the stability assessment result schematic diagram of the present invention and XOR arbitration PUF under the number of different delay path；

Fig. 6 is the stable CRP number proportion schematic diagram of the present invention and XOR arbitration PUF under the number of different delay path；

Fig. 7 is the randomness schematic diagram of the present invention and XOR arbitration PUF under the number of different delay path；

Fig. 8 is the flow chart of the method for designing of the unclonable functional circuit of strong physics of a kind of high stability of the present invention.

Detailed description of the invention

In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.

The invention provides the unclonable functional circuit of strong physics of a kind of high stability and method for designing thereof, it is therefore an objective to improve the unclonable functional circuit CRP general stability of physics.The technical solution adopted in the present invention is: the input stimulus according to the unclonable functional circuit of strong physics, same saltus step is propagated by a plurality of latency path, produces multiple time delay value simultaneously；From multiple time delay values, select multipair time delay value carry out delay inequality and compare, and the delay inequality of each pair of time delay value is divided into multiple grade by size；Delay inequality grade according to each pair of time delay value, calculates the output response of the unclonable functional circuit of strong physics, and differentiates that whether excitation response pair is stable.The present invention is by being carried out mapping (being also divided into multiple grade by delay inequality) to multi valued logic by real number field by the delay inequality of latency path, to reduce information loss；And according to time delay extent, give corresponding weight, and then produce more stable response by the voting machine of Weight, to solve prior art causes the problem that arbitration PUF response is unstable, thus improving the unclonable functional circuit CRP general stability of physics.

As it is shown in figure 1, the present invention provides the unclonable functional circuit of strong physics of a kind of high stability, including time delay generation module 10, time delay comparison module 20, RESPONSE CALCULATION module 30 and stabilizing determination module 40.

Time delay generation module 10, for the input stimulus according to the unclonable functional circuit of strong physics, is propagated same saltus step by a plurality of latency path, produces multiple time delay value simultaneously.

Time delay generation module 10 includes excitation mapping submodule 11 and multiple latency path submodule 12.Excitation mapping submodule 11, for input stimulus is mapped to each latency path submodule 12, determines the composition of time delay subpath in latency path, and the subpath in different delay path is constituted can be identical or different.Latency path submodule 12, is used for producing at least one time delay value.One latency path is made up of several time delay subpaths, and which time delay subpath constitutes latency path and determined by input stimulus.The a plurality of latency path propagating saltus step is independent of one another or interactively with each other, and every latency path all has identical time delay nominal value.Input stimulus directly drives each bar latency path or by remapping each bar latency path of driving.Thus, for the calculating finally responded, time delay generation module 10 ensures that safety is unaffected by producing multiple time delay value.

The input stimulus of whole strong PUF, after blasting mapping submodule, arrives multiple latency path submodule.For different latency path submodules, the excitation after mapping both can be identical, it is also possible to different, what the subpath being all used for determining to form latency path in latency path submodule is.Wherein, a saltus step is propagated to output from the input of all latency path, is a time delay value by the propagation time of each latency path.

Time delay comparison module 20, carries out delay inequality compare for selecting multipair time delay value from multiple time delay values, and the delay inequality of each pair of time delay value is divided into multiple grade by size.Time delay comparison module 20 includes time delay value pairing submodule 21 and delay inequality grade classification submodule 22.Concrete, that time delay comparison module 20 produces according to time delay generation module 10 multiple time delay values, time delay value matches submodule 21 and is combined into multiple time delay pair, and these time delays are to covering all time delay values.Then, the delay inequality of each time delay pair being carried out multi valued logic mapping, convert different delay inequality grades to, each delay inequality grade represents the interval of a delay inequality, and interval size is adjustable when design.Delay inequality is mapped as 01 two-valued function from real number field by prior art, loses relatively multi information, and delay inequality is mapped as many (more than 2) value logic from real number field by the present invention, utilizes more information to improve the stability of response.

Time delay value pairing submodule 21, for the multiple time delay values produced by time delay generation module 10, is combined into multiple time delay pair, and each time delay value at least occurs once in multiple time delay centerings.

Delay inequality grade classification submodule 22, for comparing the delay inequality of each time delay pair, and carries out grade classification by delay inequality with default time delay reference value, and each grade represents a time delay interval.Such as: mark off 2n grade altogether, the time delay interval that then each grade represents is: (-∞,-(n-1) × Δ d), (-(n-1) × Δ d,-(n-2) × Δ d) ... (-2 Δ d ,-Δ d), (-Δ d, 0), (0, Δ d), (Δ d, 2 Δ d) ... ((n-2) × Δ d, (n-1) × Δ d), ((n-1) × Δ d, ∞).Further, interval for each time delay, time delay reference value Δ d can be identical or different.Preferably, the delay inequality of each time delay pair is carried out grade classification by the mode of mould revolution by delay inequality grade classification submodule 22.

RESPONSE CALCULATION module 30, the delay inequality grade of each pair of time delay value for dividing according to time delay comparison module 20, calculate the output response of the unclonable functional circuit of strong physics.Concrete, the delay inequality grade of each time delay pair that RESPONSE CALCULATION module 30 obtains according to time delay comparison module 20, for each time delay to giving corresponding weight, quantitatively represent degree of stability, then by all time delays to being divided into two classes that delay inequality is more than 0 and delay inequality is less than 0, and calculate this two classes time delay pair weight and, compare the size of the weight sum of two class time delays pair, the strong PUF being mapped as two-valued function finally responds, and namely 0 or 1.That is, the final response of the unclonable functional circuit of physics is produced by the voting machine of Weight.Time delay is directly related with stability to time delay extent, and delay inequality is more big, and stability is more high, the present invention according to delay inequality size introduce weight and so that finally compare the response drawn more stable.

RESPONSE CALCULATION module 30 includes: weight is added and submodule 32 and weight and comparison sub-module 33 by time delay by delay inequality grade weight calculation submodule 31, time delay.Time delay is to delay inequality grade weight calculation submodule 31, for the corresponding weighted value of delay inequality rating calculation according to each time delay pair.The grade that delay inequality is bigger should be less than delay inequality grade there is identical or bigger weight.Weight is added and submodule 32 by time delay, for by all time delays to being divided into delay inequality two classes minus more than zero-sum delay inequality, calculate respectively two class time delays pair weight and.Weight and comparison sub-module 33, for compare two class time delays pair weight and, and according to comparative result output response.

Stabilizing determination module 40, for the delay inequality grade according to each pair of time delay value, it determines whether excitation response pair is stable.The weight of the two class time delays pair that weight is added by stabilizing determination module 40 according to time delay and submodule 32 produces and, it determines the probability of stability of an excitation response pair.Concrete, weight is added and submodule 32 by time delay described in stabilizing determination module 40 reusable by delay inequality grade weight calculation submodule 31 and time delay, to reduce hardware spending: if the weight of the first kind time delay pair that delay inequality is more than zero and with the weight of the minus Equations of The Second Kind time delay pair of delay inequality and difference exceed specific threshold, then it is assumed that corresponding response is stable response；Also dependent on first kind time delay pair weight and with the weight of Equations of The Second Kind time delay pair and difference CRP is ranked up, difference is more big, before sequence more.When PUF design realizes, select suitable strategy according to hardware constraints, then in PUF application process, only use and there is stable response or forward excitation of sorting to be further ensured that stability.The present invention is by selecting the CRP that the degree of stability that obtains from probability is high, for practical application so that while improving the unclonable functional circuit CRP general stability of physics, also ensure that seldom occur unstable situation in application process.

Fig. 2 is the schematic diagram of time delay generation module in an embodiment of the present invention.Fig. 2 is for two latency path submodules, and one of them latency path submodule is that single-hop change input single-hop becomes output, for each excitation one latency path of structure, produces a time delay value, and this latency path is separate with other latency path；Another one latency path submodule is that four saltus steps input four saltus step outputs, builds four latency path for each excitation, produces four time delay values, and these four latency path are interactively with each other.Excitation mapping submodule is by n-bit C₁～C_nExcitation input to the two latency path submodule, but for the latency path submodule of single-input single-output, C₁Near saltus step input, and C_nNear saltus step output, and for the latency path submodule that four input four outputs, C₁Near saltus step output, and C_nNear saltus step input.

In fig. 2, for the latency path submodule of single-input single-output, latency path includes n time delay subpath altogether, and each subpath is made up of two buffers and No. two selectores.For i-th time delay subpath, work as C_iWhen being 0, saltus step is through A_iAnd M_iBack-propagation；Work as C_iWhen being 1, saltus step is through B_iAnd M_iBack-propagation.For different excitations, the latency path of composition also differs, and corresponding time delay value naturally also differs.

In fig. 2, for the four latency path submodules inputting four outputs, four latency path include n/2 time delay subpath altogether, and each subpath is made up of eight No. two selectores.For by C_nAnd C_n-1The 1st the time delay subpath controlled, works as C_nWhen being 0, saltus step input 1 is through P₁Back-propagation, saltus step input 2 are through Q₁Back-propagation, saltus step input 3 are through R₁Back-propagation, saltus step input 4 are through S₁Back-propagation；Work as C_nWhen being 1, saltus step input 1 is through R₁Back-propagation, saltus step input 2 are through S₁Back-propagation, saltus step input 3 are through P₁Back-propagation, saltus step input 4 are through Q₁Back-propagation；Work as C_n-1When being 0, P₁The saltus step propagated is through P₂Back-propagation, Q₁The saltus step propagated is through Q₂Back-propagation, R₁The saltus step propagated is through R₂Back-propagation, S₁The saltus step propagated is through S₂Back-propagation；Work as C_n-1When being 1, P₁The saltus step propagated is through Q₂Back-propagation, Q₁The saltus step propagated is through P₂Back-propagation, R₁The saltus step propagated is through S₂Back-propagation, S₁The saltus step propagated is through R₂Back-propagation.For different excitations, four latency path of composition also differ, and corresponding time delay value naturally also differs.

Further, in order to ensure the safety of strong PUF, in addition it is also necessary to more latency path submodule produces more latency path and more time delay value.

Fig. 3 is the schematic diagram of time delay comparison module in an embodiment of the present invention.A total k saltus step output in Fig. 3, they are partnered by time delay value pairing submodule between two, and time delay is inputed to k/2 delay inequality grade classification submodule by total k/2.When actual design, a saltus step output can also simultaneously appear in multiple time delay centering.

With p₀And p₁The delay inequality grade classification submodule of input is example, first, and p₀And p₁It is separately input to trigger F_AD end and CLK end, if transmission is saltus step on, and p₀Compare p₁First arrive F_A, i.e. p₁Time delay compare p₀Long, then F_AQ output 1, if otherwise p₀Time delay compare p₁Long, then F_AQ output 0.For convenience, p below₀And p₁Both represented the title of line, and be also used for representing its time delay.Then, p₀P is become through the buffer that time delay is Δ d₀'=p₀+ Δ d, p₀' become p then through the buffer that time delay is Δ d₀"=p₀'+Δ d=p₀+ 2 Δ d, p₀" become p then through the buffer that time delay is Δ d₀" '=p₀"+Δ d=p₀+ 3 Δ d, p₀' and p₁Input to trigger F₁₁Produce d₁₁, p₀" and p₁Input to trigger F₁₂Produce d₁₂, p₀" ' and p₁Input to trigger F₁₃Produce d₁₃, d₁₁,d₁₂,d₁₃Characterize p₁>p₀Time delay inequality divided rank；In like manner, p₁P is become through the buffer that time delay is Δ d₁'=p₁+ Δ d, p₁' become p then through the buffer that time delay is Δ d₁"=p₁'+Δ d=p₁+ 2 Δ d, p₁" become p then through the buffer that time delay is Δ d₁" '=p₁"+Δ d=p₁+ 3 Δ d, p₁' and p₀Input to trigger F₀₁Produce d₀₁, p₁" and p₀Input to trigger F₀₂Produce d₀₂, p₁" ' and p₀Input to trigger F₀₃Produce d₀₃, d₀₁,d₀₂,d₀₃Characterize p₀>p₁Time delay inequality divided rank.

With p₀-p₁> 0 situation be example illustrate delay inequality grade partition process.In Fig. 3 shown in (2), if 0 < p₀-p₁< Δ d, then d₀₁d₀₂d₀₃=111；Otherwise, in Fig. 3 shown in (3), if Δ d < p₀-p₁< 2 Δ d, then d₀₁d₀₂d₀₃=011；Otherwise, in Fig. 3 shown in (4), if 2 Δ d < p₀-p₁< 3 Δ d, then d₀₁d₀₂d₀₃=001；Otherwise, in Fig. 3 shown in (5), if 3 Δ d < p₀-p₁, then d₀₁d₀₂d₀₃=000.As can be seen here, this delay inequality grade classification submodule is by p₀-p₁> 0 situation be divided into 4 intervals: [0, Δ d], [Δ d, 2 Δ d], [2 Δ d, 3 Δ d], [3 Δ d, ∞], use rd respectively₀₁d₀₂d₀₃=0111,0011,0001,0000 represents.In like manner, for p₀-p₁< situation of 0, has been also divided into 4 intervals: [-Δ d, 0], [-2 Δ d ,-Δ d], [-3 Δ d ,-2 Δ d], and [-∞ ,-3 Δ d] use rd respectively₁₁d₁₂d₁₃=1000,1100,1110,1111 represent.In the present embodiment, Δ d is the size that each delay inequality is interval, namely time delay reference value；R represents delay inequality, and r is binary number in the present embodiment, if delay inequality p₀-p₁More than 0 r=0, otherwise, if delay inequality p₀-p₁Less than 0, then r=1.

Further, in actual design, for the size delta d that each delay inequality is interval, it is possible to by designing the buffer of different delay size, adjust interval size.Further, in actual design, by increasing more buffer and trigger, it is possible to delay inequality to be divided into more interval.

Fig. 4 is the schematic diagram of RESPONSE CALCULATION module and stabilizing determination module in an embodiment of the present invention.Delay inequality grade is derived from the submodule of delay inequality grade classification shown in Fig. 3 by the multiple time delays shown in Fig. 4.For each time delay pair, give corresponding weight according to its delay inequality grade.Due to d₁₃d₁₂d₁₁rd₀₁d₀₂d₀₃Have eight grades: 1111111,0111111,0011111,0001111,0000111,0000011,0000001,0000000, therefore there are eight weighted value w accordingly₇,w₆,w₅,w₄,w₃,w₂,w₁,w₀.In actual applications, designer can be configured according to practical situation, arranges in this example:

w₇=7

w₆=4

w₅=3

w₄=1

w₃=1

w₂=3

w₁=4

w₀=7

Wherein, due to w₇And w₀What represent is all the absolute value of the delay inequality situation more than 3 Δ d, therefore gives the weighted value that they are identical；In like manner, due to w₆And w₁Represent be all the absolute value of delay inequality more than 2 Δ d and the situation less than 3 Δ d, therefore give the weighted value that they are identical；In like manner, due to w₅And w₂Represent be all the absolute value of delay inequality more than Δ d and the situation less than 2 Δ d, therefore give the weighted value that they are identical；In like manner, due to w₄And w₃What represent is all the absolute value of the delay inequality situation less than Δ d, therefore gives the weighted value that they are identical.Delay inequality is more big, more impossible by environmental factors, as supply voltage, temperature etc. affect, becomes negative delay inequality from positive delay inequality, or becomes positive delay inequality from negative delay inequality, thus when dividing so that delay inequality is positive and negative, more stable, the weight being endowed is also bigger.

Weight and 0 and weight and 1 initial value be 0, to all of time delay to carrying out accumulation calculating.If the delay inequality of a time delay pair is more than 0, i.e. r=0, then weight and 0 is plus weighted value；If the delay inequality of a time delay pair is less than 0, i.e. r=1, then weight and 1 is plus weighted value.Finally compare weight and 0 and weight and 1 size, if weight and 0 is more than weight and 1, then the final response of strong PUF is 0, and otherwise the final response of strong PUF is 1.

For further stabilizing determination module being illustrated, in Fig. 4, stabilizing determination module instance illustrates.RESPONSE CALCULATION module has calculated that cumulative weight and 0 and weight and 1, due to the final response of strong PUF derive from weight and 0 and weight and 1 size compare, therefore, stabilizing determination module output stability be weight and 0 and weight and 1 absolute difference.This absolute value is more big, then more impossible by environmental factors, as supply voltage, temperature etc. affect, causes that final response changes, thus response is more stable.According to this absolute value, it is possible to CRP is ranked up, select the bigger CRP of absolute value in practical application.

Present invention employs two pieces of field programmable gate array (FieldProgrammableGateArray, FPGA) chips and achieve ten described strong PUF examples, its stability and randomness have been assessed, and compare with XOR arbitration PUF.

First having randomly selected 10000 excitations, carried out in different operating environments testing to assess its stability, normal operation circumstances is: ambient temperature T_E=23 DEG C, chip internal temperature T_I=29 DEG C, supply voltage V_S=1v.Table 1 gives 8 assessments environment configurations used by stability.To each environment configurations, each excitation repeatedly inputs strong PUF125 time, therefore each excitation has repeatedly input 1000 times altogether, the stability of one response is namely in these 1000 times, response when to have how many times be with normal operation is consistent, meanwhile, if the stability of a response is 100%, then stable response or stable CRP it are referred to as.Stability experiment result is as shown in Figure 5.

The environment configurations of table 1 stability assessment

	TE(℃)	TI(℃)	VS(v)
				Configuration 1	23	29	1
Configuration 2	23	29	1.15
				Configuration 3	23	29	0.85
Configuration 4	50	59	1
				Configuration 5	50	59	1.15
Configuration 6	50	59	0.85
				Configuration 7	-20	-5	1
Configuration 8	-20	-5	1.15
				Configuration 9	-20	-5	0.85

Fig. 5 gives under the number of different delay path, the present invention (represent with VPUF) and XOR arbitration PUF (representing with XPUF) stability.When latency path number is 10, average stability of the present invention is up to 97.44%, and the stability of XOR arbitration PUF is only 92.07%.When latency path number increases to 70, average stability of the present invention is still up to 94.15%, and the stability of XOR arbitration PUF only remains 72.63%, and therefore stability is improve 29.63% by the present invention.Fig. 6 gives under the number of different delay path, the stable CRP number proportion of the present invention and XOR arbitration PUF.When latency path number is 10, it is 87.62% that the present invention stablizes CRP proportion, and the stable CRP proportion of XOR arbitration PUF is only 67.14%.When latency path number increases to 70, the present invention stablizes CRP proportion and still reaches 70.91%, and the stable CRP proportion of XOR arbitration PUF only remains 6.42%, and therefore stable CRP number is improve 10.05 times by the present invention.The visible present invention, while ensureing safety, when namely latency path number is bigger, remains able to provide higher stability.

Fig. 7 gives under the number of different delay path, the randomness of the present invention and XOR arbitration PUF.On average, the randomness of the present invention is 49.72%, and the randomness of XOR arbitration PUF is 50.70%, and both are very close, and all close to ideal value 50%.The visible present invention does not destroy randomness while improving stability.

As shown in Figure 8, the method for designing of the unclonable functional circuit of strong physics of a kind of high stability of the present invention, the method includes:

Step S801, the input stimulus according to the unclonable functional circuit of strong physics, same saltus step is propagated by a plurality of latency path, produces multiple time delay value simultaneously.This step is realized by time delay generation module 10 as shown in Figure 1.

Step S802, selects multipair time delay value from multiple time delay values and carries out delay inequality and compare, and the delay inequality of each pair of time delay value is divided into multiple grade by size.This step is realized by time delay comparison module 20 as shown in Figure 1.

Step S803, the delay inequality grade according to each pair of time delay value, calculate the output response of the unclonable functional circuit of strong physics.This step is realized by RESPONSE CALCULATION module 30 as shown in Figure 1.

Step S804, the delay inequality grade according to each pair of time delay value, it determines whether excitation response pair is stable.This step is realized by stabilizing determination module 40 as shown in Figure 1.

In sum, the time delay value that a plurality of latency path produces is selected multipair time delay value by the present invention, the delay inequality of each time delay pair is divided into multiple time delay grade, delay inequality grade according to each pair of time delay value calculates the output response of the unclonable functional circuit of strong physics, also it is mapped to multi valued logic by delay inequality from real number field, utilizes more information to produce stable response.A plurality of latency path is less on the impact of CRP stability, both ensure that and safety in turn ensure that stability.Thus, the present invention ensure the unclonable functional circuit attack tolerant of strong physics meanwhile, it is capable to real-time online measuring delay inequality, and then increase substantially stability.

Certainly; the present invention also can have other various embodiments; when without departing substantially from present invention spirit and essence thereof; those of ordinary skill in the art are when can make various corresponding change and deformation according to the present invention, but these change accordingly and deformation all should belong to the scope of the claims appended by the present invention.

Claims (10)

1. the unclonable functional circuit of strong physics of a high stability, it is characterised in that including:

Time delay generation module, for the input stimulus according to the unclonable functional circuit of strong physics, is propagated same saltus step by a plurality of latency path, produces multiple time delay value simultaneously；

Time delay comparison module, carries out delay inequality compare for selecting multipair time delay value from the plurality of time delay value, and the delay inequality of each pair of time delay value is divided into multiple grade by size；

RESPONSE CALCULATION module, for the delay inequality grade according to described each pair of time delay value, calculates the output response of the unclonable functional circuit of strong physics；

Stabilizing determination module, for the delay inequality grade according to described each pair of time delay value, it determines whether excitation response pair is stable.

2. the unclonable functional circuit of strong physics according to claim 1, it is characterised in that described time delay generation module includes excitation mapping submodule and multiple latency path submodule,

Described excitation mapping submodule, for described input stimulus is mapped to each described latency path submodule, determines the composition of time delay subpath in latency path；

Described latency path submodule, is used for producing at least one time delay value.

3. the unclonable functional circuit of strong physics according to claim 2, it is characterised in that a plurality of latency path propagating saltus step is independent of one another or interactively with each other, and every latency path all has identical time delay nominal value.

4. the unclonable functional circuit of strong physics according to claim 1, it is characterised in that described input stimulus directly drives each bar latency path or by remapping each bar latency path of driving.

5. the unclonable functional circuit of strong physics according to claim 1, it is characterised in that time delay comparison module includes:

Time delay value pairing submodule, for the multiple time delay values produced by described time delay generation module, is combined into multiple time delay pair, and each time delay value at least occurs once in the plurality of time delay centering；

Delay inequality grade classification submodule, for comparing the delay inequality of each time delay pair, and carries out grade classification by delay inequality with default time delay reference value, and each grade represents a time delay interval.

6. the unclonable functional circuit of strong physics according to claim 5, it is characterised in that the delay inequality of each time delay pair described is carried out grade classification by the mode of mould revolution by described delay inequality grade classification submodule.

7. the unclonable functional circuit of strong physics according to claim 1, it is characterised in that RESPONSE CALCULATION module includes:

Time delay is to delay inequality grade weight calculation submodule, for the corresponding weighted value of delay inequality rating calculation according to each time delay pair described；

Weight is added and submodule by time delay, for by all time delays to being divided into delay inequality two classes minus more than zero-sum delay inequality, and calculate respectively two class time delays pair weight and；

Weight and comparison sub-module, for relatively described two class time delays pair weight and, and according to comparative result output response.

8. the unclonable functional circuit of strong physics according to claim 7, it is characterised in that the final response of the unclonable functional circuit of physics is produced by the voting machine of Weight.

9. the unclonable functional circuit of strong physics according to claim 7, it is characterised in that described stabilizing determination module according to the weight of described two class time delays pair and, it determines the probability of stability of an excitation response pair.

10. the method for designing of the unclonable functional circuit of strong physics of a high stability, it is characterised in that including:

Input stimulus according to the unclonable functional circuit of strong physics, is propagated same saltus step by a plurality of latency path, produces multiple time delay value simultaneously；

From the plurality of time delay value, select multipair time delay value carry out delay inequality and compare, and the delay inequality of each pair of time delay value is divided into multiple grade by size；

Delay inequality grade according to described each pair of time delay value, calculates the output response of the unclonable functional circuit of strong physics；

Delay inequality grade according to described each pair of time delay value, it determines whether excitation response pair is stable.