CN105825885B - Multilevel memory cell, read/write circuit and its operating method based on memristor - Google Patents

Abstract

The invention discloses a memristor-based multi-value storage unit, a read-write circuit and an operation method thereof; the memristor-based multi-value storage unit utilizes the resistive characteristic of the memristor, and is composed of a plurality of memristors Constructed in a special way of connection. The multi-value storage unit composed of this connection method inherits the advantages of memristor, small size, low power consumption and strong expandability. Compared with the traditional memristor storage structure, the multi-valued storage structure provides a larger storage space and provides a new idea for memory design. The read-write circuit of the multi-value storage unit includes a storage unit, a control switch and a voltage comparison circuit. The read-write circuit selects the read, write, and erase operations by applying pulse signals. The read-write circuit has a simple structure, requires few devices, and has accurate read results, and can be combined with an address selection circuit for large-scale array storage.

Description

Memristor-based multi-valued storage unit, read-write circuit and operating method thereof

technical field

The invention belongs to the field of memory, and more specifically relates to a memristor-based multi-valued storage unit and a read-write circuit thereof.

Background technique

Memristor was proposed by Cai Shaotang, a scientist at the University of California, Berkeley, in 1971. Professor Cai Shaotang predicted from the perspective of symmetry that in addition to capacitance, inductance and resistance, electronic circuits should also have a fourth basic component-memristor. Cai Shaotang pointed out that voltage v, current i, charge q and magnetic flux There should be six mathematical relationships between these four basic circuit variables: current is defined as the derivative of charge with respect to time i(t)=dq(t)/dt; voltage is the derivative of magnetic flux with respect to time Resistance is defined as the rate of change of voltage with current R = dv/di; capacitance is defined as the rate of change of charge with voltage C = dq/dv; inductance is defined as the rate of change of magnetic flux with current Another problem is that there is a lack of a method that can connect the charge q with the magnetic flux associated circuit elements, and this element is composed of charge q and magnetic flux To define the relationship between them, Cai Shaotang named the component as memristor

Stan Williams of the Hewlett-Packard Laboratory in the United States and his colleagues produced a memristive object when conducting extremely small circuit experiments. The results were published in the "Nature" magazine in May 2008. The discovery of memristor is comparable to the triode invented 100 years ago, and any industrial application of it may bring about a new round of industrial revolution. The Ministry of Science and Technology of China pointed out on its official website on April 13, 2010: "Scientists from Hewlett-Packard Laboratory in the United States wrote in the "Nature" magazine on April 8, 2010, stating that they had made a major breakthrough in the provision of memristor and discovered that memristor Boolean logic operations can be performed for data processing and storage applications".

Since the memristor proposed by Cai Shaotang was confirmed by Hewlett-Packard Labs, the application research of memristor has covered various fields from storage and logic reconstruction to neural learning and secure communication. One of the main applications of memristor is nonvolatile random access memory.

Contents of the invention

Based on the unique threshold voltage of the memristor and the characteristics of high and low resistance states, the present invention provides a circuit structure of a multi-value memory based on the memristor. This circuit structure utilizes the small size of the memristor and the state With the characteristics of fast change speed and good compatibility, it expands the field and implementation methods of multi-value memory, and avoids the dependence of traditional memristor-based multi-value storage units on MOS transistors; The realization method of the reading, writing and erasing functions of the value storage unit circuit, its purpose is to carry out reading, writing and erasing operations for the multi-value storage unit based on the memristor proposed by the present invention, and simultaneously combine the reading and writing circuit with the array The combination of the unit address selection circuit can effectively reduce the leakage current in the read-write circuit based on the memristive memory array.

The present invention provides a memristor-based multi-valued storage unit, including a first memristor S ₁ , a second memristor S ₂ , a third memristor S ₃ , a fourth memristor S ₄ , a Five memristors _S5 and sixth memristors _S6 ; the first end of the first memristor _S1 , the first end of the second memristor _S2 and the fourth memristor The first end of _S4 is connected as the input end of the multi-valued storage unit; the second end of the first memristor _S1 , the second end of the third memristor _S3 and the second end of the first memristor S3 The second end of the six memristor _S6 is connected as the output end of the multi-valued storage unit; the second end of the second memristor _S2 is connected to the first end of the third memristor _S3 connected; the second end of the fourth memristor _S4 is connected to the first end of the fifth memristor _S5 ; the second end of the fifth memristor _S5 is connected to the sixth memristor The first end of the resistor _S6 is connected.

Furthermore, the first memristor S ₁ , the second memristor S ₂ , the third memristor S ₃ , the fourth memristor S ₄ , the fifth memristor Both the device _S5 and the sixth memristor _S6 have a high-resistance state and a low-resistance state; and the initial states of the above six memristors are all in a high-resistance state; After the memristor threshold voltage is reached, the memristor switches from a low-impedance state to a high-impedance state.

Furthermore, when the first memristor S ₁ , the second memristor S ₂ , the third memristor S ₃ , the fourth memristor S ₄ , the fifth memristor When both the resistor _S5 and the sixth memristor _S6 are in a high-impedance state, the stored value of the multi-valued storage unit is 0; when the first memristor is in a low-impedance state, and the second to the sixth When the six memristors are in a high-impedance state, the storage value of the multi-valued storage unit is 1; when the first to third memristors are in a low-impedance state, and the fourth to sixth memristors are in a high-impedance state, The storage value of the multi-value storage unit is 2; when the first memristor to the sixth memristor are all in a low resistance state, the storage value of the multi-value storage unit is 3.

The present invention provides a read-write circuit based on the above-mentioned multi-valued storage unit, comprising a first control switch T ₁ , a second control switch T ₂ , a storage unit M ₁ , a cascaded resistor R ₁ , a first diode D _1. The second diode D ₂ , the third diode D ₃ , the first voltage comparator C ₁ , the second voltage comparator C ₂ and the third voltage comparator C ₃ ; the first control switch T ₁ control terminal The input signal is connected to the first end, and the circuit function is determined by the input signal; the second end of the first control switch _T1 is connected to the first end of the storage unit _M1 ; the second end of the storage unit _M1 , the cascaded resistor The first terminal of _R1 is connected to the first terminal of the second control switch T2; the control terminal of the second control switch _T2 is connected to the read signal, and when the circuit is in the read function _, the second control switch _T2 conducts connected; the second end of the second control switch _T2 is connected to the first end of the first diode _D1 ; the second end of the first diode _D1 is connected to the first end of the first voltage comparator _C1 The terminal is connected to the first terminal of the second diode _D2 ; the second terminal of the second diode _D2 , the first terminal of the third diode _D3 and the first terminal of the second voltage comparator _C2 connected; the second end of the third diode _D3 is connected to the first end of the third voltage comparator _C3 .

Further, the first control switch T ₁ and the second control switch T ₂ are insulated gate bipolar transistors IGBT; the first diode D ₁ , the second diode D ₂ and the The third diode _D3 is a crystal diode with voltage drop.

Furthermore, in the first voltage comparator C ₁ , the second voltage comparator C ₂ and the third voltage comparator C ₃ , when the input voltage of the voltage comparator is greater than the preset voltage of the voltage comparator , outputs a high-level signal, which is recorded as 1; when the input voltage of the voltage comparator is less than the preset voltage of the voltage comparator, it outputs a low-level signal, which is recorded as 0; when the voltage comparator has no signal input, the voltage comparator outputs a low-level signal.

Furthermore, the first voltage comparator C ₁ , the second voltage comparator C ₂ and the third voltage comparator C ₃ have four output states: 000, 100, 110, 111; and these four The first state corresponds to the four storage states of the multi-valued storage unit.

The present invention also provides a writing operation method based on the above-mentioned read-write circuit, by inputting a write signal at the first end and the control end of the first control switch _T1 , and controlling the second control switch _T2 to be turned off , to implement the write operation.

The present invention also provides a reset operation method based on the above-mentioned read-write circuit, by inputting a reset signal at the first end and the control end of the first control switch _T1 , and controlling the second control switch _T2 to be turned off , to realize the reset operation; wherein the amplitude of the reset signal is large enough and the input time is long enough to ensure that the multi-valued storage unit returns to the initial state.

The present invention also provides a read operation method based on the above-mentioned read-write circuit, by inputting a read signal at the first terminal and control terminal of the first control switch _T1 , and inputting a read signal at the control terminal of the second control switch _T2 Inputting the read signal pulse makes the second control switch _T2 turn on to realize the read operation; wherein, the amplitude of the read signal cannot exceed the threshold voltage of the memristor to ensure that the multi-valued storage unit _M1 will not be changed storage status.

Generally speaking, compared with the prior art, the above technical scheme conceived by the present invention has advantages due to the good characteristics of the memristor itself, the circuit structure of the multi-valued storage unit based on the memristor and the functions of reading, writing and erasing. The implementation method can obtain the following beneficial effects of non-volatile storage:

(1) The memristor-based multi-valued storage unit of the present invention can be expanded into the form of a storage array, has good scalability, and has good compatibility with traditional MOS circuits; simultaneously, after being expanded into a storage array, The storage capacity of the traditional storage unit is improved. The key leakage current problem in the existing memristive array storage technology is optimized, and the effectiveness of storage is improved.

(2) Compared with the traditional read and write circuits, the writing circuit and erasing circuit of the memristor-based multi-valued storage unit of the present invention uses fewer electronic devices, the overall circuit structure is simpler, and the power consumption is smaller.

(3) The multi-valued storage unit reading circuit based on memristor of the present invention utilizes the diode voltage drop to simulate threshold voltage characteristics, saves the quantity of voltage comparators and external comparison power supplies, and improves the resistance of the multi-valued storage unit of the memristor. The reading accuracy of the value unit effectively improves the accuracy of repeatedly reading and writing the memristive memory unit.

Description of drawings

Figure 1 is a schematic diagram of the volt-ampere characteristic curve of a bipolar memristor;

2 is a schematic structural diagram of a memristor-based multi-valued storage unit circuit provided by an embodiment of the present invention;

Fig. 3 is the volt-ampere characteristic curve of the memristor-based multi-valued storage unit provided by the embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a read, write, and erase circuit of a multi-valued storage unit based on a memristor according to the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The terms "first", "second", etc. (if any) in the present invention and the above drawings are used to distinguish similar objects and not necessarily to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of practice in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed instead, may include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.

Before introducing the technical solution of the present invention, some characteristics of the memristor used in the present invention are firstly introduced. Fig. 1 is a schematic diagram of the volt-ampere characteristic curve of the bipolar memristor; as can be seen from Fig. 1, when added to the memristor When the voltage across the resistor is greater than or equal to the first voltage threshold V ₁ , the memristor changes from a high-resistance state (the resistance value is denoted as R _OFF ) to a low-resistance state (the resistance value is denoted as R _ON ). When the voltage of the resistor is less than or equal to the second voltage threshold V ₂ , the memristor changes from a low resistance state to a high resistance state. When the memristor is in a high-resistance state, only forward bias will change its state from high resistance to low resistance, and reverse bias or no voltage bias will not change its state; When the memristor is in a low resistance state, only the reverse bias will change its state from low resistance to high resistance, and the forward bias or no voltage bias will not change its state.

Based on the above memristor characteristics, if multiple memristors with the same initial state and threshold voltage are connected in series with the same polarity, the state resistance changes of all memristors on the series circuit will be synchronized, and the first voltage of the whole series circuit will be The amplitudes of the threshold and the second voltage threshold are proportional to the number of memristors connected in series.

Based on the above characteristics of the memristor series circuit, multiple series circuits with different numbers of memristors can be connected in parallel to form the multi-valued storage unit, as shown in FIG. 2 . FIG. 3 shows the volt-ampere characteristic curve of the multi-valued storage unit based on the memristor; as shown in the figure, the resistance value of the multi-valued storage unit is related to the voltage applied across the multi-valued storage unit. Values "0", "1", "2" and "3" are stored by changing the resistance value of the multi-valued storage unit. The voltage at both ends of the multi-valued storage unit, the resistance value and the corresponding stored value are shown in Table 1.

Table I

It should be pointed out that the initial states of the memristors used in the present invention are all high-resistance states, and then the initial resistance value R _M1 of the multi-valued storage unit _M1 is

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

As shown in FIG. 4, FIG. 4 is a circuit diagram for reading and writing a multi-valued storage unit. The figure includes a first control switch T ₁ , a second control switch T ₂ , a storage unit M ₁ , a cascaded resistor R ₁ , a first diode D ₁ , a second diode D ₂ , and a third diode D _3. The first voltage comparator C ₁ , the second voltage comparator C ₂ and the third voltage comparator C ₃ . The control end of the first control switch _T1 is connected to the first end of the input signal, and the circuit function is determined by the input signal; the second end of the first control switch _T1 is connected to the upper end of the storage unit; the lower end of the storage unit _M1 , the cascaded resistor The upper end _{of R1} is connected to the first end of the second control switch T2; the control terminal of the second control switch _T2 is connected to the read signal, and when the circuit is in the read function, the second control switch _T2 is turned on; the second control The second end of the switch _T2 is connected to the upper end of the first diode _D1 ; the lower end of the first diode _D1 is connected to the input end of the first voltage comparator _C1 and the upper end of the second diode _D2 ; the second diode The lower end of the tube _D2 and the third diode _D3 are connected to the input end of the second voltage comparator _C2 ; the lower end of the third diode _D3 is connected to the input end of the third voltage comparator _C3 . The first to third voltage comparators (OUT ₁ -OUT ₃ ) finally have four output states, ie 000, 100, 110, 111 (0 represents low level, 1 represents high level).

In order to explain more clearly the working principle of the read-write circuit based on the multi-valued storage unit, the following elaborates the read-write process and the results of the circuit test:

(1) Write operation of the multi-valued storage unit: the first control switch T1 is connected to the write signal, and the second control switch T2 is turned off. At this time, the circuit is a series structure of the storage unit M1 and the cascaded resistor R1. Assuming that the write voltage is V _write , the voltage across the memory cell M1 is According to Table 1, find out the corresponding voltage to write data, and adjust the write voltage V _write to the corresponding voltage in Table 1 to write data.

(2) The read operation of the multi-valued storage unit: the first control switch T1 accesses the read signal, and the second control switch T2 conduction assumes that the read signal voltage is V _read (in order to prevent the read signal from changing the state of the memory cell, read The signal voltage V _read should be less than the first threshold voltage V1 of the single memristor, at this time, the node voltage at the connection between the lower end of the memory cell _M1 and the upper end of the cascaded resistor _R1 is It can be seen from Table 1 that the four different resistance states of the memory cell M1 generate four voltage levels at the nodes, and these four voltages correspond to the four values stored in the multi-valued memory cell.

When the value stored in the multi-valued storage unit is 3, the resistance value of the storage unit is the smallest at this time, and the value of the node voltage is the largest, and at least greater than three times the diode voltage drop, so at this time all voltage comparators have voltage signal input and are greater than 0 , the three-way voltage comparators output high-level signals.

When the value stored in the multi-valued storage unit is 2, the value of the node voltage is between two times diode and three times diode voltage drop, so only the first voltage comparator _C1 and the second voltage comparator _C2 have voltage at this time Input, the first voltage comparator _C1 and the second voltage comparator _C2 output a high-level signal, and the third voltage comparator _C3 outputs a low-level signal.

When the value stored in the multi-valued storage unit is 1, the value of the node voltage is between one time diode and two times diode voltage drop, so only the first voltage comparator _C1 has a voltage input at this time, and the first voltage comparator C ₁ outputs a high-level signal, and the second voltage comparator C ₂ and the third voltage comparator C ₃ output a low-level signal.

When the value stored in the multi-valued storage unit is 0, all the memristors in the multi-valued storage unit are in the initial high-impedance state, the resistance of the storage unit is the highest, and the node voltage value is the smallest and less than a single diode voltage drop. Comparators have no voltage signal input, so all voltage comparator outputs are 0.

By detecting the output state of the three-way voltage comparator, according to the corresponding relationship in Table 1, the stored value of the multi-valued storage unit can be read out.

(3) Erase operation of the multi-valued storage unit: the first control switch T1 is connected to the reset signal, and the second control switch T2 is turned off. At this time, the circuit is a series structure of the storage unit M1 and the cascaded resistor. Assuming that the reset voltage is V _reset , the voltage across the memory cell M1 is According to the volt-ampere characteristic curve of the memristor shown in FIG. 1 , as long as the value of V _reset is negative and large enough, all the memristors can return to the initial high-resistance state, and the erase reset operation is completed.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (8)

1. a kind of multilevel memory cell based on memristor, it is characterised in that including the first memristor S₁, the second memristor S₂, Three memristor S₃, the 4th memristor S₄, the 5th memristor S₅With the 6th memristor S₆；

The first memristor S₁First end, the second memristor S₂First end and the 4th memristor S₄First Input after the connection of end as the multilevel memory cell；The first memristor S₁The second end, the 3rd memristor S₃ The second end and the 6th memristor S₆The connection of the second end after output end as the multilevel memory cell；

The second memristor S₂The second end and the 3rd memristor S₃First end be connected；The 4th memristor S₄'s Second end and the 5th memristor S₅First end be connected；The 5th memristor S₅The second end and the 6th memristor S₆First end be connected；

The first memristor S₁, the second memristor S₂, the 3rd memristor S₃, the 4th memristor S₄, described Five memristor S₅With the 6th memristor S₆It is respectively provided with high-impedance state and low resistance state；And the original state of above-mentioned six memristors is equal In high-impedance state state；After memristor both end voltage exceedes memristor threshold voltage, the memristor is switched to from low resistance state High-impedance state；

As the first memristor S₁, the second memristor S₂, the 3rd memristor S₃, the 4th memristor S₄, it is described 5th memristor S₅With the 6th memristor S₆When being in high-impedance state, the multilevel memory cell storage value is 0；When described First memristor is in low resistance state, and when the second to the 6th memristor is in high-impedance state, the multilevel memory cell storage value is 1；When the first to the 3rd memristor is in low resistance state, and the 4th to the 6th memristor is in high-impedance state, the multilevel storage list First storage value is 2；When the first memristor is in low resistance state to the 6th memristor, the multilevel memory cell storage value is 3.

2. a kind of read/write circuit of the multilevel memory cell based on described in claim 1, it is characterised in that opened including the first control Close T₁, the second controlling switch T₂, memory cell M₁, cascade resistance R₁, the first diode D₁, the second diode D₂, the 3rd diode D₃, first voltage comparator C₁, second voltage comparator C₂With tertiary voltage comparator C₃；

The first controlling switch T₁Control terminal and the first termination input signal, by input signal decision-making circuit function；Described first Controlling switch T₁Second end and memory cell M₁First end is connected；The memory cell M₁The second end, cascade resistance R₁First End and the second controlling switch T₂First end be connected；The second controlling switch T₂Control termination read signal, work(is read when circuit is in During energy, the second controlling switch T₂Conducting；

The second controlling switch T₂Second end and the first diode D₁First end is connected；The first diode D₁Second End, first voltage comparator C₁First end and the second diode D₂First end is connected；The second diode D₂It is second end, described 3rd diode D₃First end and second voltage comparator C₂First end is connected；The 3rd diode D₃Second end and described the Three voltage comparator C₃First end is connected.

3. read/write circuit as claimed in claim 2, it is characterised in that the first controlling switch T₁Opened with the described second control Close T₂For insulated gate bipolar transistor IGBT；The first diode D₁, the second diode D₂With the 3rd diode D₃It is the crystal diode with pressure drop.

4. read/write circuit as claimed in claim 2, it is characterised in that in the first voltage comparator C₁, the second voltage Comparator C₂With the tertiary voltage comparator C₃In, when voltage comparator input voltage is more than voltage comparator predeterminated voltage, High ordinary mail number is exported, is designated as 1；When voltage comparator input voltage is less than voltage comparator predeterminated voltage, LOW signal is exported, It is designated as 0；When voltage comparator no signal inputs, voltage comparator output LOW signal.

5. read/write circuit as claimed in claim 4, it is characterised in that the first voltage comparator C₁, the second voltage ratio Compared with device C₂With the tertiary voltage comparator C₃There are four kinds of output states：000,100,110,111；And these four states with it is described Four kinds of storage states of multilevel memory cell are corresponding.

6. a kind of write operation method of the read/write circuit based on described in claim 2, it is characterised in that by the described first control System switch T₁First end and control terminal input write signal, and control the second controlling switch T₂Disconnect, to realize write operation.

7. a kind of reset operation method of the read/write circuit based on described in claim 2, it is characterised in that by described first Controlling switch T₁First end and control terminal input reset signal, and control the second controlling switch T₂Disconnect, reset behaviour to realize Make；The amplitude of wherein described reset signal is sufficiently large and input time long enough is at the beginning of to ensure that the multilevel memory cell reverts to Beginning state.

8. a kind of read operation method of the read/write circuit based on described in claim 2, it is characterised in that by the described first control System switch T₁First end and control terminal input read signal, and in the second controlling switch T₂Signal pulse is read in control terminal input So that the second controlling switch T₂Conducting, to realize read operation；Wherein, the amplitude of the read signal is no more than memristor threshold Threshold voltage size, it is ensured that multilevel memory cell M will not be changed₁Storage state.