CN105825885B - Multilevel memory cell, read/write circuit and its operating method based on memristor - Google Patents
Multilevel memory cell, read/write circuit and its operating method based on memristor Download PDFInfo
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- CN105825885B CN105825885B CN201610160484.5A CN201610160484A CN105825885B CN 105825885 B CN105825885 B CN 105825885B CN 201610160484 A CN201610160484 A CN 201610160484A CN 105825885 B CN105825885 B CN 105825885B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
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Abstract
The invention discloses a kind of multilevel memory cell based on memristor, read/write circuit and its operating method；The multilevel memory cell based on memristor is the resistive characteristic using memristor, is made up of multiple memristors with special connected mode.The advantages of multilevel memory cell of this connected mode composition inherits memristor, and small volume is low in energy consumption, and expansibility is strong.Compared to traditional memristor storage organization, the multilevel storage structure provides bigger memory space, and a kind of new thinking is provided for reservoir designs.The read/write circuit of the multilevel memory cell includes memory cell, controlling switch and voltage comparator circuit.The read/write circuit is selected reading and writing, erasing operation by applying pulse signal, and this read/write circuit is simple in construction, and required device is few, is read result accurately and can be combined addressing circuit for large scale array storage.
Description
Technical field
The invention belongs to memory area, more particularly, to a kind of multilevel memory cell based on memristor and its reading
Write circuit.
Background technology
Memristor is that the scientist Cai Shaotang of California, USA university Berkeley proposed in 1971, Cai Shaotang
Professor from symmetry angle foretell propose, in addition to electric capacity, inductance and resistance, electronic circuit should also exist the 4th kind of primary element-
Memristor.Cai Shaotang points out, voltage v, electric current i, electric charge q and magnetic fluxThere should be six kinds between this 4 basic circuit variables
Mathematical relationship：Current definition is derivative i (t)=dq (t)/dt of the electric charge on the time；Voltage is magnetic flux leading on the time
NumberResistance is defined as rate of change R=dv/di of the voltage with electric current；Electric capacity is defined as electric charge with voltage
Rate of change C=dq/dv；Inductance is defined as rate of change of the magnetic flux with electric currentAlso a problem has been the absence of one
Kind can be by electric charge q and magnetic fluxThe circuit element associated, and this element is i.e. by electric charge q and magnetic fluxBetween
Relation defines, and the element is named as memristor by Cai Shaotang
This smooth Williams of HP Lab of the U.S. and its colleague produce memristor when carrying out minimal type Experiment of Electrical Circuits
Material object, its achievement is published in May, 2008《nature》On magazine.The discovery of memristor is enough what is invented before matching in excellence or beauty 100 years
Triode, its any one commercial application may all bring the Industrial Revolution of a new round.Chinese science and technology portion on April 13rd, 2010
Pointed out in its official website：" HP Lab of U.S. scientist exists on April 8th, 2010《It is natural》Expression is write articles on magazine, he
Obtain important breakthrough in memristor offer, it is found that memristor can carry out boolean calculation, should for data processing and storage
With ".
After the memristor that Cai Shaotang is proposed is confirmed by HP Lab, the application study of memristor is covered from storing and patrol
The every field for being reconfigured to nerve study and secret communication is collected, memristor has non-volatile memory capability in itself, therefore is based on recalling
The nonvolatile random access memory for hindering device is one of main application of memristor.
The content of the invention
Characteristic of the present invention based on the distinctive threshold voltage of memristor and with high and low two kinds of resistance states, there is provided a kind of
The circuit structure of multivalued storage based on memristor, this circuit structure is using memristor small volume, state change speed is fast,
The features such as compatibility is good, extends field and the implementation method of multivalued storage, and avoids traditional multivalue based on memristor and deposit
Dependence of the storage unit to metal-oxide-semiconductor；Reading and writing, the erasing work(of the multilevel memory cell circuit based on memristor have been inquired into simultaneously
The implementation method of energy, its object is to read and write, wipe for the multilevel memory cell proposed by the present invention based on memristor
Operation, while this read/write circuit is combined to effectively reduce with array element addressing circuit and is currently based on the read-write of memristor storage array
Leakage current in circuit.
The invention provides a kind of multilevel memory cell based on memristor, including the first memristor S1, the second memristor
S2, the 3rd memristor S3, the 4th memristor S4, the 5th memristor S5With the 6th memristor S6；The first memristor S1First
End, the second memristor S2First end and the 4th memristor S4First end connection after be used as the multilevel storage list
The input of member；The first memristor S1The second end, the 3rd memristor S3The second end and the 6th memristor S6
The connection of the second end after output end as the multilevel memory cell；The second memristor S2The second end and the described 3rd
Memristor S3First end be connected；The 4th memristor S4The second end and the 5th memristor S5First end be connected；Institute
State the 5th memristor S5The second end and the 6th memristor S6First end be connected.
Further, the first memristor S1, the second memristor S2, the 3rd memristor S3, the described 4th
Memristor S4, the 5th memristor S5With the 6th memristor S6It is respectively provided with high-impedance state and low resistance state；And above-mentioned six memristors
The original state of device is in high-impedance state state；After memristor both end voltage exceedes memristor threshold voltage, the memristor
High-impedance state is switched to from low resistance state.
Further, as the first memristor S1, the second memristor S2, the 3rd memristor S3, described
Four memristor S4, the 5th memristor S5With the 6th memristor S6When being in high-impedance state, the multilevel memory cell is deposited
Stored Value is 0；When first memristor is in low resistance state, and the second to the 6th memristor is in high-impedance state, the multivalue is deposited
Storage unit storage value is 1；When the first to the 3rd memristor is in low resistance state, and the 4th to the 6th memristor is in high-impedance state,
The multilevel memory cell storage value is 2；When the first memristor is in low resistance state to the 6th memristor, the multilevel storage
Unit storage value is 3.
The invention provides a kind of read/write circuit based on above-mentioned multilevel memory cell, including the first controlling switch T1、
Second controlling switch T2, memory cell M1, cascade resistance R1, the first diode D1, the second diode D2, the 3rd diode D3,
One voltage comparator C1, second voltage comparator C2With tertiary voltage comparator C3；First controlling switch T1Control terminal and first end
Input signal is connect, by input signal decision-making circuit function；The first controlling switch T1Second end and memory cell M1First end phase
Even；The memory cell M1The second end, cascade resistance R1First end end and the second controlling switch T2First end be connected；Institute
State the second controlling switch T2Control termination read signal, when circuit, which is in, reads function, the second controlling switch T2Conducting；It is described
Second controlling switch T2Second end and the first diode D1First end is connected；The first diode D1Second end, the first electricity
Press comparator C1First end and the second diode D2First end is connected；The second diode D2Second end, the 3rd diode
D3First end and second voltage comparator C2First end is connected；The 3rd diode D3Second end is compared with the tertiary voltage
Device C3First end is connected.
Further, the first controlling switch T1With the second controlling switch T2For insulated gate bipolar transistor
IGBT；The first diode D1, the second diode D2With the 3rd diode D3It is the pole of crystal two with pressure drop
Pipe.
Further, in the first voltage comparator C1, the second voltage comparator C2With the tertiary voltage ratio
Compared with device C3In, when voltage comparator input voltage is more than voltage comparator predeterminated voltage, high ordinary mail number is exported, is designated as 1；Work as electricity
When pressure comparator input voltage is less than voltage comparator predeterminated voltage, LOW signal is exported, is designated as 0；When voltage comparator is without letter
Number input when, voltage comparator output LOW signal.
Further, the first voltage comparator C1, the second voltage comparator C2Compare with the tertiary voltage
Device C3There are four kinds of output states：000,100,110,111；And these four states and four kinds of storage shapes of the multilevel memory cell
State is corresponding.
Present invention also offers a kind of write operation method based on above-mentioned read/write circuit, by being opened in the described first control
Close T1First end and control terminal input write signal, and control the second controlling switch T2Disconnect, to realize write operation.
Present invention also offers a kind of reset operation method based on above-mentioned read/write circuit, by the described first control
Switch T1First end and control terminal input reset signal, and control the second controlling switch T2Disconnect, reset operation to realize；
The amplitude of wherein described reset signal is sufficiently large and input time long enough is to ensure that the multilevel memory cell reverts to initially
State.
Present invention also offers a kind of read operation method based on above-mentioned read/write circuit, by being opened in the described first control
Close T1First end and control terminal input read signal, and in the second controlling switch T2Control terminal input is read signal pulse and caused
The second controlling switch T2Conducting, to realize read operation；Wherein, the amplitude of the read signal is no more than memristor threshold value electricity
Press size, it is ensured that multilevel memory cell M will not be changed1Storage state.
In general, by the contemplated above technical scheme of the present invention compared with prior art, due to memristor itself
Good characteristic, the circuit structure of the multilevel memory cell based on memristor and reading and writing, the implementation method for wiping function, can
Obtain the beneficial effect of following non-volatile memories：
(1) multilevel memory cell based on memristor of the invention can be extended to the form of storage array, have fine
Scalability, and have good compatibility with conventional MOS circuit；Simultaneously after storage array is extended to, tradition is improved
The memory capacity of memory cell.Current leakage crucial in existing memristor array memory technology is optimized, improves storage
Validity.
(2) write circuit and erasing circuit of the multilevel memory cell based on memristor of the invention, read and write compared to tradition
Circuit, the electronic device used is less, and integrated circuit structure is simpler, and power consumption is smaller.
(3) the multilevel memory cell reading circuit based on memristor of the invention, diode drop analog threshold electricity is utilized
Characteristic is pressed, saves the quantity of voltage comparator power supply compared with external, improves the resistance list of memristor multilevel memory cell
The reading accuracy of member, it is effectively improved repeatedly repeatedly to the accuracy of memristor memory cell read-write.
Brief description of the drawings
Fig. 1 is the VA characteristic curve schematic diagram of bipolarity memristor；
Fig. 2 is the multilevel memory cell electrical block diagram provided in an embodiment of the present invention based on memristor；
Fig. 3 is the multilevel memory cell VA characteristic curve provided in an embodiment of the present invention based on memristor；
Fig. 4 is multilevel memory cell reading and writing of the present invention based on memristor, erasing circuit structural representation.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Conflict can is not formed each other to be mutually combined.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The (if present)s such as term " first ", " second " in of the invention and above-mentioned accompanying drawing are for distinguishing similar pair
As without for describing specific order or precedence.It should be appreciated that the data so used in the appropriate case can be with
Exchange, so that embodiments of the invention described herein for example can be with suitable in addition to those for illustrating or describing herein
Sequence is implemented.In addition, term " comprising " and " having " and their any deformation, it is intended that cover it is non-exclusive include, example
Such as, process, method, system, product or the equipment for containing series of steps or unit are not necessarily limited to those clearly listed
Step or unit, but may include not list clearly or for intrinsic other of these processes, method, product or equipment
Step or unit.
Before technical scheme is introduced, some characteristics of memristor used in the present invention, Fig. 1 are introduced first
For the VA characteristic curve schematic diagram of bipolarity memristor；It will be seen from figure 1 that when be added in memristor both ends voltage be more than etc.
In first voltage threshold value V1When, from high resistant state of value, (resistance is designated as R to memristorOFF) being changed into low-resistance state of value, (resistance is designated as RON),
When the voltage for being added in memristor is less than or equal to second voltage threshold value V2When, memristor is changed into high resistant state of value from low-resistance state of value.
When memristor is in high resistant state of value, only forward bias can cause its state to be changed into low-resistance from high resistant, reverse bias or
It is no-voltage biasing, is changed all without its state is caused；When memristor is in low resistive state, only reverse bias meeting
So that its state is changed into high resistant, forward bias or no-voltage biasing from low-resistance, changed all without its state is caused.
Based on above-mentioned memristor characteristic, multiple original states and threshold voltage identical memristor same polarity are connected, then
The state resistance state change of all memristors will be synchronous on this series circuit, the first voltage threshold value of overall series circuit and second
The amplitude of voltage threshold and the memristor number direct proportionality connected.
, can with parallel form by the different series circuit of multiple memristor numbers based on above-mentioned memristor series circuit characteristic
The multilevel memory cell is formed, as shown in Figure 2.It is the multilevel memory cell C-V characteristic based on memristor shown in Fig. 3
Curve；As illustrated, the resistance of the multilevel memory cell is relevant with the voltage that multilevel memory cell both ends are applied.By more
The change in resistance of value memory cell stores numerical value " 0 ", " 1 ", " 2 " and " 3 ".Multilevel memory cell both end voltage, resistance and right
Numerical value should be stored as shown in Table 1.
Table one
It is pointed out that the memristor original state used in the present invention is high resistant state of value, then multilevel storage
Unit M1Initial resistance RM1For
Below in conjunction with the accompanying drawings and embodiment the present invention is described in detail.
As shown in figure 4, Fig. 4 is multilevel memory cell read/write circuit figure.Figure includes the first controlling switch T1, second control
Switch T2, memory cell M1, cascade resistance R1, the first diode D1, the second diode D2, the 3rd diode D3, first voltage ratio
Compared with device C1, second voltage comparator C2With tertiary voltage comparator C3.First controlling switch T1Control terminal and the first termination input letter
Number, by input signal decision-making circuit function；First controlling switch T1Second end is connected with memory cell upper end；The memory cell
M1Lower end, cascade resistance R1Upper end and the second controlling switch T2First end be connected；The second controlling switch T2Control terminal
Read signal is connect, when circuit, which is in, reads function, the second controlling switch T2Conducting；Second controlling switch T2Second end and the one or two pole
Pipe D1Upper end is connected；First diode D1Lower end, first voltage comparator C1Input and the second diode D2Upper end is connected；The
Two diode D2Lower end, the 3rd diode D3With second voltage comparator C2Input is connected；3rd diode D3Lower end and the 3rd
Voltage comparator C3Input is connected.Described first to tertiary voltage comparator (OUT1~OUT3) finally there are four kinds of output states
I.e. 000,100,110,111 (0 represents low level, and 1 represents high level).
For read/write circuit operation principle of the apparent explanation based on multilevel memory cell, its read-write is carefully illustrated below
The result of process and circuit test：
(1) write operation of multilevel memory cell：First controlling switch T1 accesses write signal, and the second controlling switch T2 disconnects,
Now circuit is memory cell M1 and cascades resistance R1 cascaded structures.Assuming that write-in voltage is Vwrite, then memory cell M1 both ends
Voltage isAccording to table one, the corresponding voltage for needing to write data is found out, and will write-in voltage Vwrite
Size be adjusted in table one i.e. writable data after corresponding voltage.
(2) read operation of multilevel memory cell：Signal is read in first controlling switch T1 accesses, and the second controlling switch T2 is led
It is logical, it is assumed that reading signal voltage is Vread(change state of memory cells to prevent from reading signal, read signal voltage VreadShould
Less than the single memristor first threshold voltage V1), now memory cell M1Lower end and cascade resistance R1Upper end junction node
Voltage isAs shown in Table 1, tetra- kinds of different resistance value states of memory cell M1 generate four kinds at node
Voltage class, these four voltages correspond to four kinds of numerical value of multilevel memory cell storage.
When multilevel memory cell storage numerical value is 3, now memory cell resistance is minimum, and the value of node voltage is maximum, and
At least above the diode drop of three times, so now all voltage comparators have voltage signal to input and more than 0, three roads electricity
Pressure comparator exports high ordinary mail number.
When multilevel memory cell storage numerical value is 2, the value of node voltage is between twice of diode and three times diode pressure
Between drop, so now there was only first voltage comparator C1With second voltage comparator C2There are control source, first voltage comparator
C1With second voltage comparator C2Export high ordinary mail number, tertiary voltage comparator C3Export LOW signal.
When multilevel memory cell storage numerical value is 1, the value of node voltage is between one times of diode and two times of diode pressures
Between drop, so now there was only first voltage comparator C1There are control source, first voltage comparator C1High ordinary mail number is exported, the
Two voltage comparator C2With tertiary voltage comparator C3Export LOW signal.
When multilevel memory cell storage numerical value is 0, now all memristors are in initial height in multilevel memory cell
Resistance state, memory cell resistance highest, node voltage value is minimum and is less than single diode drop, and now all voltage comparators are equal
No-voltage signal inputs, therefore the output of all voltage comparators is 0.
By detecting the output state of three road voltage comparators, according to the corresponding relation of table one, you can read multilevel storage list
The storage numerical value of member.
(3) erasing operation of multilevel memory cell：First controlling switch T1 accesses reset signal, and the second controlling switch T2 breaks
Open, now circuit is memory cell M1 and cascades resistant series structure.Assuming that resetting voltage is Vreset, then memory cell M1 both ends
Voltage isThe memristor VA characteristic curve according to Fig. 1, as long as VresetValue for it is negative and it is sufficiently large i.e.
It may be such that all memristors reply initial high-impedance state, complete erasing and reset operation.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., all should be included
Within protection scope of the present invention.
Claims (8)
1. a kind of multilevel memory cell based on memristor, it is characterised in that including the first memristor S1, the second memristor S2,
Three memristor S3, the 4th memristor S4, the 5th memristor S5With the 6th memristor S6；
The first memristor S1First end, the second memristor S2First end and the 4th memristor S4First
Input after the connection of end as the multilevel memory cell；The first memristor S1The second end, the 3rd memristor S3
The second end and the 6th memristor S6The connection of the second end after output end as the multilevel memory cell；
The second memristor S2The second end and the 3rd memristor S3First end be connected；The 4th memristor S4's
Second end and the 5th memristor S5First end be connected；The 5th memristor S5The second end and the 6th memristor
S6First end be connected；
The first memristor S1, the second memristor S2, the 3rd memristor S3, the 4th memristor S4, described
Five memristor S5With the 6th memristor S6It is respectively provided with high-impedance state and low resistance state；And the original state of above-mentioned six memristors is equal
In high-impedance state state；After memristor both end voltage exceedes memristor threshold voltage, the memristor is switched to from low resistance state
High-impedance state；
As the first memristor S1, the second memristor S2, the 3rd memristor S3, the 4th memristor S4, it is described
5th memristor S5With the 6th memristor S6When being in high-impedance state, the multilevel memory cell storage value is 0；When described
First memristor is in low resistance state, and when the second to the 6th memristor is in high-impedance state, the multilevel memory cell storage value is
1；When the first to the 3rd memristor is in low resistance state, and the 4th to the 6th memristor is in high-impedance state, the multilevel storage list
First storage value is 2；When the first memristor is in low resistance state to the 6th memristor, the multilevel memory cell storage value is 3.
2. a kind of read/write circuit of the multilevel memory cell based on described in claim 1, it is characterised in that opened including the first control
Close T1, the second controlling switch T2, memory cell M1, cascade resistance R1, the first diode D1, the second diode D2, the 3rd diode
D3, first voltage comparator C1, second voltage comparator C2With tertiary voltage comparator C3；
The first controlling switch T1Control terminal and the first termination input signal, by input signal decision-making circuit function；Described first
Controlling switch T1Second end and memory cell M1First end is connected；The memory cell M1The second end, cascade resistance R1First
End and the second controlling switch T2First end be connected；The second controlling switch T2Control termination read signal, work(is read when circuit is in
During energy, the second controlling switch T2Conducting；
The second controlling switch T2Second end and the first diode D1First end is connected；The first diode D1Second
End, first voltage comparator C1First end and the second diode D2First end is connected；The second diode D2It is second end, described
3rd diode D3First end and second voltage comparator C2First end is connected；The 3rd diode D3Second end and described the
Three voltage comparator C3First end is connected.
3. read/write circuit as claimed in claim 2, it is characterised in that the first controlling switch T1Opened with the described second control
Close T2For insulated gate bipolar transistor IGBT；The first diode D1, the second diode D2With the 3rd diode
D3It is the crystal diode with pressure drop.
4. read/write circuit as claimed in claim 2, it is characterised in that in the first voltage comparator C1, the second voltage
Comparator C2With the tertiary voltage comparator C3In, when voltage comparator input voltage is more than voltage comparator predeterminated voltage,
High ordinary mail number is exported, is designated as 1；When voltage comparator input voltage is less than voltage comparator predeterminated voltage, LOW signal is exported,
It is designated as 0；When voltage comparator no signal inputs, voltage comparator output LOW signal.
5. read/write circuit as claimed in claim 4, it is characterised in that the first voltage comparator C1, the second voltage ratio
Compared with device C2With the tertiary voltage comparator C3There are four kinds of output states：000,100,110,111；And these four states with it is described
Four kinds of storage states of multilevel memory cell are corresponding.
6. a kind of write operation method of the read/write circuit based on described in claim 2, it is characterised in that by the described first control
System switch T1First end and control terminal input write signal, and control the second controlling switch T2Disconnect, to realize write operation.
7. a kind of reset operation method of the read/write circuit based on described in claim 2, it is characterised in that by described first
Controlling switch T1First end and control terminal input reset signal, and control the second controlling switch T2Disconnect, reset behaviour to realize
Make；The amplitude of wherein described reset signal is sufficiently large and input time long enough is at the beginning of to ensure that the multilevel memory cell reverts to
Beginning state.
8. a kind of read operation method of the read/write circuit based on described in claim 2, it is characterised in that by the described first control
System switch T1First end and control terminal input read signal, and in the second controlling switch T2Signal pulse is read in control terminal input
So that the second controlling switch T2Conducting, to realize read operation；Wherein, the amplitude of the read signal is no more than memristor threshold
Threshold voltage size, it is ensured that multilevel memory cell M will not be changed1Storage state.
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| CN106920568B (en) * | 2017-03-10 | 2019-10-08 | 东南大学 | A kind of read/write circuit of four values memristor |
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| DE102018213147A1 (en) * | 2018-08-07 | 2020-02-13 | Robert Bosch Gmbh | Refreshing data stored using memristors |
| CN111143895B (en) * | 2018-11-02 | 2024-07-19 | 特忆智能科技 | Non-repetitive recording code comparator with memristor and series resistor |
| CN110797063B (en) * | 2019-09-17 | 2021-05-25 | 华中科技大学 | Memristor memory chip and operation method thereof |
| CN110797062B (en) * | 2019-09-17 | 2021-07-06 | 华中科技大学 | Memristor read-write circuit and method |
| CN110827897B (en) * | 2019-09-17 | 2021-10-01 | 华中科技大学 | Over-write prevention circuit and method of memristor |
| CN115440277A (en) * | 2021-05-07 | 2022-12-06 | 浙江树人学院 | Memristor-based XOR logic circuit |
| CN114121087B (en) * | 2021-11-16 | 2024-03-26 | 上海集成电路装备材料产业创新中心有限公司 | Reading circuit of multi-value memory |
| CN115019853B (en) * | 2022-04-28 | 2024-06-25 | 深圳市金和思锐科技有限公司 | Memristor-based multi-bit memory integrated memory unit and control method |
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