CN113314178B - Memristor reading and writing method - Google Patents
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- CN113314178B CN113314178B CN202110495859.4A CN202110495859A CN113314178B CN 113314178 B CN113314178 B CN 113314178B CN 202110495859 A CN202110495859 A CN 202110495859A CN 113314178 B CN113314178 B CN 113314178B
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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Abstract
The invention discloses a memristor read-write method, which at least comprises a write-in unit and a read-out unit, wherein when information is written into a memristor, the write-in unit is switched on to form a write-in loop, and the write-in unit generates forward voltage or reverse voltage at two ends of the memristor to enable the memristor to be in a high resistance state or a low resistance state; when the state of the memristor is read, a reading unit is switched on to form a reading loop, the reading unit generates an excitation signal at one end of the memristor, and reads an output state at the other end of the memristor so as to acquire the state of the memristor. Compared with the prior art, the technical scheme of the invention can realize richer read-write control and logic control functions by using a simpler circuit structure.
Description
Technical Field
The invention relates to the technical field of memristor reading and writing, in particular to a memristor reading and writing method.
Background
In 1971, the chinese scientist professor zeitle proposed the concept of memristors, however, researchers have progressed slowly during the thirty years after the concept was proposed. Until 2008, hewlett packard laboratory prepared the first nanometer-sized memristor element in the world, immediately aroused great interest of numerous scholars and engineers, and the memristor became a new hot spot for research. The invention of the memristor is a milestone in the development history of the technical field of electronic information.
Since the memristor has the characteristics of memory property, and the calculation result can be stored in the memristor, more and more students apply the memristor element to the circuit design, especially the fields of information storage, logic operation and the like in the current research. However, the current memristor has high requirements on reading and writing of the circuit, and the practical application of the memristor is limited.
Therefore, it is necessary to provide a technical solution to solve the technical problems in the prior art.
Disclosure of Invention
In view of the above, it is necessary to provide a memristor read-write method, which can implement richer read-write control and logic control functions with a simpler circuit structure.
In order to solve the technical problems in the prior art, the technical scheme of the invention is as follows:
a memristor read-write method at least comprises a write-in unit and a read-out unit, wherein when information is written into a memristor, the write-in unit is switched on to form a write-in loop, the write-in unit generates forward voltage at two ends of the memristor to enable the memristor to be in a high resistance state, or the write-in unit generates reverse voltage at two ends of the memristor to enable the memristor to be in a low resistance state;
when the state of the memristor is read, a reading unit is switched on to form a reading loop, the reading unit generates an excitation signal at one end of the memristor, and reads an output state at the other end of the memristor so as to acquire the state of the memristor.
As a further improvement, the reading unit at least comprises a first resistor R1, an excitation module and a state acquisition module, wherein the excitation module is connected with one end of the memristor and is used for outputting a voltage signal to the memristor; the other end of the memristor is connected with one end of a first resistor R1 to serve as a state output end, and the other end of the first resistor R1 is grounded; the state acquisition module is connected with the state output end and used for acquiring the voltage state of the state output end and acquiring the state of the memristor.
As a further improvement, the state acquisition module is implemented by using a comparator, two input ends of the comparator are respectively connected with two ends of the memristor, and the output of the comparator is the state of the memristor.
As a further improvement, the resistance value of the first resistor R1 is between the high resistance state and the low resistance state of the memristor.
As a further improvement scheme, the memristor is 100K omega in the high-resistance state, 100 omega in the low-resistance state, and the first resistor R1 is 1K omega to 10K omega in resistance.
As a further improvement, the writing unit is realized by adopting a MOS logic circuit.
As a further improvement, the write unit at least includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5, wherein the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are NMOS transistors, the fourth MOS transistor M4 and the fifth MOS transistor M5 are PMOS transistors, a gate of the first MOS transistor M1 is connected to a gate of the second MOS transistor M2 and a gate of the fourth MOS transistor M4 to serve as a first control terminal, and a drain of the first MOS transistor M1 is connected to a drain of the second MOS transistor M2 and a drain of the fourth MOS transistor M4; the source electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3 and the drain electrode of the fifth MOS transistor M5; the grid electrode of the third MOS transistor M3 is connected with the grid electrode of the fifth MOS transistor M5 and one end of the memristor to serve as a second control end, and the source electrode of the second MOS transistor M2 is connected with the other end of the memristor; the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 are connected to a power supply terminal, and the source of the third MOS transistor M3 is grounded.
As a further improvement scheme, when the first control terminal is at a high level, the writing of the high-resistance state or the low-resistance state of the memristor is carried out according to the level state of the second control terminal.
As a further improvement, the write unit is used to perform an exclusive or function, wherein the first control terminal and the second control terminal are used as input terminals, and the source of the second MOS transistor M2 is connected to the other end of the memristor as an output terminal.
As a further improvement, the state of the memristor is read through the reading unit, and the exclusive-or logic function is enabled to have a second logic output.
Compared with the prior art, the memristor read-write function is realized through a simple circuit structure, the state of the memristor is read in a resistor voltage division mode, the write-in of the state of the memristor is realized through the MOS logic circuit, the read-write function is realized, the XOR logic function can be realized, the actual circuit function is greatly enriched, and the flexibility and the expandability of the actual circuit design are improved.
Drawings
FIG. 1 is a symbolic illustration of the elements of a memristor in the present invention.
FIG. 2 is a schematic diagram of the principle of the memristor read-write method of the present invention.
FIG. 3 is a schematic diagram of a reading unit according to the present invention.
FIG. 4 is a schematic diagram of a reading unit according to another embodiment of the present invention.
FIG. 5 is a schematic diagram of a write unit according to the present invention.
The following specific embodiments will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.
The resistance value of the memristor has obvious switching characteristics and controllability, namely, when the forward or reverse voltage applied to two ends of the memristor exceeds a certain threshold value, the resistance value of the memristor is converted between a high resistance state and a low resistance state. Referring to fig. 1, a circuit symbol of the memristor is shown, when a certain forward voltage is input at two ends of the memristor, the memristor is in a high-resistance state, and when the forward voltage disappears, the high-resistance state can be maintained; when a certain reverse voltage is input at two ends of the memristor, the memristor is in a low-resistance state, and when the reverse voltage disappears, the low-resistance state can be kept. Therefore, information storage and logic operation can be realized by utilizing the characteristic of the memristor. In the following discussion, the logic '1' is represented by the high resistance state of the memristor, and the logic '0' is represented by the low resistance state of the memristor, although the opposite convention may be applied in practical circuit applications.
Referring to fig. 2, a schematic diagram of the principle of the memristor read-write method of the present invention is shown, in which at least a write-in unit and a read-out unit are provided and connected in parallel to two ends of the memristor, and in order to make the read-write process more stable, only the write-in unit or the read-out unit can be gated to work at any time. When information is written into the memristor, a writing unit is switched on to form a writing circuit, and the writing unit generates forward voltage or reverse voltage at two ends of the memristor to enable the memristor to be in a high-resistance state or a low-resistance state; that is, when a logic '1' is to be written into the memristor, the writing unit outputs a forward voltage to make the memristor be in a high-resistance state, and similarly, when a logic '0' is to be written into the memristor, the writing unit outputs a reverse voltage to make the memristor be in a low-resistance state.
When the state of the memristor is read, the reading unit is connected to form a reading loop, the reading unit generates an excitation signal at one end of the memristor, and the output state is read at the other end of the memristor, so that the state of the memristor is obtained. That is, when the memristor is in different states (a high resistance state or a low resistance state), an excitation signal is input at one end of the memristor, and an output signal at the other end of the memristor generates different states.
Referring to fig. 3, which is a schematic block diagram illustrating a preferred embodiment of the present invention, the reading unit at least includes a first resistor R1, an excitation module, and a state obtaining module, wherein the excitation module is connected to one end of the memristor and is configured to output a voltage signal to the memristor; the other end of the memristor is connected with one end of a first resistor R1 to serve as a state output end, and the other end of the first resistor R1 is grounded; the state acquisition module is connected with the state output end and used for acquiring the voltage state of the state output end and acquiring the state of the memristor.
In the circuit, a transmission loop is formed among the memristor, the first resistor R1 and the ground, when a voltage signal is input at one end of the memristor, a voltage division is formed between the memristor and the first resistor R1, and the memristor is in a high resistance state or a low resistance state, the voltage value of the first resistor R1 will be different, so that in practice, the voltage value of the point can be sampled through AD, and the state of the memristor can be judged according to the value.
In a preferred embodiment, the first resistance R1 has a resistance value between the memristor high and low resistance states. When the memristor is in a high resistance state, the voltage division value of the first resistor R1 is closer to a logic '0' level, and when the memristor is in a low resistance state, the voltage division value of the first resistor R1 is closer to a logic '1' level, so that two states can be distinguished obviously.
In a preferred embodiment, the memristor has a resistance of 100K Ω in a high-resistance state, a resistance of 100 Ω in a low-resistance state, and a resistance of 1K Ω to 10K Ω of the first resistor R1. Under the circuit parameter, when the memristor is in a high-resistance state, the voltage division value of the first resistor R1 is almost close to a logic '0' level, and when the memristor is in a low-resistance state, the voltage division value of the first resistor R1 is almost close to a logic '1' level, so that the state output can be realized by designing a logic circuit.
In a preferred embodiment, the state obtaining module is implemented by using a comparator, referring to fig. 4, two input ends of the comparator are respectively connected with two ends of a memristor, and an output of the comparator is a state of the memristor. When the memristor is in a high resistance state, the comparator outputs logic '1', and when the memristor is in a low resistance state, the comparator outputs logic '0'. Therefore, the state output of the memristor can be conveniently realized.
In the prior art, the memristor storage research and the logic operation research belong to two relatively independent research directions, and in the application, a logic operation circuit designed based on the memristor is applied to the reading and writing of the memristor.
In a preferred embodiment, the write unit is implemented using MOS logic circuits. Referring to fig. 5, which shows a schematic circuit diagram of the write-in unit, the write-in unit at least includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a fifth MOS transistor M5, wherein the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are NMOS transistors, the fourth MOS transistor M4 and the fifth MOS transistor M5 are PMOS transistors, a gate of the first MOS transistor M1 is connected to a gate of the second MOS transistor M2 and a gate of the fourth MOS transistor M4 to serve as a first control terminal, and a drain of the first MOS transistor M1 is connected to a drain of the second MOS transistor M2 and a drain of the fourth MOS transistor M4; the source electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3 and the drain electrode of the fifth MOS transistor M5; the grid electrode of the third MOS transistor M3 is connected with the grid electrode of the fifth MOS transistor M5 and one end of the memristor to serve as a second control end, and the source electrode of the second MOS transistor M2 is connected with the other end of the memristor; the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 are connected to a power supply terminal, and the source of the third MOS transistor M3 is grounded.
In the circuit, when the first control terminal is at a high level, M1 and M2 are in a conducting state, and M4 is in a cut-off state; when the second control signal is at a low level, M5 is in a conducting state, and M3 is in a blocking state; therefore, when the M1, the M2 and the M5 are in a conducting state, the power supply end VCC is transmitted from the M5, the M1 and the M2 to the output end, a reverse voltage difference is generated at two ends of the memristor, if the previous state of the memristor is a low-resistance state, the low-resistance state is continuously maintained, and if the previous state of the memristor is a high-resistance state, the low-resistance state is changed. In addition, when the second control signal is at a high level, M3 is in an on state, and M5 is in an off state; when M1, M2 and M3 are in a conducting state, a ground signal is transmitted to an output end from M3, M1 and M2, a forward voltage difference exists between two ends of the memristor, if the previous state of the memristor is a high-resistance state, the high-resistance state is continuously maintained, and if the previous state of the memristor is a low-resistance state, the high-resistance state is changed.
From the above analysis, when the first control terminal is at a high level, the writing of the memristor at a high resistance state or a low resistance state can be guaranteed to be executed according to the level state of the second control terminal.
In a preferred embodiment, the write unit is used to simultaneously perform an exclusive-or function, wherein the first control terminal and the second control terminal are used as input terminals, which are denoted as a first input terminal S1 and a second input terminal S2, and the source of the second MOS transistor M2 is connected to the other end of the memristor to be used as the output terminal Vout.
Assuming that the memristor is initially in a low-resistance state, when S1 is equal to 0, M1 and M2 are in a cut-off state, and M4 is in a conducting state.
(1) When S2 is equal to 0, the memristor is in a low resistance state, and since M2 is in an off state, the output terminal is logic 0, and at this time, there is no voltage difference between the two terminals, and the low resistance state is maintained.
(2) When S2 is equal to 1, the memristor is converted into a high resistance state, and since M2 is in an off state, the output terminal is logic 1, and at this time, there is no voltage difference between the two terminals, and the high resistance state is maintained.
When S1 is equal to 1, M1 and M2 are in an on state, and M4 is in an off state.
(1) When S2 is equal to 0, M1, M2, and M5 are in a conducting state, the power source terminal VCC is transmitted from M5, M1, and M2 to the output terminal, and at this time, there is a reverse voltage difference between the two terminals, which keeps a low resistance state, which is equivalent to a small resistance load, and the output terminal is a logic 1.
(2) When S2 is equal to 1, the memristor is converted into a high-resistance state, M1, M2, and M3 are in a conducting state, a ground signal is transmitted from M3, M1, and M2 to the output terminal, at this time, a forward voltage difference exists between the two terminals, the high-resistance state is maintained, which is equivalent to a large-resistance load, and the output terminal is logic 0.
When the memristor is initially in a high-impedance state and S1 is equal to 0, M1 and M2 are in off states.
(1) When S2 is equal to 0, the memristor is in a high resistance state, and since M2 is in an off state, the output end is logic 0, and at this time, there is no voltage difference between the two ends, and the high resistance state is maintained.
(2) When S2 is equal to 1, the memristor is in a high-resistance state, and since M2 is in an off state, the output terminal is logic 1, and at this time, there is no voltage difference between the two terminals, and the high-resistance state is maintained.
When S1 is equal to 1, M1 and M2 are in a conducting state.
(1) When S2 is equal to 0, M1, M2, and M5 are in a conducting state, VCC is transmitted from M5, M1, and M2 to the output terminal, and at this time, a reverse voltage difference exists between the two terminals, which is converted into a low resistance state, which is equivalent to a small resistance load, and the output terminal is a logic 1.
(2) When S2 is equal to 1, the memristor is in a high-impedance state, and M1, M2, and M3 are in an on state.
The ground signal is transmitted from M3, M1, M2 to the output terminal, and at this time, there is a forward voltage difference between the two terminals, and the high impedance state is maintained, which is equivalent to a large resistance load, and the output terminal is logic 0.
From the above analysis, the circuit can perform the following logic regardless of whether the initial state of the memristor is a high-resistance state or a low-resistance state:
(1) when the input signal S1 is equal to 0 and S2 is equal to 0, the output signal V out ＝0；
(2) When the input signal S1 is equal to 0 and S2 is equal to 1, the output signal V is obtained out ＝1；
(3) When the input signal S1 is equal to 1 and S2 is equal to 0, the output signal V is obtained out ＝1；
(1) When the input signal S1 is equal to 1 and S2 is equal to 1, the output signal V is out ＝0。
Thus, the above circuit can be realized
And an exclusive-or logic operation is formed, so that the functional design of the exclusive-or logic circuit is achieved. Meanwhile, when the S1 is equal to 1, the writing of the memristor state can be ensured through the level state of S2, so that the circuit function is greatly enriched, and greater flexibility is brought to the actual circuit design.
In a preferred embodiment, the memristor state is read by the read unit, so that the exclusive-or logic function has a second logic output. Prior art exclusive-or logic circuits are typically only capable of implementation
The logic function of the memory resistor is that the memristor is adopted to construct the XOR gate, although the memristor is in a high resistance state or a low resistance state, the XOR logic function can be achieved, then in the actual circuit design, the same XOR state can be identified into different circuit states by identifying the state of the memristor, and therefore the XOR logic function has second logic output. By utilizing the characteristic of the circuit, a logic circuit with more complex functions can be designed, and the design of an actual circuit is greatly facilitated.
By utilizing the memristor read-write method provided by the invention, a memristor read-write device can be realized, at least a write-in unit and a read unit which are connected in parallel with two ends of the memristor are arranged, the read unit at least comprises a first resistor R1, an excitation module and a state acquisition module, wherein the excitation module is connected with one end of the memristor and is used for outputting a voltage signal to the memristor; the other end of the memristor is connected with one end of a first resistor R1 to serve as a state output end, and the other end of the first resistor R1 is grounded; the state acquisition module is connected with the state output end and used for acquiring the voltage state of the state output end and acquiring the state of the memristor. The writing unit at least comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4 and a fifth MOS tube M5, wherein the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3 are NMOS transistors, the fourth MOS tube M4 and the fifth MOS tube M5 are PMOS transistors, the grid of the first MOS tube M1 is connected with the grid of the second MOS tube M2 and the grid of the fourth MOS tube M4 to serve as a first control end, and the drain of the first MOS tube M1 is connected with the drain of the second MOS tube M2 and the drain of the fourth MOS tube M4; the source electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3 and the drain electrode of the fifth MOS transistor M5; the grid electrode of the third MOS transistor M3 is connected with the grid electrode of the fifth MOS transistor M5 and one end of the memristor to serve as a second control end, and the source electrode of the second MOS transistor M2 is connected with the other end of the memristor; the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5 are connected to a power supply terminal, and the source of the third MOS transistor M3 is grounded. See the above analysis for the specific circuit operating principle.
In addition, by using the memristor read-write method provided by the invention, an exclusive-or logic circuit based on the memristor can be realized, and the circuit at least comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a fifth MOS transistor M5, wherein the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are NMOS transistors, the fourth MOS transistor M4 and the fifth MOS transistor M5 are PMOS transistors, the gate of the first MOS transistor M1 is connected with the gate of the second MOS transistor M2 and the gate of the fourth MOS transistor M4 to serve as a first control end, and the drain of the first MOS transistor M1 is connected with the drain of the second MOS transistor M2 and the drain of the fourth MOS transistor M4; the source electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3 and the drain electrode of the fifth MOS transistor M5; the grid electrode of the third MOS transistor M3 is connected with the grid electrode of the fifth MOS transistor M5 and one end of the memristor to serve as a second control end, and the source electrode of the second MOS transistor M2 is connected with the other end of the memristor; the source electrode of the fourth MOS transistor M4 and the source electrode of the fifth MOS transistor M5 are connected with a power supply end, and the source electrode of the third MOS transistor M3 is grounded; the first control end and the second control end are used as input ends, and the source electrode of the second MOS transistor M2 is connected with the other end of the memristor to be used as an output end. The circuit can realize the function of the exclusive-or logic no matter the memristor is in a high-resistance state or a low-resistance state, and the exclusive-or gate circuit is constructed by adopting the memristor, and the memristor can be in different states under the same exclusive-or logic, so that the exclusive-or logic can have second logic output by reading the state of the memristor, namely, the same exclusive-or logic can be identified into different circuit modes, and the expansion of the function of the actual circuit is greatly enriched.
Reading of the state of the memristor is realized through a reading unit, referring to fig. 3, the reading unit at least comprises a first resistor R1, an excitation module and a state acquisition module, wherein the excitation module is connected with one end of the memristor and is used for outputting a voltage signal to the memristor; the other end of the memristor is connected with one end of a first resistor R1 to serve as a state output end, and the other end of the first resistor R1 is grounded; the state acquisition module is connected with the state output end and used for acquiring the voltage state of the state output end and acquiring the state of the memristor.
In the circuit, a transmission loop is formed among the memristor, the first resistor R1 and the ground, when a voltage signal is input at one end of the memristor, a voltage division is formed between the memristor and the first resistor R1, and the memristor is in a high resistance state or a low resistance state, the voltage value of the first resistor R1 will be different, so that in practice, the voltage value of the point can be sampled through AD, and the state of the memristor can be judged according to the value.
In a preferred embodiment, the first resistor R1 has a resistance value between the memristor high resistance state and the low resistance state. When the memristor is in a high resistance state, the voltage division value of the first resistor R1 is closer to a logic '0' level, and when the memristor is in a low resistance state, the voltage division value of the first resistor R1 is closer to a logic '1' level, so that two states can be distinguished obviously.
In a preferred embodiment, the memristor has a resistance of 100K Ω in a high-resistance state, and a resistance of 100 Ω in a low-resistance state, and the first resistor R1 has a resistance of 1K Ω to 10K Ω. Under the circuit parameter, when the memristor is in a high-resistance state, the voltage division value of the first resistor R1 is almost close to a logic '0' level, and when the memristor is in a low-resistance state, the voltage division value of the first resistor R1 is almost close to a logic '1' level, so that the state output can be realized by designing a logic circuit.
In a preferred embodiment, the state obtaining module is implemented by using a comparator, referring to fig. 4, two input ends of the comparator are respectively connected with two ends of a memristor, and an output of the comparator is a state of the memristor. When the memristor is in a high resistance state, the comparator outputs logic '1', and when the memristor is in a low resistance state, the comparator outputs logic '0'. Therefore, the state output of the memristor can be conveniently realized.
The above description of the embodiments is only intended to facilitate the understanding of the method of the invention and its core idea. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it is possible to make various improvements and modifications to the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A memristor read-write method is characterized in that at least a write-in unit and a read-out unit are arranged, wherein when information is written into a memristor, the write-in unit is switched on to form a write-in loop, the write-in unit generates forward voltage at two ends of the memristor to enable the memristor to be in a high resistance state, or the write-in unit generates reverse voltage at two ends of the memristor to enable the memristor to be in a low resistance state;
when the state of the memristor is read, a reading unit is switched on to form a reading circuit, the reading unit generates an excitation signal at one end of the memristor, and reads an output state at the other end of the memristor so as to acquire the state of the memristor;
the write-in unit is realized by adopting an MOS logic circuit and at least comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a fifth MOS transistor M5, wherein the first MOS transistor M1, the second MOS transistor M2 and the third MOS transistor M3 are NMOS transistors, the fourth MOS transistor M4 and the fifth MOS transistor M5 are PMOS transistors, the grid of the first MOS transistor M1 is connected with the grid of the second MOS transistor M2 and the grid of the fourth MOS transistor M4 to serve as a first control end, and the drain of the first MOS transistor M1 is connected with the drain of the second MOS transistor M2 and the drain of the fourth MOS transistor M4; the source electrode of the first MOS transistor M1 is connected with the drain electrode of the third MOS transistor M3 and the drain electrode of the fifth MOS transistor M5; the grid electrode of the third MOS transistor M3 is connected with the grid electrode of the fifth MOS transistor M5 and one end of the memristor to serve as a second control end, and the source electrode of the second MOS transistor M2 is connected with the other end of the memristor; the source electrode of the fourth MOS transistor M4 and the source electrode of the fifth MOS transistor M5 are connected with a power supply end, and the source electrode of the third MOS transistor M3 is grounded;
performing an exclusive-or logic function by using a write-in unit, wherein a first control end and a second control end are used as input ends, and a source electrode of a second MOS transistor M2 is connected with the other end of the memristor to be used as an output end;
and reading the memristor state through the reading unit to enable the exclusive-OR logic function to have a second logic output.
2. The memristor read-write method according to claim 1, wherein the read unit at least comprises a first resistor R1, an excitation module and a state acquisition module, wherein the excitation module is connected with one end of the memristor and is used for outputting a voltage signal to the memristor; the other end of the memristor is connected with one end of a first resistor R1 to serve as a state output end, and the other end of the first resistor R1 is grounded; the state acquisition module is connected with the state output end and used for acquiring the voltage state of the state output end and acquiring the state of the memristor.
3. The memristor read-write method according to claim 2, wherein the state obtaining module is implemented by using a comparator, two input ends of the comparator are respectively connected with two ends of the memristor, and an output of the comparator is a state of the memristor.
4. The memristor read-write method according to claim 3, wherein the resistance of the first resistor R1 is between the high resistance state and the low resistance state of the memristor.
5. The memristor read-write method according to claim 4, wherein the resistance of the memristor is 100K Ω in a high resistance state, 100 Ω in a low resistance state, and 1K Ω to 10K Ω in the first resistor R1.
6. The memristor read-write method according to claim 1, wherein when the first control terminal is at a high level, writing of a high resistance state or a low resistance state of the memristor is performed according to a level state of the second control terminal.
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| CN202110495859.4A CN113314178B (en) | 2021-05-07 | 2021-05-07 | Memristor reading and writing method |
| CN202210954506.0A CN115440277A (en) | 2021-05-07 | 2021-05-07 | Memristor-based XOR logic circuit |
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| CN102723112B (en) * | 2012-06-08 | 2015-06-17 | 西南大学 | Q learning system based on memristor intersection array |
| WO2016085470A1 (en) * | 2014-11-25 | 2016-06-02 | Hewlett-Packard Development Company, L.P. | Bi-polar memristor |
| CN105118528B (en) * | 2015-07-14 | 2017-11-24 | 江苏时代全芯存储科技有限公司 | Non-volatile memory unit, programmable circuit and content addressable memory |
| CN105825885B (en) * | 2016-03-21 | 2018-04-10 | 华中科技大学 | Multilevel memory cell, read/write circuit and its operating method based on memristor |
| CN106920568B (en) * | 2017-03-10 | 2019-10-08 | 东南大学 | A kind of read/write circuit of four values memristor |
| CN107545922B (en) * | 2017-09-12 | 2020-07-14 | 中国联合网络通信集团有限公司 | Content address storage unit circuit, write operation method thereof and memory |
| CN108092658B (en) * | 2017-12-12 | 2020-05-19 | 华中科技大学 | Logic circuit operation method |
| CN112164412A (en) * | 2020-09-03 | 2021-01-01 | 杭州电子科技大学 | Multi-bit memristor based on multi-scale magnetic tunnel junction |
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