CN106997780B - Sense amplifier - Google Patents
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- CN106997780B CN106997780B CN201710031420.XA CN201710031420A CN106997780B CN 106997780 B CN106997780 B CN 106997780B CN 201710031420 A CN201710031420 A CN 201710031420A CN 106997780 B CN106997780 B CN 106997780B
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1695—Protection circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1693—Timing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0057—Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value
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- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/74—Array wherein each memory cell has more than one access device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
Abstract
In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first phase and a second phase. During the first phase, the NV element is coupled to a first capacitive element at a first input of an amplifier stage via a sense path transistor and a reference cell is coupled to a second capacitive element at a second input of the amplifier stage via a reference sense path transistor. During the second phase, the NV element is coupled to the second capacitive element via the sense path transistor and the reference cell is coupled to the first capacitive element via the reference sense path transistor. During the first phase, the first and second capacitive elements are initialized to voltages representing states of the NV element and a reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified.
Description
Technical Field
The present invention relates generally to integrated circuit memories, and more particularly to sense amplifiers that may be used in integrated circuit memories.
Background
Integrated circuit memory, including non-volatile memory (NVM), has become extremely important in a variety of applications. Some NVMs are not only non-volatile, but also operate at speeds close to those of random access memories. Some of the resistive NVMs, e.g., Magnetic Tunnel Junctions (MTJs), have this characteristic. Some of these resistive NVMs have other difficulties, such as read disturbs that can write memory cells during read operations. Voltage and current can be greatly limited by read disturb issues, especially where current is required to pass through the NVM cell being sensed in order to effectively perform a read. In these cases, the current must be low enough to avoid read disturb, while large enough to create a reliably detectable differential between the programmed and erased states.
Accordingly, there is a need to provide additional improvements in obtaining NVRAM.
Disclosure of Invention
According to one aspect of the present invention, there is provided a non-volatile memory (NVM) circuit comprising: a non-volatile (NV) element coupled to a first current electrode of a force path transistor and a first current electrode of a sense path transistor, wherein a second current electrode of the force path transistor is coupled to a first force node and a second current electrode of the sense path transistor is coupled to a first sense node; a reference cell coupled to a first current electrode of a reference forced path transistor and a first current electrode of a reference sense path transistor, wherein a second current electrode of the reference forced path transistor is coupled to a second forced node and a second current electrode of the reference sense path transistor is coupled to a second sense node; a first capacitive element having a first electrode and having a second electrode coupled to a first input of an amplifier stage; and a second capacitive element having a first electrode and having a second electrode coupled to the second input of the amplifier stage, wherein the NVM circuit is configured to: during a first phase of a sensing operation, coupling the first sensing node to a first electrode of the first capacitive element and the second sensing node to a first electrode of the second capacitive element; and during a second phase of the sensing operation, coupling the first sensing node to a first electrode of the second capacitive element and coupling the second sensing node to a first electrode of the first capacitive element.
Optionally, the first stage is configured to initialize the first current electrode of the first capacitive element to a voltage representing a memory state of the NV element and the first current electrode of the second capacitive element to a reference voltage representing a reference state of the reference cell.
Optionally, the second stage is configured to amplify a voltage differential between the voltage representing the memory state and the reference voltage representing the reference state.
Optionally, the NVM circuit is configured such that sensing by the amplifier stage is commenced for the sensing operation prior to commencement of the second phase.
Optionally, the NVM circuit additionally includes: a first current source; and a second current source, wherein the NVM circuit is configured to: during the first phase, coupling the first current source to the first force node and the second current source to the second force node.
Optionally, the NVM circuit is configured to: during the second phase, coupling the first current source to the second force node and coupling the second current source to the first force node.
Optionally, during the second phase, the NVM circuit is configured to reduce a difference in the first current source and the second current source.
Optionally, the NV element comprises a first resistive element.
Optionally, the first resistive element is characterized as a Magnetic Tunnel Junction (MTJ).
Optionally, the reference cell comprises a second resistive element having a resistance between a high resistance state and a low resistance state of the first resistive element.
According to a second aspect of the present invention, there is provided in an NVM, a method of performing a sensing operation to read NV elements, comprising: during a first phase, coupling the NV element to a first capacitive element at a first input of an amplifier stage via a sense path transistor and coupling a reference cell to a second capacitive element at a second input of the amplifier stage via a reference sense path transistor; and during a second phase, after the first phase, coupling the NV element to the second capacitive element via the sense path transistor and coupling the reference cell to the first capacitive element via the reference sense path transistor.
Optionally, the method additionally comprises: during the first phase, providing a first current to the NV element via a force path transistor and a second current to the reference cell via a reference force path transistor; and during the second phase, providing the first current to the reference cell via the reference force path transistor and providing the second current to the NV element via the force path transistor.
Optionally, sensing by the amplifier stage is enabled prior to the start of the second stage.
Optionally, the method additionally includes outputting a logic state responsive to the NV element enabled to be sensed by the amplifier stage.
Optionally, during the first phase, the first capacitive element is initialized to a voltage representing a memory state of the NV element and the second capacitive element is initialized to a reference voltage representing a reference state of the reference cell.
Optionally, during the second phase, the voltage differential between the voltage representing the memory state and the reference voltage representing the reference state is amplified.
Optionally, the NV element is characterized as a Magnetic Tunnel Junction (MTJ).
According to another aspect of the present invention, there is provided an NVM circuit comprising: a non-volatile (NV) element; a first transistor coupled between the NV element and a first sense node; a reference unit; a second transistor coupled between the reference cell and a second sensing node; a first switch coupled between the first sensing node and a first capacitive element at a first input of an amplifier stage; a second switch coupled between the second sensing node and a second capacitive element at a second input of the amplifier stage; a third switch coupled between the first sensing node and the second capacitive element; and a fourth switch coupled between the second sensing node and the first capacitive element, wherein: the first and second switches are configured to: during a first phase of a sensing operation, coupling the first sensing node to the first capacitive element and the second sensing node to the second capacitive element, and the third and fourth switches are configured to: during a second phase of the sensing operation, the first sensing node is coupled to the second capacitive element and the second sensing node is coupled to the first capacitive element.
Optionally, the NVM circuit additionally includes: a third transistor coupled between the NV element and a first forced node; a fourth transistor coupled between the reference cell and a second force node; a first current source; a second current source; a fifth switch coupled between the third transistor and the first current source; a sixth switch coupled between the fourth transistor and the second current source; a seventh switch coupled between the first current source and the fourth transistor; and an eighth switch coupled between the second current source and the third transistor, wherein: the fifth and sixth switches are configured to: during the first phase, coupling the first current source to the third transistor and the second current source to the fourth transistor, and the seventh and eighth switches are configured to: during the second phase, the first current source is coupled to the fourth transistor and the second current source is coupled to the third transistor.
Optionally, the NVM circuit is configured such that sensing by the amplifier stage is commenced for the sensing operation prior to commencement of the second phase.
Drawings
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Shown in FIG. 1 is a circuit diagram of a sense amplifier suitable for use in a memory, and particularly suitable for NVM using MTJ; and is
Illustrated in fig. 2 is a timing diagram useful in understanding the operation of the sense amplifier of fig. 1.
Detailed Description
In one aspect, a sense amplifier provides a first differential signal to a sense amplifier on a differential pair during a first phase and then increases the differential during a second phase by inverting the input to the sense amplifier. This is better understood by reference to the drawings and the written description that follows.
Shown in fig. 1 is a non-volatile memory (NVM) circuit 10 having NVM cells 11 and sense amplifiers 17. The NVM cell 11 has an NV element 12 that can be a Magnetic Tunnel Junction (MTJ), a transistor 14, and a transistor 16. The NV element 12 has a first terminal and a second terminal connected to a negative power supply terminal that may be connected to ground. Transistor 14 has a first current electrode connected to the second terminal of NVM element 12, a control electrode connected to word line WL, and a second current electrode. Transistor 16 has a first current electrode connected to the first current electrode of transistor 14 and the second terminal of NV element 12, a control electrode connected to word line WL, and a second current electrode. Sense amplifier 17 has transistor 18, transistor 20, current source 22, transistor 24, capacitor 26, transistor 28, inverting amplifier 30, latch 32, reference cell 34, transistor 36, transistor 38, transistor 40, current source 42, transistor 44, capacitor 50, transistor 52, and inverting amplifier 54.
The reference cell 34 is designed to have a half-way resistance (half way) between the high-resistance state and the low-resistance state of the NV element (e.g., NV element 12). This may be achieved by a first pair of NV elements connected in series with opposite resistances connected in parallel with a second pair of NV elements connected in series with opposite resistances.
Shown in fig. 2 is a timing diagram showing reading of NV elements 12 starting at time t0 and ending at time t6 which causes latch 32 to provide output DO in response to latch signal LT at time t 4. Immediately prior to time t0, word line WL, reference enable signal RE, first phase signal P1, and second phase signal P2 are logic low, such that transistors 14, 16, 18, 20, 24, 36, 38, 40, 43, 44, 46, and 48 are non-conductive; latch signal LT is logic low so that latch 32 is disabled and output signal D0 is not active; and the sense signal S is a logic high so that transistors 28 and 52 are conductive but sensing does not occur in this condition. Under this condition, inverting amplifiers 30 and 54 have their inputs coupled to their outputs such that inverting amplifiers 30 and 54 are at their trip points of indeterminate states between logic high and logic low.
At time t0, the word line WL and the reference enable signal are switched to logic high, which causes transistors 14, 16, 36 and 38 to become conductive. The second current electrodes of transistors 18 and 24 are thus coupled to NV element 12, and the second current electrodes of transistors 40 and 44 are coupled to reference cell 34. This is the start of a read operation.
At time t1, the first phase signal P1 is switched to logic high, which causes transistors 18, 24, 40, and 44 to become conductive and result in switching to the first phase. At the beginning of the first phase, current from the current source 22 then flows through transistors 18 and 14 and NV element 12, which has the effect of representing the voltage of the logic state of the NV element coupled to the first terminal of capacitor 26 through transistors 16 and 24. Similarly, current from current source 42 flows through transistors 40 and 38 and reference 34, which has the effect of providing a reference voltage to the first terminal of capacitor 50, where the reference voltage is about half the voltage provided by the NV element programmed to logic high and the NV element programmed to logic low. Assuming that the high-resistance NV element 12 is a logic high and the low-resistance is a logic low, a voltage on the first terminal of capacitor 26 that is higher than the voltage on the first terminal of capacitor 50 indicates that the NV element 12 has been programmed to a logic high. If the voltage on the second terminal of capacitor 26 is lower than the voltage on the second terminal of capacitor 50, then NV element 12 will be programmed to logic low. Since transistors 28 and 52 couple the inputs to the outputs, the inputs of inverting amplifiers 30 and 54 are not affected at this time. For this example where NV element 12 is logic low, the first terminal of capacitor 26 will have a voltage difference of V1+ within the reference voltage at the first terminal of capacitor 50.
At time t2 (very close in time to time t3), sense signal S is switched to logic low so that transistors 28 and 52 are non-conductive, which has the effect that inverting amplifiers 30 and 54 no longer couple their outputs back to their inputs so that the inverting amplifiers become sensitive to changes on the first terminals of capacitors 26 and 54.
At time t3, the first phase signal P1 is switched to logic low and the second phase signal P2 is switched to logic high so that transistors 18, 24, 40, and 44 become non-conductive and transistors 20, 43, 46, and 48 become conductive, which begins switching from the first phase to the second phase. With transistor 43 conductive and transistor 18 non-conductive, current from current source 42 passes through NV element 12. Although the current sources 22 and 42 are designed to be identical, in practice they do not supply the same current. The current differential results in a deviation from the desired relationship between the reference voltage and the voltage provided from the NV element being read. Switching the current source between the reference cell and the NV element being read reduces this unwanted deviation from the desired relationship. With transistor 24 non-conductive and transistor 46 conductive, the voltage generated by the current through NV element 12 is coupled to a first terminal of capacitor 50. Similarly, with transistor 44 non-conducting and transistor 48 conducting, the voltage generated by reference cell 34 is coupled to the first terminal of capacitor 26. Inverting amplifiers 30 and 54 are now actively sensing. In the case of the inverting amplifier 30, there is a change from the voltage difference V1+ to the reference voltage, which is a negative voltage change, through capacitive coupling of the capacitor 26, which reduces the input of the inverting amplifier 30 below the switching point. In the case of inverting amplifier 54 (which has similar operation), the voltage on the first terminal of capacitor 50 goes from the reference voltage (which is now generated by the current from current source 22 through reference cell 34) to the voltage generated by NV element 12 which is a logic high. As the current sources 22 and 42 are switched, the reference voltage and logic high voltage regions will have a similar differential to the voltage difference V1+ generated by the logic high period first phase signal P1. In the case of inverting amplifier 30, inverting amplifier 30 provides a logic high output due to the voltage drop at the first terminal of capacitor 26 after inverting amplifier 30 becomes active. In the case of inverting amplifier 54, inverting amplifier 54 provides a logic low output due to the voltage drop at the first terminal of capacitor 50 after inverting amplifier 54 becomes active.
At time t4, latch signal LT is switched to logic high so that latch 32 reacts to the logic state that caused latch 32 to provide output signal D0 as a logic high at its input. The output of latch 32 is then an output representing the logic state of NV element 12.
At time t5, the second phase signal P2 is switched to logic low and the sense signal S is switched to logic high. At time t5, circuit 10 is then returned to its state in its prior to time t0, except for latch 32.
At time t6, latch signal LT is returned to logic low and latch 32 is then also in its condition prior to time t 0. Returning the latch signal LT to logic low results in the output signal D0 not being latched and may not provide valid data.
In the case where the NV element 12 is programmed to a logic low, the low resistance of the NV element 12 will result in a voltage below the reference voltage on the first terminal of the capacitor 26 that can be considered as voltage V1 (below the reference voltage). Subsequent re-steering of the current source, voltage from the reference cell, and voltage from the NV element will result in a decrease in the voltage on the input of inverting amplifier 30 causing a logic low output and an increase in the voltage on the input of inverting amplifier 54 causing a logic high output. When the latch signal LT is switched to logic high, the latch 32 will provide a logic low output indicating a logic low condition of the NV element 12.
By having a true differential, not only comparing the signal to a reference, increasing the difference between the input signals for a given cell current, the given cell current is desirably low since read disturbs need to be avoided with a high degree of certainty. Thus, differentially doubling the sensed voltage allows a lower current to be used to generate the voltage used in sensing. Reducing the risk of current increase read disturb. The current supplied to the sensed NV element may take into account the forcing current due to the voltage it is used to force sensing. Forcing current through the transistor 14 with the first-phase signal P1 applied as a logic high to the transistor 14 may treat the transistor 14 as a force-path transistor because it provides a current path that causes the force NV element 12 to generate a voltage relative to its logic state. The current reaches the second current electrode of transistor 14 through a force node (force node) that receives current from either current source 22 or current source 42. The transistor 16 couples this voltage out of the NV element 12 relative to its logic state for purposes of sensing the sense node. Transistor 24 or transistor 46 couples the sense node to the selected capacitive element (capacitor 26 or capacitor 50, respectively). Thus, transistor 16 may be considered a sense path transistor. A similar current for reference (reference cell 34) passes through transistor 38 and may be referenced as a reference current passing through a reference force path transistor 38 coupled to a reference force path. Similar to transistor 16, transistor 36 may be referred to as a reference sense path transistor coupled to a reference sense node. The first stage establishes a voltage differential that increases to about twice in the second stage.
It should now be appreciated that the non-volatile memory (NVM) circuits disclosed herein have a non-volatile (NV) element coupled to a first current electrode of a force path transistor and to a first current electrode of a sense path transistor, wherein a second current electrode of the force path transistor is coupled to a first force node and a second current electrode of the sense path transistor is coupled to a first sense node. The NVM circuit additionally includes a reference cell coupled to a first current electrode of a reference force path transistor and to a first current electrode of a reference sense path transistor, wherein a second current electrode of the reference force path transistor is coupled to a second force node and a second current electrode of the reference sense path transistor is coupled to a second sense node. The NVM circuit additionally includes a first capacitive element having a first electrode and having a second electrode coupled to the first input of the amplifier stage. The NVM circuit additionally includes a second capacitive element having a first electrode and having a second electrode coupled to the second input of the amplifier stage. The NVM circuit is characterized in that the NVM circuit is configured to: during a first phase of a sensing operation, coupling a first sensing node to a first electrode of a first capacitive element and a second sensing node to a first electrode of a second capacitive element; and during a second phase of the sensing operation, coupling the first sensing node to the first electrode of the second capacitive element and coupling the second sensing node to the first electrode of the first capacitive element. The NVM circuit may have further features, the features being: the first stage is configured to initialize a first current electrode of the first capacitive element to a voltage representing a memory state of the NV element and a first current electrode of the second capacitive element to a reference voltage representing a reference state of the reference cell. The NVM circuit may have further features, the features being: the second stage is configured to amplify a voltage differential between a voltage representing the memory state and a reference voltage representing the reference state. The NVM circuit may have further features, the features being: the NVM circuit is configured such that sensing through the amplifier stage is commenced for a sensing operation prior to commencement of the second phase. The NVM circuit can additionally include a first current source and a second current source, wherein the NVM circuit is configured to: during a first phase, a first current source is coupled to a first force node and a second current source is coupled to a second force node. The NVM circuit may have further features, the features being: the NVM circuit is configured to couple the first current source to the second force node and the second current source to the first force node during the second phase. The NVM circuit may have further features, the features being: the NVM circuit is configured to reduce a difference in the first current source and the second current source during the second phase. The NVM circuit may have further features, the features being: the NV element includes a first resistive element. The NVM circuit may have further features, the features being: the first resistive element is characterized as a Magnetic Tunnel Junction (MTJ). The NVM circuit may have further features, the features being: the reference cell includes a second resistive element having a resistance between a high resistance state and a low resistance state of the first resistive element.
Also disclosed is a method of performing a sensing operation in an NVM to read NV elements, the method comprising: during the first phase, the NV element is coupled to a first capacitive element at a first input of the amplifier stage via a sense path transistor and the reference cell is coupled to a second capacitive element at a second input of the amplifier stage via a reference sense path transistor. The method further comprises the following steps: during a second phase after the first phase, the NV element is coupled to the second capacitive element via a sense path transistor and the reference cell is coupled to the first capacitive element via a reference sense path transistor. The method may additionally include: during a first phase, a first current is provided to the NV element via the force path transistor and a second current is provided to the reference cell via the reference force path transistor, and during a second phase, the first current is provided to the reference cell via the reference force path transistor and the second current is provided to the NV element via the force path transistor. The method may have additional features, the features being: enabling sensing through the amplifier stage before the start of the second stage. The method may additionally include outputting a logic state responsive to the NV element enabled to be sensed by the amplifier stage. The method may have additional features, the features being: a first capacitive element is initialized to a voltage representing a memory state of the NV element and a second capacitive element is initialized to a reference voltage representing a reference state of a reference cell during a first phase. The method may have additional features, the features being: a voltage differential between a voltage representing the memory state and a reference voltage representing the reference state is amplified during the second phase. The method may have additional features, the features being: the NV element is characterized as a Magnetic Tunnel Junction (MTJ).
NVM circuits including non-volatile (NV) elements are also disclosed. The NVM circuit additionally includes a first transistor coupled between the NV element and a first sense node. The NVM circuit additionally includes a reference cell. The NVM circuit additionally includes a second transistor coupled between the reference cell and a second sensing node. The NVM circuit additionally includes a first switch coupled between the first sensing node and a first capacitive element at a first input of the amplifier stage. The NVM circuit additionally includes a second switch coupled between the second sensing node and a second capacitive element at the second input of the amplifier stage. The NVM circuit additionally includes a third switch coupled between the first sensing node and the second capacitive element. The NVM circuit additionally includes a fourth switch coupled between the second sensing node and the first capacitive element. The NVM circuit has further features that are characterized by: the first and second switches are configured to couple the first sensing node to the first capacitive element and the second sensing node to the second capacitive element during a first phase of the sensing operation and the third and fourth switches are configured to couple the first sensing node to the second capacitive element and the second sensing node to the first capacitive element during a second phase of the sensing operation. The NVM circuit can additionally include: a third transistor coupled between the NV element and the first force node; a fourth transistor coupled between the reference cell and the second force node; a first current source; a second current source; a fifth switch coupled between the third transistor and the first current source; a sixth switch coupled between the fourth transistor and the second current source; a seventh switch coupled between the first current source and the fourth transistor; and an eighth switch coupled between the second current source and the third transistor; wherein the fifth and sixth switches are configured to couple the first current source to the third transistor and the second current source to the fourth transistor during the first phase, and the seventh and eighth switches are configured to couple the first current source to the fourth transistor and the second current source to the third transistor during the second phase. The NVM circuit may have further features, the features being: the NVM circuit is configured such that sensing through the amplifier stage is commenced for a sensing operation prior to commencement of the second phase.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the supply voltages coupled to the NV elements may be different voltages, and one or more of the transistors may be of different types. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Any advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.
Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Furthermore, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an". The same holds true for the use of definite articles.
Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Claims (7)
1. A non-volatile memory (NVM) circuit, comprising:
a non-volatile (NV) element coupled to a first current electrode of a force path transistor and a first current electrode of a sense path transistor, wherein a second current electrode of the force path transistor is coupled to a first force node and a second current electrode of the sense path transistor is coupled to a first sense node;
a reference cell coupled to a first current electrode of a reference forced path transistor and a first current electrode of a reference sense path transistor, wherein a second current electrode of the reference forced path transistor is coupled to a second forced node and a second current electrode of the reference sense path transistor is coupled to a second sense node;
a first capacitive element having a first electrode and having a second electrode coupled to a first input of an amplifier stage; and
a second capacitive element having a first electrode and having a second electrode coupled to a second input of the amplifier stage,
wherein the NVM circuitry is configured to: during a first phase of a sensing operation, coupling the first sensing node to a first electrode of the first capacitive element and the second sensing node to a first electrode of the second capacitive element; and during a second phase of the sensing operation, coupling the first sensing node to a first electrode of the second capacitive element and the second sensing node to a first electrode of the first capacitive element,
wherein the NVM circuitry is further configured to include a first current source; and
a second current source, wherein the NVM circuitry is configured to: coupling the first current source to the first force node and the second current source to the second force node during the first phase, and coupling the first current source to the second force node and the second current source to the first force node during the second phase.
2. The NVM circuit of claim 1 wherein the first stage is configured to initialize the first current electrode of the first capacitive element to a voltage representing a memory state of the NV element and the first current electrode of the second capacitive element to a reference voltage representing a reference state of the reference cell.
3. The NVM circuit of claim 2 wherein the second stage is configured to amplify a voltage differential between the voltage representing the memory state and the reference voltage representing the reference state.
4. The NVM circuit of claim 3, wherein the NVM circuit is configured such that sensing by the amplifier stage begins for the sensing operation prior to a beginning of the second phase.
5. The NVM circuit according to any of the preceding claims wherein during the second phase, the NVM circuit is configured to reduce the difference in the first current source and the second current source.
6. The NVM circuit of claim 1 wherein the NV element comprises a first resistive element.
7. An NVM circuit, comprising:
a non-volatile (NV) element;
a first transistor coupled between the NV element and a first sense node;
a reference unit;
a second transistor coupled between the reference cell and a second sensing node;
a first switch coupled between the first sensing node and a first capacitive element at a first input of an amplifier stage;
a second switch coupled between the second sensing node and a second capacitive element at a second input of the amplifier stage;
a third switch coupled between the first sensing node and the second capacitive element; and
a fourth switch coupled between the second sensing node and the first capacitive element, wherein:
the first and second switches are configured to: during a first phase of a sensing operation, the first sensing node is coupled to the first capacitive element and the second sensing node is coupled to the second capacitive element, and
the third and fourth switches are configured to: coupling the first sensing node to the second capacitive element and the second sensing node to the first capacitive element during a second phase of the sensing operation;
the NVM circuit additionally includes: a third transistor coupled between the NV element and a first forced node; a fourth transistor coupled between the reference cell and a second force node; a first current source; a second current source; a fifth switch coupled between the third transistor and the first current source; a sixth switch coupled between the fourth transistor and the second current source; a seventh switch coupled between the first current source and the fourth transistor; and an eighth switch coupled between the second current source and the third transistor, wherein: the fifth and sixth switches are configured to: during the first phase, coupling the first current source to the third transistor and the second current source to the fourth transistor, and the seventh and eighth switches are configured to: during the second phase, the first current source is coupled to the fourth transistor and the second current source is coupled to the third transistor.
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| US15/003,922 US9659622B1 (en) | 2016-01-22 | 2016-01-22 | Sense amplifier |
| US15/003922 | 2016-01-22 |
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| US9773537B2 (en) | 2015-10-27 | 2017-09-26 | Nxp Usa, Inc. | Sense path circuitry suitable for magnetic tunnel junction memories |
| JP2017162535A (en) * | 2016-03-11 | 2017-09-14 | ソニー株式会社 | Storage device, information processor, and control method for storage device |
| US10121522B1 (en) * | 2017-06-22 | 2018-11-06 | Sandisk Technologies Llc | Sense circuit with two sense nodes for cascade sensing |
| US10984846B2 (en) * | 2019-07-10 | 2021-04-20 | Nxp Usa, Inc. | Reference generation for voltage sensing in a resistive memory |
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| CN105264607A (en) * | 2013-03-15 | 2016-01-20 | 高通股份有限公司 | Reading a memory cell using a reference cell and a common sensing path |
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| US9659622B1 (en) | 2017-05-23 |
| CN106997780A (en) | 2017-08-01 |
| EP3200191A1 (en) | 2017-08-02 |
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| US9767877B2 (en) | 2017-09-19 |
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