CN105590647B

CN105590647B - Non-volatile static random access memory circuit

Info

Publication number: CN105590647B
Application number: CN201410647788.5A
Authority: CN
Inventors: 金宁泰; 谢明辉
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2014-11-13
Filing date: 2014-11-13
Publication date: 2020-02-28
Anticipated expiration: 2034-11-13
Also published as: CN105590647A

Abstract

The invention provides a nonvolatile static random access memory circuit, which comprises a first switch, a second switch and a latch circuit. The first switch has a first end coupled to the first bit line and a second end. The second switch has a first end coupled to the second bit line and a second end. The latch circuit is coupled to the second end of the first switch and the second end of the second switch, and has a first nonvolatile memory element. When the nonvolatile static random access memory circuit is in a write mode, first data on the first bit line is written into the latch circuit, and the first nonvolatile memory cell has a first state corresponding to the first data. When the non-volatile static random access memory circuit is in a read mode, first read data is generated according to a first state of a first non-volatile memory cell and provided to a first bit line. According to the embodiment of the invention, the data on the bit line is recorded in the latch circuit through the stroke of the impedance state of the nonvolatile memory element, and the conventional mode is not needed.

Description

Non-volatile static random access memory circuit

Technical Field

The present invention relates to a non-volatile static random access memory circuit, and more particularly, to a non-volatile static random access memory circuit without an access mode and a recall mode.

Background

Semiconductor memory devices are widely used in computers or other electronic products to store digital information. A typical semiconductor memory device has a large number of memory elements, known as memory cells, which are capable of storing a single digital bit or data bit. Among various semiconductor memory devices, a nonvolatile static random access memory has a high access speed. In addition, when the power supply of the nonvolatile static random access memory is closed, the pre-stored data can not be lost. Therefore, in the power-off state or the standby mode, the power supply of the nonvolatile static random access memory can be completely cut off without worrying about the problem of data storage, thereby reducing power consumption.

Generally, before a conventional non-volatile sram enters a power-off state or a standby mode, the non-volatile sram must be operated in a storage mode to store data from the latch to the non-volatile storage element. After the power supply of the non-volatile sram is turned on, the non-volatile sram must operate in a recall mode to recall data from the non-volatile memory device to the latch. However, the occurrence of the store mode and the recall mode described above results in additional timing.

Disclosure of Invention

Accordingly, the present invention provides a non-volatile sram that does not need to operate in a storage mode or a recall mode when it is in a power-off state or a standby mode.

The invention provides a nonvolatile static random access memory circuit which comprises a first switch, a second switch and a latch circuit. The first switch has a first terminal coupled to the first bit line and a second terminal. The second switch has a first terminal coupled to the second bit line and a second terminal. The latch circuit is coupled to the second end of the first switch and the second end of the second switch, and has a first nonvolatile memory element. When the nonvolatile static random access memory circuit is in a write mode, first data on the first bit line is written into the latch circuit, and the first nonvolatile storage element has a first state corresponding to the first data. When the non-volatile static random access memory circuit is in a read mode, first read data is generated according to a first state of a first non-volatile storage element and provided to a first bit line.

In the write mode, the first switch and the second switch are turned on. In the reading mode, the first switch and the second switch are conducted. In another embodiment, between the write mode and the read mode, no supply voltage powers the non-volatile static random access memory circuit, or the non-volatile static random access memory circuit is in a standby mode.

The non-volatile static random access memory circuit also includes a write control circuit. The write control circuit is coupled to the latch circuit and receives a write select signal to control the latch circuit. In a write mode, the write select signal is at a first voltage level to control the latch circuit to change the first non-volatile storage element to a first state. In the read mode, the write select signal is at a second voltage level to control the latch circuit to generate the first read signal according to the first state.

In one embodiment, a latch circuit of a non-volatile static random access memory circuit includes a first type transistor, a first second type transistor, a second type transistor, a second first type transistor, a third second type transistor, and a fourth second transistor. The first type transistor has a control terminal coupled to the first node, an input terminal, and an output terminal coupled to the second node. The first second-type transistor has a control terminal coupled to the third node, an input terminal coupled to the second node, and an output terminal coupled to ground. The second-type transistor has a control terminal, an input terminal coupled to the first node, and an output terminal coupled to the second node. The second first-type transistor has a control terminal, an input terminal, and an output terminal coupled to the third node. The third second-type transistor has a control terminal coupled to the second node, an input terminal coupled to the third node, and an output terminal coupled to ground. The fourth second transistor has a control terminal, an input terminal coupled to the fourth node, and an output terminal coupled to the third node. The first non-volatile storage element is coupled between the second node and the fourth node. The second terminal of the first switch is coupled to the third node, and the second terminal of the second switch is coupled to the second node. In the write mode, the second-type transistor and the fourth second-type transistor are turned on. In the read mode, the second-type transistor and the fourth second-type transistor are turned off, and the input terminal of the first-type transistor and the input terminal of the second first-type transistor receive a supply voltage of the non-volatile SRAM circuit.

The non-volatile static random access memory circuit further comprises a third first type transistor. The third first-type transistor has a control terminal, an input terminal coupled to a supply voltage of the non-volatile static random access memory circuit, and an output terminal coupled to the input terminal of the first-type transistor and the input terminal of the second first-type transistor. The control end of the second type transistor and the control end of the fourth second type transistor receive the write-in selection signal. In the write mode, the third first-type transistor is turned off, and the write select signal is at the first voltage level to turn on the second-type transistor and the fourth second-type transistor. In the read mode, the third first-type transistor is turned on, and the write select signal is at the second voltage level to turn off the second-type transistor and the fourth second-type transistor.

In an embodiment, the control terminal of the third first-type transistor receives a write selection signal. In a write mode, the write select signal is at a first voltage level to turn off the third first-type transistor. In the read mode, the write select signal is at a second voltage level to turn on the third first-type transistor.

In another embodiment, the control terminal of the third first-type transistor receives a power limiting signal. In the write mode, the power supply is limited to a third voltage level to turn off the third first-type transistor. In the read mode, the power supply limit signal is at a fourth voltage level to turn on the third first-type transistor. When the non-volatile static random access memory circuit is in the standby mode, the power limiting signal is at a third voltage level to turn off the third first-type transistor.

In another embodiment, a latch circuit of a non-volatile SRAM circuit includes a first type transistor, a first second type transistor, a second type transistor, a second first type transistor, a third second type transistor, and a fourth second type transistor. The first type transistor has a control terminal coupled to the first node, an input terminal, and an output terminal coupled to the second node. The first second-type transistor has a control terminal coupled to the first node, an input terminal coupled to the third node, and an output terminal coupled to ground. The second-type transistor has a control terminal, an input terminal coupled to the second node, and an output terminal coupled to the first node. The second first-type transistor has a control terminal coupled to the third node, an input terminal, and an output terminal coupled to the fourth node. The third second-type transistor has a control terminal coupled to the third node, an input terminal coupled to the first node, and an output terminal coupled to ground. The fourth second-type transistor has a control terminal, an input terminal coupled to the fourth node, and an output terminal coupled to the third node. The first nonvolatile memory cell is coupled between the first node and the fourth node. The second terminal of the first switch is coupled to the first node, and the second terminal of the second switch is coupled to the third node. In the write mode, the second-type transistor and the fourth second-type transistor are turned on. In the read mode, the second-type transistor and the fourth second-type transistor are turned off, and the input terminal of the first-type transistor and the input terminal of the second first-type transistor receive a supply voltage of the non-volatile SRAM circuit.

The non-volatile static random access memory circuit further includes a third first type transistor. The third first-type transistor has a control terminal, an input terminal coupled to a supply voltage of the non-volatile static random access memory circuit, and an output terminal coupled to the input terminal of the first-type transistor and the input terminal of the second first-type transistor. The control end of the second type transistor and the control end of the fourth second type transistor receive the write-in selection signal. In the write mode, the third first-type transistor is turned off, and the write select signal is at the first voltage level to turn on the second-type transistor and the fourth second-type transistor. In the read mode, the third first-type transistor is turned on, and the write select signal is at the second voltage level to turn off the second-type transistor and the fourth second-type transistor.

In another embodiment, the control terminal of the third first-type transistor receives a power limiting signal. In the write mode, the power supply is limited to a third voltage level to turn off the third first-type transistor. In the read mode, the power supply limit signal is at a fourth voltage level to turn on the third first-type transistor. When the non-volatile static random access memory circuit is in the standby mode, the power limiting signal is at the third voltage level to turn off the third first-type transistor.

In yet another embodiment, the latch circuit further includes a second non-volatile storage element. When the nonvolatile static random access memory circuit is in a write mode, the second data on the second bit line is written into the latch circuit, and the second nonvolatile memory element has a second state corresponding to the second data. When the nonvolatile static random access memory circuit is in a read mode, second read data is generated according to a second state of a second nonvolatile memory element and provided to a second bit line.

In the embodiment of the invention, the data on the bit line is recorded in the latch circuit through the stroke of the impedance state of the nonvolatile memory element. Therefore, the conventional mode is not required until the nonvolatile SRAM circuit enters a power-off state or a standby mode, thereby saving the timing of the nonvolatile SRAM circuit.

Drawings

FIG. 1 shows a non-volatile SRAM circuit according to one embodiment of the present invention.

FIG. 2 shows a non-volatile SRAM circuit according to another embodiment of the present invention.

FIG. 3A illustrates the operation of the non-volatile SRAM circuit of FIG. 2 in a write mode according to one embodiment of the present invention.

FIG. 3B illustrates the operation of the non-volatile SRAM circuit of FIG. 2 in a read mode according to one embodiment of the present invention.

FIG. 4A illustrates the operation of the non-volatile SRAM circuit of FIG. 2 in a write mode according to another embodiment of the present invention.

FIG. 4B illustrates the operation of the non-volatile SRAM circuit of FIG. 2 in a read mode according to another embodiment of the present invention.

FIG. 5 shows a non-volatile SRAM circuit according to yet another embodiment of the present invention.

FIG. 6A illustrates the operation of the non-volatile SRAM circuit of FIG. 5 in a write mode according to one embodiment of the present invention.

FIG. 6B illustrates the operation of the non-volatile SRAM circuit of FIG. 5 in a read mode in accordance with one embodiment of the present invention.

FIG. 7A illustrates the operation of the non-volatile SRAM circuit of FIG. 5 in a write mode according to another embodiment of the present invention.

FIG. 7B illustrates the operation of the non-volatile SRAM circuit of FIG. 5 in a read mode in accordance with another embodiment of the present invention.

FIG. 8 shows a non-volatile SRAM circuit according to one embodiment of the present invention.

FIG. 9 shows a non-volatile SRAM circuit according to another embodiment of the present invention.

Description of the symbols:

1-a non-volatile static random access memory circuit;

10-a write control circuit;

11-latch circuit;

12. 13, switching;

100-PMOS transistors;

200. 201-PMOS transistor;

202. 203, 204, 205 to NMOS transistors;

206. 207 to nonvolatile memory element;

208. 209 to NMOS transistors;

500. 501-PMOS transistor;

502. 503, 504, 505 to NMOS transistors;

506. 507 to a nonvolatile memory element;

508. 509 to NMOS transistors;

BL, BLB-bit line;

GND-grounding;

HRS — high impedance state;

LRS-low impedance state;

n10, N11, N12-node;

n20, N21-node;

n50, N51-node;

OFF-closing;

ON-conduction;

PG power limit signal;

VS-voltage source;

WL word lines.

Detailed Description

The following description is an example of the present invention. The general principles of the present invention are intended to be illustrative, but not limiting, of the scope of the invention, which is defined by the claims.

It is noted that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The following specific examples and arrangements of components are merely illustrative of the spirit of the invention and are not intended to limit the scope of the invention. Moreover, the following description may repeat reference numerals and/or letters in the various examples. However, this repetition is for the purpose of providing a simplified and clear illustration only and is not intended to limit the scope of the various embodiments and/or configurations discussed below. Moreover, the description below of one feature connected to, coupled to, and/or formed on another feature, and the like, may actually encompass a variety of different embodiments that include the feature in direct contact, or that include other additional features formed between the features, and the like, such that the features are not in direct contact.

FIG. 1 shows a non-volatile SRAM circuit according to an embodiment of the present invention. In fig. 1, a nonvolatile sram circuit 1 includes a write control circuit 10, a latch circuit 11, and switches 12 and 13. As shown in FIG. 1, one end of the switch 12 is coupled to the bit line BL, and the other end thereof is coupled to the latch circuit 11 at the node N10. Switch 13 has one end coupled to bit line BLB and the other end coupled to latch 11 at node N11. The control terminals of

switches

12 and 13 are both coupled to word line WL. The write control circuit 10 is coupled to the latch circuit 11 to control the operation of the non-volatile sram circuit 1 in the write mode or the read mode. Data from the bit lines BL and BLB is stored in the latch circuit 11 under the control of the write control circuit 10. Therefore, the nonvolatile static random access memory circuit 1 does not need to operate in the existing storage mode before the nonvolatile static random access memory circuit 1 enters the power-off state or the standby mode. In addition, after the power of the non-volatile sram circuit 1 is turned on, the non-volatile sram circuit 1 does not need to operate in the conventional recall mode. The detailed circuit architecture and operation of the non-volatile SRAM circuit will be described below.

Referring to FIG. 2, in one embodiment, the write control circuit 10 includes a P-type metal oxide semiconductor (PMOS) transistor 100. The PMOS transistor 100 has a control terminal (gate) receiving the write select signal WS, an input terminal (source) coupled to the voltage source VS of the non-volatile sram circuit 1, and an output terminal (drain) coupled to the latch circuit 11 at the node N12. The latch circuit 11 includes

PMOS transistors

200 and 201, N-type metal oxide semiconductor (NMOS) transistors 202-205, and

non-volatile memory devices

206 and 207. In this embodiment, switches 12 and 13 are implemented with

NMOS transistors

208 and 209. The PMOS transistor 200 has a gate coupled to the node N20, an input coupled to the node N12, and an output coupled to the node N11. The control terminal (gate) of the NMOS transistor 202 is coupled to the node N10, the input terminal (drain) thereof is coupled to the node N11, and the output terminal thereof is coupled to the ground GND. The control terminal of the NMOS transistor 204 receives the write select signal WS, the input terminal thereof is coupled to the node N20, and the output terminal thereof is coupled to the node N11. The non-volatile memory element 206 is coupled between nodes N20 and N10.

The control terminal of the PMOS transistor 201 is coupled to the node N21, the input terminal thereof is coupled to the node N12, and the output terminal thereof is coupled to the node N10. The control terminal of the NMOS transistor 203 is coupled to the node N11, the input terminal thereof is coupled to the node N10, and the output terminal thereof is coupled to the ground GND. The control terminal of the NMOS transistor 205 receives the write select signal WS, the input terminal thereof is coupled to the node N21, and the output terminal thereof is coupled to the node N10. Non-volatile storage element 207 is coupled between nodes N21 and N11.

As shown in fig. 3A, when the supply voltage VDD supplies power to the nonvolatile static random access memory circuit 1 through the voltage source VS and the nonvolatile static random access memory circuit 1 operates in the write mode, the write select signal WS is at a high level of the supply voltage VDD (SW — VDD), and the word line WL has a high level. Assume that data of logic "0" is located on bit line BL (BL ═ 0), and data of logic "1" is located on bit line BLB (BLB ═ 1). The

NMOS transistors

204 and 205 are turned ON (ON) due to the write select signal WS having a high level. Due to the high level of the word line WL, the

NMOS transistors

208 and 209 are turned on. At this time, the node N10 has a low level to turn off the NMOS transistor 202 in response to the data of logic "0" on the bit line BL. The node N21 has a low level due to the low level of the node N10 and the conductive state of the NMOS transistor 205. In addition, node N11 has a high level to turn on NMOS transistor 203 in response to a data of logic "1" on bit line BLB. Due to the high level of the node N11 and the conductive state of the NMOS transistor 204, the node N20 has a high level.

As described above, the nonvolatile memory element 206 is coupled between nodes N20 and N10, and the nonvolatile memory element 207 is coupled between nodes N21 and N11. Since node N20 has a high level and node N10 has a low level, there is a forward bias applied to the non-volatile storage element 206, and the non-volatile storage element 206 has a low impedance state (LRS) to record data of a logic "0" on the bit line BL. Conversely, since node N21 has a low level and node N11 has a high level, there is a reverse bias applied to non-volatile storage element 207 and non-volatile storage element 206 has a high impedance state (HRS) to record a logic "1" of data on bit line BLB.

According to this embodiment, the data on the bit lines BL and BLB is recorded in the latch circuit 11 by the impedance state of the

nonvolatile memory elements

206 and 207. Therefore, the conventional mode is not required until the nonvolatile static random access memory circuit 1 enters a power-off state or a standby mode (i.e., no supply voltage VDD is supplied), thereby saving the timing of the nonvolatile static random access memory circuit 1.

As shown in fig. 3B, when the supply voltage VDD supplies power to the nonvolatile static random access memory circuit 1 through the voltage source VS and the nonvolatile static random access memory circuit 1 operates in the read mode, the write select signal WS is at a low level of 0V (WS ═ 0), and the word line WL also has a high level. The PMOS transistor 100 is turned on and the

NMOS transistors

204 and 205 are turned off due to the write select signal WS having a low level. Node N12 has a high level of the supply voltage VDD through PMOS transistor 100 being turned on. Due to the high level of the word line WL, the

NMOS transistors

208 and 209 are turned on. At this time, since the nonvolatile memory element 206 has a low impedance state, the node N20 is at a low level to turn on the PMOS transistor 200. With the PMOS transistor 200 turned on, the node N11 is at a high level (N11 ═ H) in response to the high level of the node N12. Further, since the nonvolatile memory element 207 has a high impedance state, the node N21 is at a high level to turn off the PMOS transistor 201. The NMOS transistor 203 is turned on in response to the high level of the node N11. Therefore, the node N10 is at a low level (N10 ═ L). NMOS transistor 202 turns off in response to the low level on node 10.

As described above, the node N11 is at a high level, and the node N10 is at a low level. With the NMOS transistor 208 turned on, the bit line BL has a low level, i.e., the bit line BL reads data of logic "0" from the latch circuit 11. With the NMOS transistor 209 turned on, the bit line BLB has a high level, i.e., the bit line BLB reads data of logic "1" from the latch circuit 11. In addition, since the PMOS transistor 201 and the NMOS transistor 202 are both turned off, the bit line BL stably reads data of logic "0", and the bit line BLB stably reads data of logic "1". Therefore, after the supply voltage VDD of the nonvolatile sram circuit 1 is supplied, the nonvolatile sram circuit 1 does not need to operate in the existing recall mode, thereby saving timing.

Fig. 4A and 4B illustrate the operation of the non-volatile sram circuit 1 according to another embodiment of the present invention. In this embodiment, as shown in FIG. 4A, when the nonvolatile SRAM circuit 1 operates in the write mode, the data of logic "1" is located on the bit line BL, and the data of logic "0" is located on the bit line BLB. When the nonvolatile static random access memory circuit 1 operates in the read mode, the bit line BL stably reads data of logic "1" and the bit line BLB stably reads data of logic "0", the operation of the nonvolatile static random access memory circuit 1 in fig. 4A and 4B is similar to that of fig. 3A and 3B. Accordingly, the operation of the embodiment of fig. 4A and 4B is omitted here.

Fig. 5 shows a non-volatile sram circuit 1 according to another embodiment of the present invention. Referring to fig. 2 and 5, the difference between the embodiment of fig. 2 and the embodiment of fig. 5 is the structure of the latch circuit 11. As shown in FIG. 5, the latch circuit 11 includes

PMOS transistors

500 and 501, NMOS transistors 502-505, and

nonvolatile memory elements

506 and 507. In this embodiment, switches 12 and 13 are implemented with

NMOS transistors

508 and 509, respectively. The PMOS transistor 500 has a control terminal coupled to the node N10, an input terminal coupled to the node N12, and an output terminal coupled to the node N50. The control terminal of the NMOS transistor 502 is coupled to the node N10, the input terminal thereof is coupled to the node N11, and the output terminal thereof is coupled to the ground GND. The control terminal of the NMOS transistor 504 receives the write select signal WS, the input terminal thereof is coupled to the node N50, and the output terminal thereof is coupled to the node N10. The non-volatile storage element 506 is coupled between nodes N50 and N11.

The control terminal of the PMOS transistor 501 is coupled to the node N11, the input terminal thereof is coupled to the node N12, and the output terminal thereof is coupled to the node N51. The control terminal of the NMOS transistor 503 is coupled to the node N11, the input terminal thereof is coupled to the node N10, and the output terminal thereof is coupled to the ground GND. The control terminal of the NMOS transistor 505 receives the write select signal WS, the input terminal thereof is coupled to the node N51, and the output terminal thereof is coupled to the node N11. Nonvolatile memory cell 507 is coupled between nodes N51 and N10.

As shown in fig. 6A, when the supply voltage VDD supplies power to the nonvolatile static random access memory circuit 1 through the voltage source VS and the nonvolatile static random access memory circuit 1 operates in the write mode, the write select signal WS is at a high level of the supply voltage VDD (SW — VDD), and the word line WL has a high level. Assume that data of logic "0" is located on bit line BL (BL ═ 0), and data of logic "1" is located on bit line BLB (BLB ═ 1). Due to the write select signal WS having a high level, the PMOS transistor is turned OFF (OFF), and the

NMOS transistors

504 and 505 are turned ON (ON). Due to the high level of the word line WL, the

NMOS transistors

508 and 509 are turned on. At this time, the node N10 has a low level to turn off the NMOS transistor 502 in response to the data of logic "0" on the bit line BL. The node N50 has a low level due to the low level of the node N10 and the conductive state of the NMOS transistor 504. In addition, in response to the data of logic "1" on the bit line BLB, the node N11 has a high level to turn on the NMOS transistor 503. The node N51 has a high level due to the high level of the node N11 and the conductive state of the NMOS transistor 505.

As described above, the nonvolatile memory element 506 is coupled between nodes N50 and N11, and the nonvolatile memory 507 is coupled between nodes N51 and N10. Since node N50 has a low level and node N11 has a high level, then there is a reverse bias applied to the non-volatile storage element 506, and the non-volatile storage element 506 is defined as having a low impedance state (LRS) to record data of a logic "0" on the bit line BL. Conversely, since node N51 has a low level and node N10 has a high level, then there is a forward bias applied to the non-volatile storage element 507 and the non-volatile storage element 507 is defined as having a high impedance state (HRS) to record data of a logic "1" on the bit line BLB.

nonvolatile memory elements

506 and 507. Therefore, the conventional mode is not required until the nonvolatile static random access memory circuit 1 enters a power-off state or a standby mode (i.e., no supply voltage VDD is supplied), thereby saving the timing of the nonvolatile static random access memory circuit 1.

As shown in fig. 6B, when the supply voltage VDD supplies power to the nonvolatile static random access memory circuit 1 through the voltage source VS and the nonvolatile static random access memory circuit 1 operates in the read mode, the write select signal WS is at a low level of 0V (WS ═ 0), and the word line WL also has a high level. Due to the write select signal WS having a low level, the PMOS transistor 100 is turned on, and the

NMOS transistors

504 and 505 are turned off. With the PMOS transistor 100 turned on, the node N12 has a high level of the supply voltage VDD. Due to the high level of the word line WL, the

NMOS transistors

508 and 509 are turned on. At this time, since the nonvolatile memory element 507 has a high impedance state, a current flowing through the nonvolatile memory element 507 is small, and the node N10 is at a low level (N10 ═ L ") to turn on the PMOS transistor 500 and turn off the NMOS transistor 502. In addition, since the nonvolatile memory cell 506 has a low resistance state, more current flows through the nonvolatile memory element 506, and the node N11 is at a high level (N11 ═ H ") to turn off the PMOS transistor 501 and turn on the NMOS transistor 503.

As described above, the node N11 is at a high level, and the node N10 is at a low level. With the switch 12 turned on, the bit line BL has a low level, i.e., the bit line BL reads data of logic "0" from the latch circuit 11. With switch 13 turned on, bit line BLB has a high level, i.e., bit line BLB reads data of logic "1" from latch circuit 11. In addition, since the PMOS transistor 501 and the NMOS transistor 502 are both turned off, the bit line BL stably reads data of logic "0", and the bit line BLB stably reads data of logic "1".

Fig. 7A and 7B illustrate the operation of the non-volatile sram circuit 1 according to another embodiment of the present invention. In this embodiment, as shown in FIG. 7A, when the nonvolatile SRAM circuit 1 operates in the write mode, the data of logic "1" is located on the bit line BL, and the data of logic "0" is located on the bit line BLB. When the nonvolatile static random access memory circuit 1 operates in the read mode, the bit line BL stably reads data of logic "1" and the bit line BLB stably reads data of logic "0", the operation of the nonvolatile static random access memory circuit 1 in fig. 7A and 7B is similar to that of fig. 6A and 6B. Accordingly, the operation of the embodiment with respect to fig. 7A and 7B is omitted here.

Fig. 8 shows a non-volatile sram circuit 1 according to another embodiment of the present invention. The difference between the embodiment of fig. 2 and the embodiment of fig. 8 is the architecture of the write control circuit 10. In the write control circuit 10, the control terminal of the PMOS transistor 100 receives the power supply restriction signal PG instead of the write selection signal WS. When the nonvolatile static random access memory circuit 1 operates in the standby mode or operates in the write mode, the power supply restriction signal PG has a high level to turn off the PMOS transistor 100. When the nonvolatile static random access memory circuit 1 operates in the read mode, the power supply restriction signal PG has a low level to turn on the PMOS transistor 100. The operation of other elements of the non-volatile sram circuit 1 in the embodiment of fig. 8 is similar to that of fig. 2, 3A, 3B, 4A, and 4B, and therefore the related description is omitted. In this embodiment, the write select signal WS has a low level in the standby mode.

Fig. 9 shows a non-volatile sram circuit 1 according to another embodiment of the present invention. The difference between the embodiment of fig. 5 and the embodiment of fig. 9 is the architecture of the write control circuit 10. In the write control circuit 10, the control terminal of the PMOS transistor 100 receives the power supply restriction signal PG instead of the write selection signal WS. When the nonvolatile static random access memory circuit 1 operates in the standby mode or operates in the write mode, the power supply restriction signal PG has a high level to turn off the PMOS transistor 100. When the nonvolatile static random access memory circuit 1 operates in the read mode, the power supply restriction signal PG has a low level to turn on the PMOS transistor 100. The operations of the other elements of the non-volatile sram circuit 1 in the embodiment of fig. 8 are similar to those in fig. 5, 6A, 6B, 7A, and 7B, and therefore the related descriptions are omitted. In this embodiment, the write select signal WS has a low level in the standby mode.

Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A non-volatile static random access memory circuit, comprising:

a first switch having a first end coupled to a first bit line and a second end;

a second switch having a first end coupled to a second bit line and a second end;

a control circuit for receiving a write select signal or a power limit signal;

a latch circuit, coupled to the second terminal of the first switch and the second terminal of the second switch, coupled to the control circuit, for receiving the write select signal, and having a first non-volatile storage element;

when the nonvolatile static random access memory circuit is in a writing mode, first data on the first bit line is written into the latch circuit, and the first nonvolatile storage element has a first state corresponding to the first data;

wherein, when the non-volatile static random access memory circuit is in a read mode, a first read data is generated according to the first state of the first non-volatile storage element and provided to the first bit line;

in the write mode, the write select signal is at a first voltage level to control the latch circuit to change the first nonvolatile memory element to the first state; and

in the read mode, the write select signal is at a second voltage level to control the latch circuit to generate the first read data according to the first state.

2. The non-volatile sram circuit of claim 1, wherein the first switch and the second switch are turned on in the write and read modes.

3. The non-volatile sram circuit of claim 1, wherein no supply voltage powers the non-volatile sram circuit between the write mode and the read mode, or the non-volatile sram circuit is in a standby mode.

4. The circuit of claim 1, wherein the latch circuit comprises:

a first type transistor having a control terminal coupled to a first node, an input terminal, and an output terminal coupled to a second node;

a first second-type transistor having a control terminal coupled to a third node, an input terminal coupled to the second node, and an output terminal coupled to a ground;

a second-type transistor having a control terminal for receiving the write select signal, an input terminal coupled to the first node, and an output terminal coupled to the second node;

a second first type transistor having a control terminal coupled to a fourth node, an input terminal, and an output terminal coupled to the third node;

a third second-type transistor having a control terminal coupled to the second node, an input terminal coupled to the third node, and an output terminal coupled to the ground; and

a fourth second-type transistor having a control terminal for receiving the write select signal, an input terminal coupled to a fourth node, and an output terminal coupled to the third node;

wherein the first non-volatile storage element is coupled between the second node and the fourth node; and

the second terminal of the first switch is coupled to the third node, and the second terminal of the second switch is coupled to the second node.

5. The non-volatile SRAM circuit of claim 4 wherein the second-type transistor and the fourth second-type transistor are turned on in the write mode.

6. The non-volatile SRAM circuit of claim 4 wherein in the read mode the second-type transistor and the fourth second-type transistor are turned off and the input of the first-type transistor and the input of the second first-type transistor receive a supply voltage of the non-volatile SRAM circuit.

7. The non-volatile sram circuit of claim 4, wherein the control circuit receives the write select signal and further comprises:

a third first-type transistor having a control terminal for receiving the write select signal, an input terminal coupled to a supply voltage of the non-volatile SRAM circuit, and an output terminal coupled to the input terminal of the first-type transistor and the input terminal of the second first-type transistor;

wherein the control terminal of the second type transistor and the control terminal of the fourth second type transistor receive a write select signal;

in the write mode, the write selection signal is at the first voltage level to turn off the third first-type transistor and turn on the second-type transistor and the fourth second-type transistor; and

in the read mode, the write select signal is at the second voltage level to turn on the third first-type transistor and turn off the second-type transistor and the fourth second-type transistor.

8. The non-volatile SRAM circuit of claim 4 wherein the first type transistor and the second first type transistor are PMOS transistors and the first second type transistor, the second type transistor, the third second type transistor and the fourth second type transistor are NMOS transistors.

9. The circuit of claim 1, wherein the latch circuit comprises:

a first second-type transistor having a control terminal coupled to the first node, an input terminal coupled to a third node, and an output terminal coupled to a ground;

a second-type transistor having a control terminal for receiving the write select signal, an input terminal coupled to the second node, and an output terminal coupled to the first node;

a second first type transistor having a control terminal coupled to the third node, an input terminal, and an output terminal coupled to a fourth node;

a third second-type transistor having a control terminal coupled to the third node, an input terminal coupled to the first node, and an output terminal coupled to the ground; and

a fourth second-type transistor having a control terminal for receiving the write select signal, an input terminal coupled to the fourth node, and an output terminal coupled to the third node;

wherein the first non-volatile storage element is coupled between the first node and the fourth node; and

the second terminal of the first switch is coupled to the first node, and the second terminal of the second switch is coupled to the third node.

10. The non-volatile sram circuit of claim 9, wherein the second-type transistor and the fourth second-type transistor are turned on in the write mode.

11. The non-volatile sram circuit of claim 9, wherein in the read mode the second-type transistor and the fourth second-type transistor are turned off, and the input of the first-type transistor and the input of the second first-type transistor receive a supply voltage of the non-volatile sram circuit.

12. The non-volatile sram circuit of claim 9 wherein the control circuit receives the power limit signal and further comprises:

a third first-type transistor having a control terminal for receiving the power-limiting signal, an input terminal coupled to a supply voltage of the non-volatile SRAM circuit, and an output terminal coupled to the input terminal of the first-type transistor and the input terminal of the second first-type transistor;

wherein the control terminal of the second type transistor and the control terminal of the fourth second type transistor receive the write select signal;

in the write mode, the power limiting signal is at a third voltage level to turn off the third first-type transistor and turn on the second-type transistor and the fourth second-type transistor; and

in the read mode, the power-limiting signal is at a fourth voltage level to turn on the third first-type transistor and turn off the second-type transistor and the fourth second-type transistor.

13. The circuit of claim 9, wherein the first and second first-type transistors are PMOS transistors, and the first second-type transistor, the second-type transistor, the third second-type transistor, and the fourth second-type transistor are NMOS transistors.

14. The non-volatile sram circuit of claim 1 wherein the latch circuit further comprises a second non-volatile storage element;

when the nonvolatile static random access memory circuit is in the writing mode, a second data on the second bit line is written into the latch circuit, and the second nonvolatile storage element has a second state corresponding to the second data; and

when the non-volatile static random access memory circuit is in the read mode, a second read data is generated according to the second state of the second non-volatile storage element and provided to the second bit line.