CN105825885A - Multilevel memory cell based on memristor, read-write circuit and operation method thereof - Google Patents
Multilevel memory cell based on memristor, read-write circuit and operation method thereof Download PDFInfo
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- CN105825885A CN105825885A CN201610160484.5A CN201610160484A CN105825885A CN 105825885 A CN105825885 A CN 105825885A CN 201610160484 A CN201610160484 A CN 201610160484A CN 105825885 A CN105825885 A CN 105825885A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
Abstract
The invention discloses a multilevel memory cell based on memristor, a read-write circuit and an operation method thereof. The multilevel memory cell is formed by connecting a plurality of memristors in a special mode based on the resistance changing characteristic of memristor. The multilevel memory cell has the advantages of memristor such as small volume, low energy consumption, strong expansibility, and the like. Compared with a conventional memristor memory structure, the multilevel memory structure provides a larger memory space, and a novel thinking is provided for memory design. The read-write circuit of the multilevel memory cell comprises a memory cell, a control switch, and a voltage comparison circuit. The read-write circuit can select the read/write/erase operations through an applied pulse signal, has the advantages of simple structure, few required devices, and precise read results, and can be applied to large-scale array memory by being combined with a location circuit.
Description
Technical field
The invention belongs to memory area, more particularly, to a kind of multilevel memory cell based on memristor and read/write circuit thereof.
Background technology
Memristor is that the scientist Cai Shaotang of California, USA university Berkeley proposed in 1971, and Cai Shaotang professor proposes from symmetry angle prophesy, and in addition to electric capacity, inductance and resistance, electronic circuit also should exist the 4th kind of primary element memristor.Cai Shaotang points out, voltage v, electric current i, electric charge q and magnetic fluxSix kinds of mathematical relationships should be there are: current definition is electric charge derivative i (t)=dq (t)/dt about the time between these 4 basic circuit variablees；Voltage is the magnetic flux derivative about the timeResistance is defined as voltage along with the rate of change R=dv/di of electric current；Electric capacity is defined as electric charge along with the rate of change C=dq/dv of voltage；Inductance is defined as magnetic flux along with the rate of change of electric currentAlso having a problem to be the absence of one can be by electric charge q and magnetic fluxThe component associated, and this element is i.e. by electric charge q and magnetic fluxBetween relation define, Cai Shaotang is by named for this element memristor
This smooth Williams of U.S. HP Lab and its colleague produce the material object of memristor when carrying out minimal type Experiment of Electrical Circuits, and its achievement is published on " nature " magazine in May, 2008.The audion that the discovery of memristor is invented before being enough to match in excellence or beauty 100 years, its any one commercial application all may bring the Industrial Revolution of a new round.Chinese science and technology portion points out in its official website on April 13rd, 2010: " U.S. HP Lab scientist writes articles expression on April 8th, 2010 on " naturally " magazine; they obtain important breakthrough on memristor provides; find that memristor can carry out boolean calculation, processes for data and storage application ".
After the memristor of Cai Shaotang proposition is confirmed by HP Lab, the applied research of memristor covers and learns and the every field of secret communication to nerve from storage and logical reconstruction, memristor itself has non-volatile memory ability, and therefore nonvolatile random access memory based on memristor is one of main application of memristor.
Summary of the invention
The present invention is based on the distinctive threshold voltage of memristor and the characteristic with high and low two kinds of resistance states, provide the circuit structure of a kind of multivalued storage based on memristor, this circuit structure utilizes the features such as memristor volume is little, state change speed is fast, compatibility is good, extend field and the implementation method of multivalued storage, and avoid the tradition multilevel memory cell based on the memristor dependence to metal-oxide-semiconductor；The described reading and writing of multilevel memory cell circuit based on memristor, the implementation method of erasing function have been inquired into simultaneously, its object is to the multilevel memory cell based on memristor for the present invention proposes read and write, wipe operation, this read/write circuit is combined with array element addressing circuit simultaneously and can effectively reduce the leakage current being currently based in memristor storage array read/write circuit.
The invention provides a kind of multilevel memory cell based on memristor, including the first memristor S1, the second memristor S2, the 3rd memristor S3, the 4th memristor S4, the 5th memristor S5With the 6th memristor S6；Described first memristor S1The first end, described second memristor S2The first end and described 3rd memristor S4The first end connect after as the input of described multilevel memory cell；Described first memristor S1The second end, described 3rd memristor S3The second end and described 6th memristor S6The second end phase downlink connection after as the outfan of described multilevel memory cell；Described second memristor S2The second end and described 3rd memristor S3The first end be connected；Described 4th memristor S4The second end and described 5th memristor S5The first end be connected；Described 5th memristor S5The second end and described 6th memristor S6The first end be connected.
Further, described first memristor S1, described second memristor S2, described 3rd memristor S3, described 4th memristor S4, described 5th memristor S5With described 6th memristor S6It is respectively provided with high-impedance state and low resistance state；And the original state of above-mentioned six memristors is in low resistance state state；After memristor both end voltage exceedes memristor voltage threshold value, described memristor is switched to high-impedance state from low resistance state.
Further, as described first memristor S1, described second memristor S2, described 3rd memristor S3, described 4th memristor S4, described 5th memristor S5With described 6th memristor S6When being in initial high-impedance state, described multilevel memory cell storage value is 0；When described first memristor is in low resistance state, and when the second to the 6th memristor is in high-impedance state, described multilevel memory cell storage value is 1；When the first to the 3rd memristor is in low resistance state, and when the 4th to the 6th memristor is in high-impedance state, described multilevel memory cell storage value is 2；When the first memristor to the 6th memristor is in high-impedance state, described multilevel memory cell storage value is 3.
The invention provides a kind of read/write circuit based on above-mentioned multilevel memory cell, including the first control switch T1, second control switch T2, memory element M1, cascade resistance R1, the first diode D1, the second diode D2, the 3rd diode D3, the first voltage comparator C1, the second voltage comparator C2With tertiary voltage comparator C3；First controls switch T1Control end and the first termination input signal, by input signal decision-making circuit function；Described first controls switch T1Second end and memory element M1First end end is connected；Described memory element M1The second end end, cascade resistance R1The first end end and second control switch T2The first end be connected；Described second controls switch T2Controlling termination read signal, when circuit is in reading function, described second controls switch T2Conducting；Described second controls switch T2Second end and described first diode D1First end is connected；Described first diode D1Second end, the first voltage comparator C1First end and the second diode D2First end is connected；Described second diode D2Second end, described 3rd diode D3First end and the second voltage comparator C2First end is connected；Described 3rd audion D3Second end and described tertiary voltage comparator C3First end is connected.
Further, described first controls switch T1Switch T is controlled with described second2For insulated gate bipolar transistor IGBT；Described first diode D1, described second diode D2With described 3rd diode D3It is the crystal diode of band pressure drop.
Further, at described first voltage comparator C1, described second voltage comparator C2With described tertiary voltage comparator C3In, when voltage comparator input voltage is more than voltage comparator predeterminated voltage, exports high ordinary mail number, be designated as 1；When voltage comparator input voltage is less than voltage comparator predeterminated voltage, exports LOW signal, be designated as 0；When voltage comparator no signal inputs, voltage comparator output LOW signal.
Further, described first voltage comparator C1, described second voltage comparator C2With described tertiary voltage comparator C3There are four kinds of output states: 000,001,011,111；And these four state is corresponding with the four of described multilevel memory cell kinds of storage states.
Present invention also offers a kind of write operation method based on above-mentioned read/write circuit, by controlling switch T described first1First end and control end input write signal, and control described second control switch T2Disconnect, realize write operation.
Present invention also offers a kind of reset operation method based on above-mentioned read/write circuit, by controlling switch T described first1First end and control end input reset signal, and control described second control switch T2Disconnect, realize the operation that resets；The amplitude of wherein said reset signal is sufficiently large and long enough input time is to ensure that described multilevel memory cell reverts back to original state.
Present invention also offers a kind of read operation method based on above-mentioned read/write circuit, by controlling switch T described first1First end and control end input read signal, and control switch T described second2Controlling end input reading signal pulse makes described second to control switch T2Conducting, realizes read operation；Wherein, the amplitude of described read signal not can exceed that single described memristor threshold voltage size, it is ensured that will not change multilevel memory cell M1Storage state.
In general, by the contemplated above technical scheme of the present invention compared with prior art, due to characteristic, the circuit structure of multilevel memory cell based on memristor and reading and writing, the implementation method of erasing function that memristor self is good, it is possible to obtain the beneficial effect of following non-volatile memories:
(1) multilevel memory cell based on memristor of the present invention can be extended to the form of storage array, has good extensibility, and has good compatibility with conventional MOS circuit；Simultaneously after being extended to storage array, improve the memory capacity of conventional memory cell.Optimize leakage problem crucial in existing memristor array stores technology, improve the effectiveness of storage.
(2) write circuit of the multilevel memory cell based on memristor of the present invention and erasing circuit, compared to tradition read/write circuit, the electronic device of use is less, and integrated circuit structure is simpler, and power consumption is less.
(3) the multilevel memory cell reading circuit based on memristor of the present invention, utilize diode drop analog threshold voltage characteristic, save voltage comparator and the external quantity comparing power supply, improve the reading accuracy of the resistance unit of memristor multilevel memory cell, be effectively improved the accuracy the most repeatedly to the read-write of memristor memory element.
Accompanying drawing explanation
Fig. 1 is the VA characteristic curve schematic diagram of bipolarity memristor；
Fig. 2 is the multilevel memory cell electrical block diagram based on memristor that the embodiment of the present invention provides；
Fig. 3 is the multilevel memory cell VA characteristic curve based on memristor that the embodiment of the present invention provides；
Fig. 4 is present invention multilevel memory cell based on memristor reading and writing, erasing circuit structural representation.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.As long as just can be mutually combined additionally, technical characteristic involved in each embodiment of invention described below does not constitutes conflict each other.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
The (if present) such as term " first " in the present invention and above-mentioned accompanying drawing, " second " is for distinguishing similar object, without being used for describing specific order or precedence.Should be appreciated that the data of so use can be exchanged in the appropriate case, in order to embodiments of the invention described herein such as can be implemented with the order in addition to those here illustrating or describing.In addition, term " includes " and " having " and their any deformation, it is intended to cover non-exclusive comprising, such as, contain series of steps or the process of unit, method, system, product or equipment be not necessarily limited to those steps or the unit clearly listed, but can include the most clearly listing or for intrinsic other step of these processes, method, product or equipment or unit.
Before introducing technical scheme, first introducing some characteristics of memristor used in the present invention, Fig. 1 is the VA characteristic curve schematic diagram of bipolarity memristor；It will be seen from figure 1 that when being added in the voltage at memristor two ends more than or equal to the first voltage threshold V1Time, from high value state, (resistance is designated as R to memristorOFF) (resistance is designated as R to become low resistance stateON), when being added in the voltage of memristor less than or equal to the second voltage threshold V2Time, memristor becomes high value state from low resistance state.When memristor is in high value state, only forward bias can make its state be become low-resistance, reverse bias or no-voltage biasing from high resistant, changes all without the state making it；When memristor is in low resistive state, only reverse bias can make its state be become high resistant, forward bias or no-voltage biasing from low-resistance, changes all without the state making it.
Based on above-mentioned memristor characteristic, by memristor same polarity series connection identical with threshold voltage for multiple original states, then on this series circuit, the state resistance state change of all memristors will synchronize, overall first voltage threshold of series circuit and the amplitude of the second voltage threshold and the memristor number direct proportionality connected.
Based on above-mentioned memristor series circuit characteristic, series circuits different for multiple memristor numbers can be formed described multilevel memory cell with parallel form, as shown in Figure 2.It it is described multilevel memory cell VA characteristic curve based on memristor shown in Fig. 3；As it can be seen, the resistance of described multilevel memory cell is relevant with the voltage that multilevel memory cell two ends are applied.Numerical value " 0 ", " 1 ", " 2 " and " 3 " is stored by the change in resistance of multilevel memory cell.Multilevel memory cell both end voltage, resistance and corresponding storage numerical value are as shown in Table 1.
Table one
It is pointed out that the memristor original state used in the present invention is high value state, then multilevel memory cell M1Initial resistance RM1For
Below in conjunction with the accompanying drawings and embodiment the present invention is described in detail.
As shown in Figure 4, Fig. 4 is multilevel memory cell read/write circuit figure.Figure includes the first control switch T1, second control switch T2, memory element M1, cascade resistance R1, the first diode D1, the second diode D2, the 3rd diode D3, the first voltage comparator C1, the second voltage comparator C2With tertiary voltage comparator C3.First controls switch T1Control end and the first termination input signal, by input signal decision-making circuit function；First controls switch T1Second end is connected with memory element upper end；Described memory element M1Lower end, cascade resistance R1Upper end and second control switch T2The first end be connected；Described second controls switch T2Controlling termination read signal, when circuit is in reading function, second controls switch T2Conducting；Second controls switch T2Second end and the first diode D1Upper end is connected；First diode D1Lower end, the first voltage comparator C1Input and the second diode D2Upper end is connected；Second diode D2Lower end, the 3rd audion D3With the second voltage comparator C2Input is connected；3rd audion D3Lower end and tertiary voltage comparator C3Input is connected.Described the first to tertiary voltage comparator (OUT1～OUT3) finally there are four kinds of output states that is 000,100,110,111 (0 represents low level, and 1 represents high level).
For apparent explanation read/write circuit operation principle based on multilevel memory cell, below carefully illustrate its read-write process and result of circuit test:
(1) write operation of multilevel memory cell: first controls switch T1 accesses write signal, and second controls switch T2 disconnects, and now circuit is memory element M1 and cascade resistance R1 cascaded structure.Assume that writing voltage is Vwrite, then memory element M1 both end voltage isAccording to table one, find out the corresponding voltage needing to write data, and will write voltage VwriteSize be adjusted in table one after corresponding voltage i.e. writable data.
(2) read operation of multilevel memory cell: first controls switch T1 accesses reading signal, and second controls switch T2 conducting, it is assumed that reading signal voltage is Vread(in order to prevent reading signal change state of memory cells, read signal voltage VreadShould be less than described single memristor first threshold voltage V1), now memory element M1Lower end and cascade resistance R1Junction, upper end node voltage isAs shown in Table 1, tetra-kinds of different resistance value state of memory element M1 create four kinds of electric pressures, four kinds of numerical value of these four voltage correspondence multilevel memory cell storage at node.
When multilevel memory cell storage numerical value is 3, now memory element resistance is minimum, and the value of node voltage is maximum, and the diode drop at least above three times, so the most all voltage comparators all have voltage signal input and more than 0, three road voltage comparators all export high ordinary mail number.
When multilevel memory cell storage numerical value is 2, the value of node voltage is between twice diode and three times of diode drops, so now only having the first voltage comparator C1With the second voltage comparator C2Voltage is had to input, the first voltage comparator C1With the second voltage comparator C2Export high ordinary mail number, tertiary voltage comparator C3Output LOW signal.
When multilevel memory cell storage numerical value is 1, the value of node voltage is between one times of diode and two times of diode drops, so now only having the first voltage comparator C1Voltage is had to input, the first voltage comparator C1Export high ordinary mail number, the second voltage comparator C2With tertiary voltage comparator C3Output LOW signal.
When multilevel memory cell storage numerical value is 0, now in multilevel memory cell, all memristors are in initial high-impedance state, memory element resistance is the highest, node voltage value is minimum and is less than single diode drop, the equal no-voltage signal of the most all voltage comparators inputs, therefore the output of all voltage comparators is 0.
By detecting the output state of three road voltage comparators, according to table one corresponding relation, the storage numerical value of multilevel memory cell can be read.
(3) the erasing operation of multilevel memory cell: first controls switch T1 accesses reset signal, and second controls switch T2 disconnects, and now circuit is memory element M1 and cascade resistant series structure.Assume that resetting voltage is Vreset, then memory element M1 both end voltage isAccording to memristor VA characteristic curve shown in Fig. 1, if VresetValue all memristors can be made to reply initial high-impedance state for negative and sufficiently large, complete erasing and reset operation.
Those skilled in the art is easy to understand; the foregoing is only presently preferred embodiments of the present invention; not in order to limit the present invention, all any amendment, equivalent and improvement etc. made within the spirit and principles in the present invention, should be included within the scope of the present invention.
Claims (10)
1. a multilevel memory cell based on memristor, it is characterised in that include the first memristor S1, the second memristor S2, the 3rd memristor S3, the 4th memristor S4, the 5th memristor S5With the 6th memristor S6；
Described first memristor S1The first end, described second memristor S2The first end and described 3rd memristor S4The first end connect after as the input of described multilevel memory cell；Described first memristor S1The second end, described 3rd memristor S3The second end and described 6th memristor S6The second end phase downlink connection after as the outfan of described multilevel memory cell；
Described second memristor S2The second end and described 3rd memristor S3The first end be connected；Described 4th memristor S4The second end and described 5th memristor S5The first end be connected；Described 5th memristor S5The second end and described 6th memristor S6The first end be connected.
2. multilevel memory cell as claimed in claim 1, it is characterised in that described first memristor S1, described second memristor S2, described 3rd memristor S3, described 4th memristor S4, described 5th memristor S5With described 6th memristor S6It is respectively provided with high-impedance state and low resistance state；And the original state of above-mentioned six memristors is in low resistance state state；After memristor both end voltage exceedes memristor voltage threshold value, described memristor is switched to high-impedance state from low resistance state.
3. multilevel memory cell as claimed in claim 1 or 2, it is characterised in that as described first memristor S1, described second memristor S2, described 3rd memristor S3, described 4th memristor S4, described 5th memristor S5With described 6th memristor S6When being in initial high-impedance state, described multilevel memory cell storage value is 0；When described first memristor is in low resistance state, and when the second to the 6th memristor is in high-impedance state, described multilevel memory cell storage value is 1；When the first to the 3rd memristor is in low resistance state, and when the 4th to the 6th memristor is in high-impedance state, described multilevel memory cell storage value is 2；When the first memristor to the 6th memristor is in high-impedance state, described multilevel memory cell storage value is 3.
4. a read/write circuit based on the multilevel memory cell described in any one of claim 13, it is characterised in that include the first control switch T1, second control switch T2, memory element M1, cascade resistance R1, the first diode D1, the second diode D2, the 3rd diode D3, the first voltage comparator C1, the second voltage comparator C2With tertiary voltage comparator C3；
Described first controls switch T1Control end and the first termination input signal, by input signal decision-making circuit function；Described first controls switch T1Second end and memory element M1First end end is connected；Described memory element M1The second end end, cascade resistance R1The first end and second control switch T2The first end be connected；Described second controls switch T2Controlling termination read signal, when circuit is in reading function, described second controls switch T2Conducting；
Described second controls switch T2Second end and described first diode D1First end is connected；Described first diode D1Second end, the first voltage comparator C1First end and the second diode D2First end is connected；Described second diode D2Second end, described 3rd diode D3First end and the second voltage comparator C2First end is connected；Described 3rd audion D3Second end and described tertiary voltage comparator C3First end is connected.
5. read/write circuit as claimed in claim 4, it is characterised in that described first controls switch T1Switch T is controlled with described second2For insulated gate bipolar transistor IGBT；Described first diode D1, described second diode D2With described 3rd diode D3It is the crystal diode of band pressure drop.
6. read/write circuit as claimed in claim 4, it is characterised in that at described first voltage comparator C1, described second voltage comparator C2With described tertiary voltage comparator C3In, when voltage comparator input voltage is more than voltage comparator predeterminated voltage, exports high ordinary mail number, be designated as 1；When voltage comparator input voltage is less than voltage comparator predeterminated voltage, exports LOW signal, be designated as 0；When voltage comparator no signal inputs, voltage comparator output LOW signal.
7. read/write circuit as claimed in claim 6, it is characterised in that described first voltage comparator C1, described second voltage comparator C2With described tertiary voltage comparator C3There are four kinds of output states: 000,001,011,111；And these four state is corresponding with the four of described multilevel memory cell kinds of storage states.
8. a write operation method based on the read/write circuit described in claim 4, it is characterised in that by controlling switch T described first1First end and control end input write signal, and control described second control switch T2Disconnect, realize write operation.
9. a reset operation method based on the read/write circuit described in claim 4, it is characterised in that by controlling switch T described first1First end and control end input reset signal, and control described second control switch T2Disconnect, realize the operation that resets；The amplitude of wherein said reset signal is sufficiently large and long enough input time is to ensure that described multilevel memory cell reverts back to original state.
10. a read operation method based on the read/write circuit described in claim 4, it is characterised in that by controlling switch T described first1First end and control end input read signal, and control switch T described second2Controlling end input reading signal pulse makes described second to control switch T2Conducting, realizes read operation；Wherein, the amplitude of described read signal not can exceed that single described memristor threshold voltage size, it is ensured that will not change multilevel memory cell M1Storage state.
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| CN110797062A (en) * | 2019-09-17 | 2020-02-14 | 华中科技大学 | Memristor read-write circuit and method |
| WO2021051548A1 (en) * | 2019-09-17 | 2021-03-25 | 华中科技大学 | Read-write circuit and read-write method for memristor |
| CN110797063B (en) * | 2019-09-17 | 2021-05-25 | 华中科技大学 | Memristor memory chip and operation method thereof |
| CN110797062B (en) * | 2019-09-17 | 2021-07-06 | 华中科技大学 | Memristor read-write circuit and method |
| US11238928B2 (en) | 2019-09-17 | 2022-02-01 | Huazhong University Of Science And Technology | Read-write circuit and read-write method of memristor |
| CN113314178A (en) * | 2021-05-07 | 2021-08-27 | 浙江树人学院（浙江树人大学） | Memristor reading and writing method |
| CN114121087A (en) * | 2021-11-16 | 2022-03-01 | 上海集成电路装备材料产业创新中心有限公司 | Read circuit of multivalued memory |
| CN114121087B (en) * | 2021-11-16 | 2024-03-26 | 上海集成电路装备材料产业创新中心有限公司 | Reading circuit of multi-value memory |
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