CN103106922B - Programming method for separating grid memory array - Google Patents
Programming method for separating grid memory array Download PDFInfo
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- CN103106922B CN103106922B CN201210577034.8A CN201210577034A CN103106922B CN 103106922 B CN103106922 B CN 103106922B CN 201210577034 A CN201210577034 A CN 201210577034A CN 103106922 B CN103106922 B CN 103106922B
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Abstract
The invention discloses a programming method for separating a grid memory array. The programming method comprises the following steps of: at a preprogramming stage, applying a preprogramming voltage to word lines within a sector where a target memory bit unit is arranged, applying a work voltage to all the word lines, and applying the work voltage to source electrode wires within the sector where the target memory bit unit is arranged, so that the mis-programming to a non-target memory bit unit in the stage of programming can be avoided or reduced; and at a programming stage, applying a word line programming voltage to the word lines of the target memory bit unit, applying a bit line programming voltage to a bit line of the target memory bit unit, applying the source electrode programming voltage to the source electrode wires of the target memory bit unit, and programming the target memory bit unit. According to the programming method for separating the grid memory array, the interference to the non-target memory bit unit can be reduced when the target memory bit unit is programmed.
Description
Technical field
The present invention relates to memory technology field, more particularly to a kind of programmed method of separate gate storage array.
Background technology
Flash memory (flash memory) as a kind of integrated circuit memory devices, because there is electrically-erasable to deposit for it
The function of storage information, and the information stored after power-off will not lose, therefore, flash memory is widely used in as portable
In the electronic products such as computer, mobile phone, digital music player.Common, according to the difference of grid structure, flash memory is divided into
Piled grids flash memory and Frash memory in separate grids two types, both flash memories are required for storage is single
Unit is arranged with the array for being adapted to operation itself, and each storage bit unit is all used for storing the data of single position.
Fig. 1 is a kind of cross-sectional view of the separate gate flash memory of shared source electrode line, and Fig. 1 is that a storage is single
Unit, has two storage bit units, respectively the first storage bit unit 1 and the second storage bit unit in a memory cell
2, each storage bit unit includes a wordline 16, bit line 14, floating boom 15, and bitline regions 12 are located in the substrate 10 under wordline 16,
First storage bit unit 1 and the second storage bit unit 2 share a source electrode line 17, and source area 13 is located at the substrate under source electrode line 17
In 10, there is channel region 11 between bitline regions 12 and source area 13, share first storage bit unit 1 and the of a source electrode line 17
Two storage bit units 2 are symmetrical.Multiple above-mentioned storage bit unit array arrangements, form separate gate storage array, wherein, each column
The storage bit unit connects a bit line, and the storage bit unit of often going connects a wordline, storage bit unit described in each column
One source electrode line of connection, each described storage bit unit shares one with another adjacent described storage bit unit of its same column
Source electrode line, by the source electrode line, wordline and bit line in the different driving voltage of each storage bit unit loading, realize described in deposit
The reading and writing operation of storage space unit.
Fig. 2 is a kind of structural representation of separate gate storage array, and the separate gate storage array includes multiple in array
The memory cell of arrangement, and for selecting the memory cell and providing multiple bit lines, wordline and the source electrode of drive signal
Line.The memory cell is separate gate flash memory, and storage bit unit described in each column connects a bit line (such as BLn-2, BLn-
1st, BLn, BLn+1, BLn+2), the storage bit unit of often going connects a wordline (such as WLn-1, WLn), and described in each column position is stored
Unit connects a source electrode line (such as Vss), another adjacent described storage position of each described storage bit unit and its same column
One source electrode line of units shared (such as Vss).
In the prior art, in Fig. 2 target storage bit unit s (by taking the first storage bit unit 1 in Fig. 1 as an example)
When, the waveform diagram when separate gate storage array is programmed is as shown in figure 3, the process being programmed is：It is (right in wordline WLn
Answer wordline 16 in Fig. 1) apply a word line programming voltage Vpwl, bit line BLn (correspondence Fig. 1 neutrality lines 14) applies bit line program electricity
Pressure Vdp, source electrode line Vss (source electrode line 17 in correspondence Fig. 1) apply source program voltage Vpp, under the configuration of such voltage, bit line
, all in open mode state, channel electrons are from described plus bit line program electricity for area 12 and the channel region below 11 of corresponding floating boom 15
The Jing transverse electric fields of bit line 14 of pressure Vdp accelerate to corresponding floating boom 15 becomes below thermoelectron, then sends out in the presence of longitudinal electric field
Raw tunnelling, oxidized layer enters floating boom 15, completes programming process.
However, when being programmed to target storage bit unit s, the sector that can be located with target storage bit unit s
(sector) it is unit, source voltage Vpp is applied to all of source electrode line in whole sector so that the non-targeted storage in sector
Bit location produces programming interference.For example, with storage bit unit such as storage bit unit a of target storage bit unit s same row, due to
Target storage bit unit s and storage bit unit a in same sector, common-source voltage Vpp, although WLn-1 is biased to 0V, deposits
The raceway groove of storage space unit a is closed, but still may so be possible to storage with the presence of minority channel leakage stream
Bit location a produces undesirable programming, so as to interfere；In the same manner, with target storage bit unit s with a line storage position
Unit such as storage bit unit b, because target storage bit unit s and storage bit unit b are also in same sector, target storage position list
First s and storage bit unit b common-source voltage Vpp and wordline WLn, although the bit line BLn+1 of storage bit unit b is applied with compared with
High operating voltage, to close storage bit unit b bit line raceway groove, but still may be with the presence of minority channel leakage stream, thus
It is possible to produce memory cell b programming interference.
Therefore, how the programmed method of separate gate storage array that is a kind of noiseless or reducing interference is provided, it has also become this
Art personnel need the problem for solving.
The content of the invention
It is an object of the present invention to provide the programmed method of separate gate storage array that is a kind of noiseless or reducing interference.
To solve above-mentioned technical problem, the present invention provides a kind of programmed method of separate gate storage array, the separate gate
Storage array includes some memory cell, and each described memory cell is comprising two storage position lists for sharing a source electrode line
Unit, the storage bit unit array arrangement, storage bit unit described in each column connects a bit line, and the storage bit unit of often going connects
A wordline is connect, the programmed method includes：
Pre-programming phase is carried out, pair wordline being located with target storage bit unit and with target storage bit unit belongs to same
The wordline that the non-targeted storage bit unit of sector is located applies pre-programmed voltage, pair applies operating voltage with all of bit line, right
The source electrode line of the target storage bit unit place sector applies the operating voltage, with the wordline ditch of non-targeted memory cell
Road produces net many subproducts and gathers；
The stage is programmed, a word line programming voltage is applied to the wordline of the target storage bit unit, to the target
The bit line of storage bit unit applies a bitline programming voltage, and to the source electrode line that the target storage bit unit is located the source is applied
Pole program voltage, to be programmed to the target storage bit unit.
Further, it is described carry out pre-programming phase the step of in, make to belong to same sector with target storage bit unit
The wordline raceway groove of non-targeted storage bit unit there are many subproducts and gather, when being programmed the stage in the target storage bit unit
In step, with the wordline raceway groove of the non-targeted storage bit unit that target storage bit unit belongs to same sector in because of channel leakage stream
There is being combined and offseting for few son in the few sub and described son more for producing, to reduce programming interference.
Further, the raceway groove of all storage bit units is N-type channel, and many sons are hole, and few son is
Electronics.
Further, the pre-programmed voltage is -1V～-2V.
Further, the word line programming voltage is 1V～2V, and the bitline programming voltage is 0V～1V, and the source electrode is compiled
Journey voltage is 5V～10V.
Further, it is described carry out pre-programming phase step before, also include：
One operating voltage, the position to all storage bit units are applied to the wordline that the target storage bit unit is located
Line applies the operating voltage, and to the source electrode line that the target storage bit unit is located the operating voltage is applied.
Further, the operating voltage is chip power supply voltage.
Further, the raceway groove of the storage bit unit is P-type channel, and many sons are electronics, and few son is hole.
Further, the pre-programmed voltage is 1V～2V.
Further, the burst length of the pre-programmed voltage is 1 microsecond～10 microsecond.
Compared with prior art, the programmed method of the separate gate storage array that the present invention is provided has advantages below：This
The programmed method of the separate gate storage array of bright offer, the programmed method of the separate gate storage array is to target storage bit unit
Before being programmed, a pre-programmed voltage is applied to the raceway groove in the sector of target storage bit unit place, deposit the non-targeted
There are many subproducts and gather in the raceway groove of storage space unit, compared with prior art, the programmed method of the present invention is when to target storage bit unit
When being programmed, gather because the raceway groove of non-targeted storage bit unit has many subproducts, when due to being located to target storage bit unit
Source line, wordline or bit line applied voltage in sector causes the raceway groove of the non-targeted storage bit unit in the sector to produce electric leakage
During stream, many sons can occur the compound of few son with few son of leakage current, substantially reduce the leakage current that the few son of raceway groove is constituted, also
Correspondingly reduce the possibility of programming interference.
Description of the drawings
Fig. 1 is the cross-sectional view of the separate gate flash memory of shared source electrode line；
Fig. 2 is the structural representation of separate gate storage array；
Fig. 3 is waveform diagram when separate gate storage array is programmed；
Fig. 4 is the flow chart of the programmed method of separate gate storage array in one embodiment of the invention；
Fig. 5 is waveform diagram when separate gate storage array is programmed in one embodiment of the invention；
Fig. 6 is the energy band schematic diagram of the programmed method of separate gate storage array in one embodiment of the invention.
Specific embodiment
The programmed method of the separate gate storage array of the present invention is described in more detail below in conjunction with schematic diagram, its
In illustrate the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and
Still the advantageous effects of the present invention are realized.Therefore, description below is appreciated that extensively knowing for those skilled in the art
Road, and it is not intended as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In sending out, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to relevant system or relevant business
Limit, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only to those skilled in the art routine work.
Referring to the drawings the present invention more particularly described below by way of example in the following passage.Will according to following explanation and right
Book, advantages and features of the invention is asked to become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and using non-
Accurately ratio, only aids in illustrating the purpose of the embodiment of the present invention to convenience, lucidly.
The core concept of the present invention is, there is provided a kind of programmed method of separate gate storage array, separate gate storage
Array includes some memory cell, and each described memory cell is comprising two storage bit units for sharing a source electrode line, institute
Storage bit unit array arrangement is stated, storage bit unit described in each column connects a bit line, the storage bit unit of often going connects one
Bar wordline, the programmed method includes：
Carry out pre-programming phase, in the sector of target storage bit unit place wordline apply pre-programmed voltage, pair and institute
Some bit lines apply operating voltage, and to the source electrode line in the target storage bit unit place sector operating voltage is applied,
With preventing or reducing the non-targeted storage bit unit is programmed by mistake in programming phases；
The stage is programmed, a word line programming voltage is applied to the wordline of the target storage bit unit, to the target
The bit line of storage bit unit applies a bitline programming voltage, and to the source electrode line that the target storage bit unit is located the source is applied
Pole program voltage, to be programmed to the target storage bit unit.
Several embodiments of the section test structure are exemplified below, with clear explanation present disclosure, it should be clearly that
, present disclosure is not restricted to following examples, and other are by the routine techniques hand of those of ordinary skill in the art
The improvement of section is also within the thought range of the present invention.
In the present embodiment, the memory in separate gate storage array is the separate gate flash memory of shared source electrode line,
Its basic memory cell is storage bit unit, and storage bit unit described in each column connects a source electrode line, each described storage position
Another adjacent described storage bit unit of unit and its same column shares a source electrode line, and its separate gate flash memory is cutd open
Face structure is as shown in figure 1, the structure of separate gate storage array is as shown in Figure 2.
Below incorporated by reference to Fig. 4-Fig. 6, Fig. 4 is the flow process of the programmed method of separate gate storage array in one embodiment of the invention
Figure, Fig. 5 is waveform diagram when separate gate storage array is programmed in one embodiment of the invention, and Fig. 6 is one embodiment of the invention
The energy band schematic diagram of the programmed method of middle separate gate storage array.
Before step S11 is carried out, preferably one is applied to wordline WLn that target storage bit unit s is located and worked
Voltage Vdd, all bit lines apply operating voltage Vdd, and the source electrode line Vss that target storage bit unit s is located is applied
Plus operating voltage Vdd, it is that step S11 and step S12 are prepared so that step S11 and step S12 energy with drive circuit
It is smoothed out.Now, wordline WLn at the target storage bit unit s place, bit line BLn, source electrode line Vss apply the work
Make voltage Vdd；With the storage bit unit of the target storage bit unit s same column, by taking storage bit unit a as an example, storage bit unit a
Wordline WLn-1 it is unloaded, bit line BLn applies operating voltage Vdd, and source electrode line Vss applies operating voltage Vdd；With institute
The storage bit unit of target storage bit unit s colleague is stated, by taking storage bit unit b as an example, wordline WLn of storage bit unit b applies
Operating voltage Vdd, bit line BLn+1 applies operating voltage Vdd, and source electrode line Vss applies operating voltage Vdd, such as
Shown in Fig. 5.In the present embodiment, the raceway groove of the storage bit unit is N-type channel, so operating voltage Vdd is chip
Supply voltage, representative value is 3V, but is not limited to 3V, as long as the voltage of chip normal work can be made.
Then, step S11 is carried out, carries out pre-programming phase, the wordline in the sector of target storage bit unit s place is applied
The pre-programmed voltage Vbe, to all of bit line the pre-programmed voltage Vbe is applied, and target storage bit unit s is located
Source electrode line in sector applies operating voltage Vdd, and the raceway groove of the non-targeted storage bit unit has net many subproducts and gathers.
Now, wordline WLn that target storage bit unit s is located applies the pre-programmed voltage Vbe, bit line BLn, source electrode line Vss
Apply operating voltage Vdd；With the storage bit unit of the target storage bit unit s same column, it is with storage bit unit a
Example, wordline WLn-1 of storage bit unit a applies the pre-programmed voltage Vbe, and bit line BLn applies operating voltage Vdd, source
Polar curve Vss applies operating voltage Vdd；The storage bit unit gone together with target storage bit unit s, with storage bit unit
As a example by b, wordline WLn of storage bit unit b applies the pre-programmed voltage Vbe, and bit line BLn+1 applies operating voltage Vdd,
Source electrode line Vss applies operating voltage Vdd, as shown in Figure 5.In the present embodiment, the raceway groove of the storage bit unit is N-type
Raceway groove, so the pre-programmed voltage Vbe is low-voltage, then in storage bit unit a, because wordline WLn-1 applies a low electricity
The pre-programmed voltage Vbe of pressure, so forming void coalescence in the raceway groove of storage bit unit a, now hole is son more, in the same manner
Also void coalescence is formed in the raceway groove of storage bit unit b.Preferably, the pre-programmed voltage Vbe is -1V～-2V, can guarantee that non-
There are enough many subproducts and gather in the raceway groove of target storage bit unit, to avoid programming by mistake in step s 12.
Then, step S12 is carried out, wordline WLn of target storage bit unit s applies a word line programming voltage Vpwl,
Remaining wordline is unloaded, and the bit line BLn of target storage bit unit s applies a bitline programming voltage Vdp, and remaining bit line is applied
Plus operating voltage Vdd, source electrode line Vss applyings source program voltage Vpp that target storage bit unit s is located,
When the non-targeted storage bit unit due to it is impacted and produce leakage current when, the generation in its wordline raceway groove it is few son with step
The many sons produced in rapid S02 are offseted.Now, wordline WLn that target storage bit unit s is located applies the word line program
Voltage Vpwl, bit line BLn apply the bitline programming voltage Vdp, and source electrode line Vss applies source program voltage Vpp, institute
Target storage bit unit s is stated in programming state；With the storage bit unit of the target storage bit unit s same column, to store position
As a example by unit a, wordline WLn-1 of storage bit unit a is unloaded, and bit line BLn applies operating voltage Vdd, and source electrode line Vss applies
Source program voltage Vpp, when storage bit unit a due to it is impacted and when producing leakage current, due to institute in the present embodiment
The raceway groove for stating storage bit unit is N-type channel, so few son of the generation in the raceway groove of storage bit unit a is electronics, few son
There is the compound (e- of few son in the net many sons (hole) that can and produce in the wordline raceway groove of storage bit unit a in step s 11
Hrecombine), the leakage current that with schematic diagram, can thus significantly reduce the few son composition of raceway groove as shown in Figure 6, also with regard to phase
Reduce the possibility of programming interference with answering；The storage bit unit gone together with target storage bit unit s, with storage bit unit
As a example by b, wordline WLn of storage bit unit b applies the word line programming voltage Vpwl, and bit line BLn+1 applies the operating voltage
Vdd, source electrode line Vss apply source program voltage Vpp, as shown in figure 5, when storage bit unit b is due to impacted and produce
During leakage current, because the raceway groove of the storage bit unit in the present embodiment is N-type channel, so the raceway groove of storage bit unit b
In few son of generation be electronics, it is net many that few son can and be produced in step s 11 in the wordline raceway groove of storage bit unit b
There is few son and be combined in sub (hole), correspondingly reduce the possibility of programming interference.In the present embodiment, the word line program electricity
Press as 1V～2V, the bitline programming voltage is 0V～1V, the source program voltage is 5V～10V, the pre-programmed voltage
Burst length be 1 microsecond～10 microsecond.
In the present invention, the programmed method of separate gate storage array is not limited to above-described embodiment, for example, the storage position
The raceway groove of unit is P-type channel, because the operating voltage and program voltage of P-type channel are negative pressure, as long as then controlling in step s 11
It is positive voltage to make the pre-programmed voltage, preferably, the pre-programmed voltage is 1V～2V so that the ditch of the storage bit unit
Enough electronics aggregations are formed in road, now many sons are electronics, then in step s 12, when to target storage bit unit s volume
Cheng Shi, if producing leakage current in the raceway groove of storage bit unit a or storage bit unit b, the few son in raceway groove is hole, this
When, there is few son and be combined in hole, the beneficial effect for avoiding interference can be also reached, also at this with the electronics for producing in step s 11
Within the thought range of invention.In addition, the structure of the separate gate storage array is also not necessarily limited to the structure of above-described embodiment, may be used also
Think the separate gate storage array of common word line, i.e., often the storage bit unit of row also includes a control gate, often capable institute
State storage bit unit connection one and control grid line, the storage bit unit of often going connects a wordline, each described storage bit unit
A wordline is shared with another adjacent described storage bit unit of its same column, as long as compiling to target storage bit unit
Before journey, a pre-programmed voltage is applied by the raceway groove to the non-targeted storage bit unit, so that non-targeted storage
There are many subproducts and gather in the raceway groove of bit location, when being programmed to the target storage bit unit, the non-targeted storage bit unit
Raceway groove in few sub and described many sons of generation occur compound and offset, can also reach the beneficial effect for avoiding interference, also
Within the thought range of the present invention.
In sum, the present invention provides a kind of programmed method of separate gate storage array, the separate gate storage array bag
Containing some memory cell, each described memory cell is comprising two storage bit units for sharing a source electrode line, the storage
Bit cell array is arranged, and storage bit unit described in each column connects a bit line, and the storage bit unit of often going connects a wordline,
The programmed method includes：The separate gate storage array includes some memory cell, and each described memory cell includes two
The individual storage bit unit for sharing a source electrode line, the storage bit unit array arrangement, storage bit unit connection one described in each column
Bar bit line, the storage bit unit of often going connects a wordline, and the programmed method includes：Pre-programming phase is carried out, to target
Wordline in the sector of storage bit unit place applies pre-programmed voltage, pair applies operating voltage with all of bit line, to the mesh
Source electrode line in mark storage bit unit place sector applies the operating voltage, to prevent or reduce in programming phases to described non-
Target storage bit unit is programmed by mistake；The stage is programmed, word line program electricity is applied to the wordline of the target storage bit unit
Pressure, applies a bitline programming voltage, the source being located to the target storage bit unit to the bit line of the target storage bit unit
Polar curve applies the source program voltage, to be programmed to the target storage bit unit.Compared with prior art, the present invention
The programmed method of the separate gate storage array of offer has advantages below：
The programmed method of the separate gate storage array that the present invention is provided, the programmed method of the separate gate storage array is to mesh
Before mark storage bit unit is programmed, a pre-programmed voltage is applied to the raceway groove in the sector of target storage bit unit place, made
There are many subproducts and gather in the raceway groove of the non-targeted storage bit unit, compared with prior art, the programmed method of the present invention is when to mesh
When mark storage bit unit is programmed, gather because the raceway groove of non-targeted storage bit unit has many subproducts, when due to depositing to target
Source line, wordline or bit line applied voltage in the sector of storage space unit place causes the non-targeted storage bit unit in the sector
When raceway groove produces leakage current, many sons can occur the compound of few son with few son of leakage current, substantially reduce the few son of raceway groove and constitute
Leakage current, also just correspondingly reduce the possibility of programming interference.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of programmed method of separate gate storage array, the separate gate storage array includes some memory cell, each institute
Memory cell is stated comprising two storage bit units for sharing a source electrode line, the storage bit unit array arrangement, each column institute
State storage bit unit and connect a bit line, the storage bit unit of often going connects a wordline, and the programmed method includes：
Pre-programming phase is carried out, pre-programmed voltage is applied to the wordline in the sector of target storage bit unit place, to all of position
Line applies operating voltage, applies the operating voltage to the source electrode line in the target storage bit unit place sector, to prevent
Or reduce in programming phases to the programming by mistake of non-targeted storage bit unit；
The stage is programmed, a word line programming voltage is applied to the wordline of the target storage bit unit, the target is stored
The bit line of bit location applies a bitline programming voltage, and to the source electrode line that the target storage bit unit is located source program electricity is applied
Pressure, to be programmed to the target storage bit unit.
2. the programmed method of separate gate storage array as claimed in claim 1, it is characterised in that carry out pre-programmed rank described
In the step of section, there is son more in the wordline raceway groove for making the non-targeted storage bit unit for belonging to same sector with target storage bit unit
Accumulation, when in the step of target storage bit unit is programmed the stage, with target storage bit unit same sector is belonged to
Non-targeted storage bit unit wordline raceway groove in there is the compound of few son because of channel leakage raw few sub and described many sons of miscarrying
And offset, to reduce programming interference.
3. the programmed method of separate gate storage array as claimed in claim 2, it is characterised in that all storage bit units
Raceway groove be N-type channel, many sons are hole, and few son is electronics.
4. the programmed method of separate gate storage array as claimed in claim 3, it is characterised in that the pre-programmed voltage for-
1V～-2V.
5. the programmed method of separate gate storage array as claimed in claim 3, it is characterised in that the word line programming voltage is
1V～2V, the bitline programming voltage is 0V～1V, and the source program voltage is 5V～10V.
6. the programmed method of separate gate storage array as claimed in claim 3, it is characterised in that carry out pre-programmed rank described
Before section step, also include：
One operating voltage is applied to the wordline that the target storage bit unit is located, the bit line of all storage bit units is applied
Plus the operating voltage, the operating voltage is applied to the source electrode line that the target storage bit unit is located.
7. the programmed method of separate gate storage array as claimed in claim 6, it is characterised in that the operating voltage is chip
Supply voltage.
8. the programmed method of separate gate storage array as claimed in claim 2, it is characterised in that the ditch of the storage bit unit
Road is P-type channel, and many sons are electronics, and few son is hole.
9. the programmed method of separate gate storage array as claimed in claim 8, it is characterised in that the pre-programmed voltage is 1V
～2V.
10. the programmed method of the separate gate storage array as described in any one in claim 1-2, it is characterised in that described
The burst length of pre-programmed voltage is 1 microsecond～10 microsecond.
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| CN201210577034.8A CN103106922B (en) | 2012-12-26 | 2012-12-26 | Programming method for separating grid memory array |
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| CN201210577034.8A CN103106922B (en) | 2012-12-26 | 2012-12-26 | Programming method for separating grid memory array |
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| CN103106922B true CN103106922B (en) | 2017-05-10 |
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| CN103137181B (en) * | 2013-02-25 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Memory, the programmed method of storage array and voltage provide system |
| CN106158027B (en) * | 2015-04-09 | 2020-02-07 | 硅存储技术公司 | System and method for programming split-gate non-volatile memory cells |
| CN108257638B (en) * | 2018-01-18 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | Programming method suitable for split gate flash memory |
| CN108648777B (en) * | 2018-05-10 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Programming sequential circuit and method of double-separation gate flash memory |
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| CN102341865A (en) * | 2009-04-30 | 2012-02-01 | 力晶股份有限公司 | Programming method for nand flash memory device |
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| WO2007117869A2 (en) * | 2006-03-30 | 2007-10-18 | Sandisk Corporation | Self-boosting system with suppression of high lateral electric fields |
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| CN102341865A (en) * | 2009-04-30 | 2012-02-01 | 力晶股份有限公司 | Programming method for nand flash memory device |
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