CN103106922A - Programming method for separating grid memory array - Google Patents
Programming method for separating grid memory array Download PDFInfo
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- CN103106922A CN103106922A CN2012105770348A CN201210577034A CN103106922A CN 103106922 A CN103106922 A CN 103106922A CN 2012105770348 A CN2012105770348 A CN 2012105770348A CN 201210577034 A CN201210577034 A CN 201210577034A CN 103106922 A CN103106922 A CN 103106922A
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Abstract
The invention discloses a programming method for separating a grid memory array. The programming method comprises the following steps of: at a preprogramming stage, applying a preprogramming voltage to word lines within a sector where a target memory bit unit is arranged, applying a work voltage to all the word lines, and applying the work voltage to source electrode wires within the sector where the target memory bit unit is arranged, so that the mis-programming to a non-target memory bit unit in the stage of programming can be avoided or reduced; and at a programming stage, applying a word line programming voltage to the word lines of the target memory bit unit, applying a bit line programming voltage to a bit line of the target memory bit unit, applying the source electrode programming voltage to the source electrode wires of the target memory bit unit, and programming the target memory bit unit. According to the programming method for separating the grid memory array, the interference to the non-target memory bit unit can be reduced when the target memory bit unit is programmed.
Description
Technical field
The present invention relates to the memory technology field, particularly relate to a kind of programmed method of separate gate storage array.
Background technology
Flash memory (flash memory) is as a kind of integrated circuit memory devices, because it has the function of electrically-erasable storage information, and after outage, canned data can not lost, therefore, flash memory is widely used in as in the electronic products such as portable computer, mobile phone, digital music player.Common, difference according to grid structure, flash memory is divided into two types of piled grids flash memory and Frash memory in separate grids, these two kinds of flash memories all need storage unit is arranged with the array that is fit to itself operate, and each storage bit unit all is used for storing the data of single position.
Fig. 1 is a kind of cross-sectional view of separate gate flash memory of shared source electrode line, Fig. 1 is a storage unit, have two storage bit unit in a described storage unit, be respectively the first storage bit unit 1 and the second storage bit unit 2, each storage bit unit includes a word line 16, bit line 14, floating boom 15, bitline regions 12 is positioned at the substrate 10 under word line 16, the first storage bit unit 1 and the second storage bit unit 2 are shared a source electrode line 17, source area 13 is positioned at the substrate 10 under source electrode line 17, has channel region 11 between bitline regions 12 and source area 13, the first storage bit unit 1 and the second storage bit unit 2 of sharing a source electrode line 17 are symmetrical.A plurality of above-mentioned storage bit unit array arrangements, form the separate gate storage array, wherein, the described storage bit unit of every row connects a bit lines, the described storage bit unit of every row connects a word line, the described storage bit unit of every row connects a source electrode line, the described storage bit unit that another of each described storage bit unit and its same column is adjacent shares a source electrode line, load different driving voltages by described source electrode line, word line and bit line in each storage bit unit, realize the reading and writing operation of described storage bit unit.
Fig. 2 is a kind of structural representation of separate gate storage array, and described separate gate storage array comprises a plurality of storage unit that are arranged in array, and is used for selecting described storage unit and multiple bit lines, word line and the source electrode line that drives signal being provided.Described storage unit is separate gate flash memory, the described storage bit unit of every row connects a bit lines (as BLn-2, BLn-1, BLn, BLn+1, BLn+2), the described storage bit unit of every row connects a word line (as WLn-1, WLn), the described storage bit unit of every row connects a source electrode line (as Vss), and the described storage bit unit that another of each described storage bit unit and its same column is adjacent shares a source electrode line (as Vss).
in the prior art, when to the target storage bit unit s in Fig. 2 (the first storage bit unit 1 in Fig. 1 is as example), waveform schematic diagram during this separate gate storage array programming as shown in Figure 3, the process of programming is: apply a word line program voltage Vpwl at word line WLn (word line 16 in corresponding diagram 1), bit line BLn (corresponding diagram 1 neutrality line 14) applies a bit line program voltage Vdp, source electrode line Vss (in corresponding diagram 1, source electrode line 17) applies one source pole program voltage Vpp, under voltage configures like this, channel region 11 below bitline regions 12 and corresponding floating boom 15 all is in the open mode state, channel electrons becomes thermoelectron from the described bit line 14 that adds bit line program voltage Vdp below transverse electric field accelerates to corresponding floating boom 15, under the effect of longitudinal electric field, tunnelling occurs again, enter floating boom 15 through oxide layer, complete programming process.
Yet, when target storage bit unit s is programmed, can apply source voltage Vpp to source electrode lines all in whole sector take the sector (sector) at target storage bit unit s place as unit, make the non-target storage bit unit the sector in produce the interference of programming.For example, storage bit unit such as storage bit unit a with the same row of target storage bit unit s, due to target storage bit unit s and storage bit unit a in same sector, common-source voltage Vpp, although WLn-1 is biased to 0V, the raceway groove of storage bit unit a is in closed condition, but still may have minority channel leakage stream to exist, so just might produce storage bit unit a and do not wish the programming that occurs, thereby cause interference; In like manner, with storage bit unit such as the storage bit unit b of target storage bit unit s with delegation, due to target storage bit unit s and storage bit unit b also in same sector, target storage bit unit s and storage bit unit b common-source voltage Vpp and word line WLn, although the bit line BLn+1 to storage bit unit b has applied higher operating voltage, closing storage bit unit b bit line raceway groove, but still may there be minority channel leakage stream to exist, so just might produces the interference of programming to storage unit b.
Therefore, how to provide a kind of programmed method of separate gate storage array of noiseless or reduce disturbance, become the problem that those skilled in the art need to solve.
Summary of the invention
The object of the invention is to, a kind of programmed method of separate gate storage array of noiseless or reduce disturbance is provided.
For solving the problems of the technologies described above, the invention provides a kind of programmed method of separate gate storage array, described separate gate storage array comprises some storage unit, each described storage unit all comprises two storage bit unit that share a source electrode line, described storage bit unit array arrangement, the described storage bit unit of every row connects a bit lines, and the described storage bit unit of every row connects a word line, and described programmed method comprises:
Carry out the pre-programmed stage, to applying pre-programmed voltage with the word line at target storage bit unit place and with word line that the target storage bit unit belongs to the non-target storage bit unit place of same sector, to applying operating voltage with all bit line, source electrode line to sector, described target storage bit unit place applies described operating voltage, produces clean many subproducts with the word wire channel at non-Destination Storage Unit poly-;
Carry out programming phases, word line to described target storage bit unit applies a word line program voltage, bit line to described target storage bit unit applies a bit line program voltage, source electrode line to described target storage bit unit place applies described source program voltage, so that described target storage bit unit is programmed.
Further, in described step of carrying out the pre-programmed stage, make the word wire channel that belongs to the non-target storage bit unit of same sector with the target storage bit unit exist many subproducts poly-, when in described target storage bit unit is carried out the step of programming phases, belong to the target storage bit unit compound the offseting that few son occurs for few son of giving birth to because of the channel leakage miscarriage in the word wire channel of non-target storage bit unit of same sector and described many sons, with the reduction programming interference.
Further, the raceway groove of all described storage bit unit is the N-type raceway groove, and described many sons are the hole, and described few son is electronics.
Further, described pre-programmed voltage be-1V～-2V.
Further, described word line program voltage is 1V～2V, and described bit line program voltage is 0V～1V, and described source program voltage is 5V～10V.
Further, described carry out pre-programmed stage step before, also comprise:
Word line to described target storage bit unit place applies an operating voltage, and the bit line of all described storage bit unit is applied described operating voltage, and the source electrode line at described target storage bit unit place is applied described operating voltage.
Further, described operating voltage is chip power supply voltage.
Further, the raceway groove of described storage bit unit is P type raceway groove, and described many sons are electronics, and described few son is the hole.
Further, described pre-programmed voltage is 1V～2V.
Further, the burst length of described pre-programmed voltage is 1 microsecond～10 microseconds.
compared with prior art, the programmed method of separate gate storage array provided by the invention has the following advantages: the programmed method of separate gate storage array provided by the invention, the programmed method of this separate gate storage array is before programming to the target storage bit unit, raceway groove in sector, target storage bit unit place is applied a pre-programmed voltage, make the raceway groove of described non-target storage bit unit exist many subproducts poly-, compared with prior art, programmed method of the present invention is when programming to the target storage bit unit, because the raceway groove of non-target storage bit unit exists many subproducts poly-, when due to the source line in sector, target storage bit unit place, when word line or bit line apply raceway groove that voltage causes the non-target storage bit unit in described sector and produce leakage current, the compound of few son can occur with few son of leakage current in described many sons, significantly reduce the leakage current that the few son of raceway groove consists of, also just correspondingly reduced the possibility of programming interference.
Description of drawings
Fig. 1 is the cross-sectional view of the separate gate flash memory of shared source electrode line;
Fig. 2 is the structural representation of separate gate storage array;
Waveform schematic diagram when Fig. 3 is the programming of separate gate storage array;
Fig. 4 is the process flow diagram of the programmed method of separate gate storage array in one embodiment of the invention;
Fig. 5 is the waveform schematic diagram when in one embodiment of the invention, the separate gate storage array is programmed;
Fig. 6 be separate gate storage array in one embodiment of the invention programmed method can be with schematic diagram.
Embodiment
Be described in more detail below in conjunction with the programmed method of schematic diagram to separate gate storage array of the present invention, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example according to the restriction of relevant system or relevant business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
With way of example, the present invention is described more specifically with reference to accompanying drawing in the following passage.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, a kind of programmed method of separate gate storage array is provided, described separate gate storage array comprises some storage unit, each described storage unit all comprises two storage bit unit that share a source electrode line, described storage bit unit array arrangement, the described storage bit unit of every row connects a bit lines, and the described storage bit unit of every row connects a word line, and described programmed method comprises:
Carry out the pre-programmed stage, word line in sector, target storage bit unit place is applied pre-programmed voltage, to applying operating voltage with all bit line, source electrode line in sector, described target storage bit unit place is applied described operating voltage, to prevent or to reduce in programming phases the programming of described non-target storage bit unit mistake;
Carry out programming phases, word line to described target storage bit unit applies a word line program voltage, bit line to described target storage bit unit applies a bit line program voltage, source electrode line to described target storage bit unit place applies described source program voltage, so that described target storage bit unit is programmed.
Below enumerate several embodiment of described section test structure, to clearly demonstrate content of the present invention, will be clear that content of the present invention is not restricted to following examples, the improvement of other routine techniques means by those of ordinary skills is also within thought range of the present invention.
In the present embodiment, storer in the separate gate storage array is for sharing the separate gate flash memory of source electrode line, its basic storage unit is storage bit unit, the described storage bit unit of every row connects a source electrode line, the described storage bit unit that another of each described storage bit unit and its same column is adjacent shares a source electrode line, the cross-section structure of its separate gate flash memory as shown in Figure 1, the structure of separate gate storage array is as shown in Figure 2.
Below please in conjunction with Fig. 4-Fig. 6, Fig. 4 is the process flow diagram of the programmed method of separate gate storage array in one embodiment of the invention, Fig. 5 is the waveform schematic diagram in separate gate storage array when programming in one embodiment of the invention, Fig. 6 be separate gate storage array in one embodiment of the invention programmed method can be with schematic diagram.
Carrying out between step S11, better word line WLn to described target storage bit unit s place applies an operating voltage Vdd, all described bit lines apply described operating voltage Vdd, the source electrode line Vss at described target storage bit unit s place applies described operating voltage Vdd, with driving circuit, for step S11 and step S12 prepare, make step S11 and step S12 to carry out smoothly.At this moment, word line WLn, bit line BLn, the source electrode line Vss at described target storage bit unit s place all apply described operating voltage Vdd; With the storage bit unit of described target storage bit unit s same column, take storage bit unit a as example, the word line WLn-1 of storage bit unit a is unloaded, and bit line BLn applies described operating voltage Vdd, and source electrode line Vss applies described operating voltage Vdd; The storage bit unit of going together with described target storage bit unit s, take storage bit unit b as example, the word line WLn of storage bit unit b applies described operating voltage Vdd, and bit line BLn+1 applies described operating voltage Vdd, source electrode line Vss applies described operating voltage Vdd, as shown in Figure 5.In the present embodiment, the raceway groove of described storage bit unit is the N-type raceway groove, so described operating voltage Vdd is chip power supply voltage, representative value is 3V, but is not limited to 3V, as long as can make the voltage of chip normal operation.
Then, carry out step S11, carry out the pre-programmed stage, word line in sector, target storage bit unit s place is applied described pre-programmed voltage Vbe, all bit lines are applied described pre-programmed voltage Vbe, source electrode line in sector, described target storage bit unit s place is applied described operating voltage Vdd, and the raceway groove of described non-target storage bit unit exists clean many subproducts poly-.At this moment, the word line WLn at described target storage bit unit s place applies described pre-programmed voltage Vbe, and bit line BLn, source electrode line Vss all apply described operating voltage Vdd; With the storage bit unit of described target storage bit unit s same column, take storage bit unit a as example, the word line WLn-1 of storage bit unit a applies described pre-programmed voltage Vbe, and bit line BLn applies described operating voltage Vdd, and source electrode line Vss applies described operating voltage Vdd; The storage bit unit of going together with described target storage bit unit s, take storage bit unit b as example, the word line WLn of storage bit unit b applies described pre-programmed voltage Vbe, and bit line BLn+1 applies described operating voltage Vdd, source electrode line Vss applies described operating voltage Vdd, as shown in Figure 5.In the present embodiment, the raceway groove of described storage bit unit is the N-type raceway groove, so described pre-programmed voltage Vbe is low-voltage, in storage bit unit a, apply the described pre-programmed voltage Vbe of a low-voltage due to word line WLn-1, so form void coalescence in the raceway groove of storage bit unit a, the hole for how sub, in like manner also forms void coalescence in the raceway groove of storage bit unit b at this moment.Better, described pre-programmed voltage Vbe is-1V～-2V, can guarantee that the raceway groove of non-target storage bit unit exists abundant many subproducts poly-, to avoid the mistake programming in step S12.
Then, carry out step S12, the word line WLn of described target storage bit unit s applies a word line program voltage Vpwl, remaining word line is unloaded, the bit line BLn of described target storage bit unit s applies a bit line program voltage Vdp, remaining bit line applies described operating voltage Vdd, the source electrode line Vss at described target storage bit unit s place applies described source program voltage Vpp, due to influenced when producing leakage current, few son of the generation in its word wire channel offsets with the many sons that produce in step S02 when described non-target storage bit unit.at this moment, the word line WLn at described target storage bit unit s place applies described word line program voltage Vpwl, bit line BLn applies described bit line program voltage Vdp, and source electrode line Vss all applies described source program voltage Vpp, and described target storage bit unit s is in programming state, storage bit unit with described target storage bit unit s same column, take storage bit unit a as example, the word line WLn-1 of storage bit unit a is unloaded, bit line BLn applies described operating voltage Vdd, source electrode line Vss applies described source program voltage Vpp, as storage bit unit a due to influenced when producing leakage current, because the raceway groove of described storage bit unit in the present embodiment is the N-type raceway groove, so few son of the generation in the raceway groove of storage bit unit a is electronics, few sub compound (e-hrecombine) occurs in clean many sons (hole) of should meeting of few son and producing in the word wire channel of storage bit unit a in step S11, as shown in Figure 6 can be with schematic diagram, so just significantly reduced the leakage current that the few son of raceway groove consists of, also just correspondingly reduced the possibility of programming interference, the storage bit unit of going together with described target storage bit unit s, take storage bit unit b as example, the word line WLn of storage bit unit b applies described word line program voltage Vpwl, bit line BLn+1 applies described operating voltage Vdd, source electrode line Vss applies described source program voltage Vpp, as shown in Figure 5, as storage bit unit b due to influenced when producing leakage current, because the raceway groove of described storage bit unit in the present embodiment is the N-type raceway groove, so few son of the generation in the raceway groove of storage bit unit b is electronics, clean many sons (hole) of should meeting of few son and producing in the word wire channel of storage bit unit b in step S11 occur few sub compound, correspondingly reduced the possibility of programming interference.In the present embodiment, described word line program voltage is 1V～2V, and described bit line program voltage is 0V～1V, and described source program voltage is 5V～10V, and the burst length of described pre-programmed voltage is 1 microsecond～10 microseconds.
in the present invention, the programmed method of separate gate storage array is not limited to above-described embodiment, for example, the raceway groove of described storage bit unit is P type raceway groove, because the operating voltage of P type raceway groove and program voltage are negative pressure, be positive voltage as long as control described pre-programmed voltage in step S11, better, described pre-programmed voltage is 1V～2V, make and form enough electronics in the raceway groove of described storage bit unit and assemble, this moment, many sons were electronics, in step S12, when to described target storage bit unit s programming, if produce leakage current in the raceway groove of storage bit unit a or storage bit unit b, the few son in raceway groove is the hole, at this moment, the hole occurs few sub compound with the electronics that produces in step S11, also can reach the beneficial effect that avoids interference, also within thought range of the present invention.in addition, the structure of described separate gate storage array also is not limited to the structure of above-described embodiment, can also be the separate gate storage array of common word line, the described storage bit unit that is every row also comprises a control gate, the described storage bit unit of every row connects one and controls grid line, the described storage bit unit of every row connects a word line, the described storage bit unit that another of each described storage bit unit and its same column is adjacent shares a word line, as long as before the target storage bit unit is programmed, apply a pre-programmed voltage by the raceway groove to described non-target storage bit unit, thereby the raceway groove that makes described non-target storage bit unit exists many subproducts poly-, when described target storage bit unit is programmed, few son of the generation in the raceway groove of described non-target storage bit unit and described many sons occur compound and offset, also can reach the beneficial effect that avoids interference, also within thought range of the present invention.
in sum, the invention provides a kind of programmed method of separate gate storage array, described separate gate storage array comprises some storage unit, each described storage unit all comprises two storage bit unit that share a source electrode line, described storage bit unit array arrangement, the described storage bit unit of every row connects a bit lines, the described storage bit unit of every row connects a word line, described programmed method comprises: described separate gate storage array comprises some storage unit, each described storage unit all comprises two storage bit unit that share a source electrode line, described storage bit unit array arrangement, the described storage bit unit of every row connects a bit lines, the described storage bit unit of every row connects a word line, described programmed method comprises: carry out the pre-programmed stage, word line in sector, target storage bit unit place is applied pre-programmed voltage, to applying operating voltage with all bit line, source electrode line in sector, described target storage bit unit place is applied described operating voltage, to prevent or to reduce in programming phases the programming of described non-target storage bit unit mistake, carry out programming phases, word line to described target storage bit unit applies a word line program voltage, bit line to described target storage bit unit applies a bit line program voltage, source electrode line to described target storage bit unit place applies described source program voltage, so that described target storage bit unit is programmed.Compared with prior art, the programmed method of separate gate storage array provided by the invention has the following advantages:
the programmed method of separate gate storage array provided by the invention, the programmed method of this separate gate storage array is before programming to the target storage bit unit, raceway groove in sector, target storage bit unit place is applied a pre-programmed voltage, make the raceway groove of described non-target storage bit unit exist many subproducts poly-, compared with prior art, programmed method of the present invention is when programming to the target storage bit unit, because the raceway groove of non-target storage bit unit exists many subproducts poly-, when due to the source line in sector, target storage bit unit place, when word line or bit line apply raceway groove that voltage causes the non-target storage bit unit in described sector and produce leakage current, the compound of few son can occur with few son of leakage current in described many sons, significantly reduce the leakage current that the few son of raceway groove consists of, also just correspondingly reduced the possibility of programming interference.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of claim of the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the programmed method of a separate gate storage array, described separate gate storage array comprises some storage unit, each described storage unit all comprises two storage bit unit that share a source electrode line, described storage bit unit array arrangement, the described storage bit unit of every row connects a bit lines, the described storage bit unit of every row connects a word line, and described programmed method comprises:
Carry out the pre-programmed stage, word line in sector, target storage bit unit place is applied pre-programmed voltage, all bit lines are applied operating voltage, source electrode line in sector, described target storage bit unit place is applied described operating voltage, to prevent or to reduce in programming phases the programming of described non-target storage bit unit mistake;
Carry out programming phases, word line to described target storage bit unit applies a word line program voltage, bit line to described target storage bit unit applies a bit line program voltage, source electrode line to described target storage bit unit place applies described source program voltage, so that described target storage bit unit is programmed.
2. the programmed method of separate gate storage array as claimed in claim 1, it is characterized in that, in described step of carrying out the pre-programmed stage, make the word wire channel that belongs to the non-target storage bit unit of same sector with the target storage bit unit exist many subproducts poly-, when in described target storage bit unit is carried out the step of programming phases, belong to the target storage bit unit compound the offseting that few son occurs for few son of giving birth to because of the channel leakage miscarriage in the word wire channel of non-target storage bit unit of same sector and described many sons, with the reduction programming interference.
3. as the programmed method of the described separate gate storage array of any one in claim 1-2, it is characterized in that, the raceway groove of all described storage bit unit is the N-type raceway groove, and described many sons are the hole, and described few son is electronics.
4. the programmed method of separate gate storage array as claimed in claim 3, is characterized in that, described pre-programmed voltage is-and 1V～-2V.
5. the programmed method of separate gate storage array as claimed in claim 3, is characterized in that, described word line program voltage is 1V～2V, and described bit line program voltage is 0V～1V, and described source program voltage is 5V～10V.
6. the programmed method of separate gate storage array as claimed in claim 3, is characterized in that, described carry out pre-programmed stage step before, also comprise:
Word line to described target storage bit unit place applies an operating voltage, and the bit line of all described storage bit unit is applied described operating voltage, and the source electrode line at described target storage bit unit place is applied described operating voltage.
7. the programmed method of separate gate storage array as claimed in claim 6, is characterized in that, described operating voltage is chip power supply voltage.
8. as the programmed method of the described separate gate storage array of any one in claim 1-2, it is characterized in that, the raceway groove of described storage bit unit is P type raceway groove, and described many sons are electronics, and described few son is the hole.
9. the programmed method of separate gate storage array as claimed in claim 8, is characterized in that, described pre-programmed voltage is 1V～2V.
10. as the programmed method of the described separate gate storage array of any one in claim 1-2, it is characterized in that, the burst length of described pre-programmed voltage is 1 microsecond～10 microseconds.
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| CN103137181A (en) * | 2013-02-25 | 2013-06-05 | 上海宏力半导体制造有限公司 | Memory, memory array programming method, and voltage supply system |
| CN103137181B (en) * | 2013-02-25 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Memory, the programmed method of storage array and voltage provide system |
| CN106158027A (en) * | 2015-04-09 | 2016-11-23 | 硅存储技术公司 | For to the system and method separating the programming of grating Nonvolatile memery unit |
| US10079061B2 (en) | 2015-04-09 | 2018-09-18 | Silicon Storage Technology, Inc. | System and method for programming split-gate, non-volatile memory cells |
| CN106158027B (en) * | 2015-04-09 | 2020-02-07 | 硅存储技术公司 | System and method for programming split-gate non-volatile memory cells |
| CN108257638A (en) * | 2018-01-18 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | A kind of programmed method suitable for separate gate flash memory |
| CN108257638B (en) * | 2018-01-18 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | Programming method suitable for split gate flash memory |
| CN108648777A (en) * | 2018-05-10 | 2018-10-12 | 上海华虹宏力半导体制造有限公司 | The program timing sequence circuit and method of double separate gate flash memories |
| CN108648777B (en) * | 2018-05-10 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Programming sequential circuit and method of double-separation gate flash memory |
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| CN103106922B (en) | 2017-05-10 |
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