CN110083563A - A kind of arbitration circuit for realizing fair arbitration based on circular priority - Google Patents
A kind of arbitration circuit for realizing fair arbitration based on circular priority Download PDFInfo
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- G06F13/4031—Coupling between buses using bus bridges with arbitration
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Abstract
The invention discloses a kind of arbitration circuits that fair arbitration is realized based on circular priority, belong to technical field of integrated circuits, it is made of several arbitration units, the arbitration unit includes priority selector unit, request generates unit and response generates unit, the characteristics of circuit is by introducing counter, being alternately produced 0 and 1 using counter has judged odd even time conflict, and force to draw high or drag down the metastable state to interfere rest-set flip-flop using output result control, reduce the delay of entire circuit.Two switches while effect simultaneously ensures the stability of circuit, two-way to ensure that metastable state property is disturbed, is not in the indefinite situation of result, significantly enhances the robustness of circuit.Integrated circuit reduces the number of gate level circuit, reduces the use of time delay module, significantly reduces power consumption, reduces delay, reduces circuit area, realizes low-power consumption, few to postpone, the stable fair arbitration circuit of the small performance of area.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of to realize the secondary of fair arbitration based on circular priority
Cut out circuit.
Background technique
With the continuous development of integrated circuit, integrated level is improved, and circuit expands, and conventional synchronous circuit is brought by clock signal
Clock skew, the problems such as signal delay, power consumption is big constantly highlights.The advantage of asynchronous circuit gradually embodies, asynchronous electricity
In road each system due to can not reference clock signal work, between each module often through shake hands complete.
The case where usually will appear multiple events in asynchronous circuit while requesting, need a kind of arbitration of justice this when
Mode realizes fair arbitration.Circular priority diagnostic method in reference bus arbitration, as shown in Figure 1, priority therein is
It dynamically distributes, it is identical that each request, which obtains the probability of response, and then realizes fair arbitration.
Existing arbitration circuit is as shown in Fig. 2, (patent No. 201710347888.X, double priority grade control type fair arbitration
Device) after two request signal~req0 and~req1 arrive, d_req0 and d_req0 is generated by delay cell, using prolonging
Slow unit and phase inverter generation~r0 and~r0, then pass through logical operation generation~c0 and~c1 and cp.Logical operation later
The signal generated after having these to postpone participates in.This circuit realizes that the central principle of fair arbitration is the cp by generating to generate
Odd-times conflict pulse _ odd and even-times conflict pulse ps_even to interfere bistable circuit, and then realize fair arbitration.
The shortcomings that above structure, is obvious.First, participating in the last logic circuit for realizing feedback has the letter after delay
Number participate in, when multiple arbitration units link together composition arbitration tree when, will cause very big delay.Second, by producing
Raw pulse carry out interference and its it is unstable, it is ensured that the width of pulse also accurately to control pulse arrival time, this is to work
Skill has very high requirement, and robustness and anti-interference ability are poor.
Summary of the invention
The shortcomings that in order to overcome the prior art, postpones big influence arbitration result if circuit complexity consumes area, and robustness is low
Deng, the invention proposes it is a kind of based on circular priority realize fair arbitration arbitration circuit.
The present invention is achieved through the following technical solutions:
A kind of arbitration circuit for being realized fair arbitration based on circular priority, is made of several arbitration units, such as Fig. 3 institute
Show, the arbitration unit includes priority selector unit, request generates unit and response generates unit；
The priority selector unit, as shown in figure 4, including rest-set flip-flop and a digit counter that nor gate is constituted, institute
It states rest-set flip-flop (as shown in Figure 5) to be made of two nor gates, works as input signalWithWhen different moments arrive,WithIt is terminated with the end R of rest-set flip-flop and S respectively into the output effective signal q0 and q1 of low level；One meter
Number device (as shown in Figure 6) the D trigger that is triggered by a failing edge and full adder form, the carry of full adder input (ci) and
Carry-out (co) is grounded, and input A terminates high level 1, the output Q of input B termination d type flip flop, output end SUM contact hair
The end device D, reset signalAccess the reset terminal of d type flip flop；Work as input signalWithWhen being carved into next at the same time,
WithBy one two input with behind the door be used as d type flip flop clock inputThe output end of d type flip flop leads to respectively
One group of mos pipe is crossed to be connected on the output q0 and q1 of rest-set flip-flop；The output signal Q of d type flip flop andIt alternately changes, control alternating
Low level effective q0 and q1 is generated as output and passes to response generation unit；Wherein, q0 effectively indicates wheel arbitration inputPriority is enjoyed, q1 effectively indicates wheel arbitration inputEnjoy priority；
The request generates unit, for generating request signal, as shown in fig. 7, input signalWithPass through one
A two input generates request signal with doorHaving an input signal is 0 (effective), just generates a request signal
(low level)；Two input signalsWithWhen being all 0 (effective), effective request signal is equally generated(low electricity
It is flat)；
The response generates unit and generates the request signal that unit generates according to requestAnd priority selector unit
Output signal q0, q1 generates answer signalOr
Further, the arbitration circuit (as shown in figure 11) is 2nThe n-layer binary tree shape of -1 arbitration unit composition
Structure；Each arbitration unit completes the arbitration work requested for this layer two, generates upper one layer of request signal, and
After the answer signal for receiving upper layer return, answer signal is returned in next layer of arbitration unit according to the sequence of arbitration,
The request signal that the top layer and bottom floor units of tree-shaped fair arbitration circuit can generate is transferred to external circuit, and receives external electrical
The answer signal that road returns, is transmitted to lower layer.
Further, the response generates unit, for generating answer signal, as shown in figure 8, by two three inputs or door
Constitute, two or input be respectivelyQ0 andQ1, it is describedIt is generated by request single
The request signal that member generatesGenerated after the delay of two-stage phase inverter, when or the input of door be low level when, have
The answer signal of effectOr
A kind of principle of arbitration circuit for realizing fair arbitration based on circular priority of the invention is as follows:
The d type flip flop of initial time, a digit counter is reset, and works as input signalWithIt arrives in different moments
When, rest-set flip-flop works normally without interruption, and the value of q0 and q1 is determined according to input signal；WhenWithIt carves at the same time
When arrival, is inputted by generating a low level signal as the clock of d type flip flop with door, when generating conflict for the first time, counted
The output signal Q (switch0) of device becomes 1,(switch1) become 0,1 number of each clock falling edge meter, with the 2nd
It is secondary, the 3rd time, the 4th ... conflict arrive, counter constantly starts counting, counter output signal Q (switch0) occurs 0,1,
0, it 1 ... alternately changes,(switch1) occur 1,0,1,0 ... alternately change, control be alternately produced the effective q0 of low level
Response, which is passed to, as output with q1 generates unit；Under conflict arbitration, q0 effectively indicates wheel arbitration inputIt enjoys preferential
Grade, q1 effectively indicate wheel arbitration inputEnjoy priority.Q andRegard switch switch0 and switch1 as, when
When switch0=0, switch1=1, q1 is set to 1, q0 since drop-down effect is set to 0 due to pull-up effect；Work as switch0
When=1, switch1=0, q1 is set to 0, q0 since drop-down effect is set to 1 due to pull-up effect.The meaning done so is to work asWithSimultaneously when arriving, Q is constantly inverted between zero and one, due to the interference effect of switch0 and switch1, q0 and
The probability that q1 is pulled low or draws high respectively is 50 percent.In conjunction with the logic of subsequent conditioning circuit, it ensure that each request signal obtains
The probability of response is the same, and then realizes fair arbitration.
Compared with prior art, advantages of the present invention is as follows:
The present invention is based on circular priorities to realize fair arbitration, judges that odd even is rushed instead of with the method for introducing time delay count
The characteristics of prominent, which passes through the method for introducing a digit counter, is alternately produced 0 and 1 using counter, judges
Odd even time conflict, and force to draw high or drag down the metastable state to interfere RS trigger using output result control, so that entire electricity
The delay on road substantially reduces.
Two switches while effect simultaneously ensures the stability of circuit, two-way to ensure that metastable state property is disturbed, will not
There is the indefinite situation of result, significantly enhances the robustness of circuit.
Integrated circuit reduces the number of gate level circuit, reduces the use of time delay module, significantly reduces power consumption, subtracts
Lack delay, reduced circuit area, realizes low-power consumption, few to postpone, the stable fair arbitration circuit of the small performance of area.
Detailed description of the invention
Fig. 1 is a kind of rotation priority level work of arbitration circuit that fair arbitration is realized based on circular priority of the invention
Flow chart；
The existing arbitration unit of Fig. 2, wherein (a) basic structure schematic diagram, (b) preselected portions electricity structure (c) arbitrate part
Circuit structure, (d) response part circuit structure (e) request hop circuit structure；
Fig. 3 is a kind of arbitration unit circuit of arbitration circuit that fair arbitration is realized based on circular priority of the invention
Schematic diagram；
Fig. 4 is a kind of priority selector unit of arbitration circuit that fair arbitration is realized based on circular priority of the invention
Schematic diagram；
Fig. 5 is the RS that a kind of nor gate of arbitration circuit that fair arbitration is realized based on circular priority of the invention is constituted
The schematic diagram of trigger；
Fig. 6 is a kind of showing for a digit counter of arbitration circuit that fair arbitration is realized based on circular priority of the invention
It is intended to；
Fig. 7 is that a kind of request of arbitration circuit that fair arbitration is realized based on circular priority of the invention generates unit
Schematic diagram；
Fig. 8 is that a kind of response of arbitration circuit that fair arbitration is realized based on circular priority of the invention generates unit
Schematic diagram；
Fig. 9 is a kind of working timing figure of arbitration unit that fair arbitration is realized based on circular priority of the invention；
The schematic diagram for the 2 rank fair arbitration circuits that Figure 10 is made of fair arbitration unit；
The schematic diagram for the n rank fair arbitration circuit that Figure 11 is made of fair arbitration unit.
Specific embodiment
The present invention is described further with reference to the accompanying drawing.
Embodiment 1:
A kind of arbitration circuit for being realized fair arbitration based on circular priority, is made of several arbitration units, such as Fig. 3 institute
Show, the arbitration unit includes priority selector unit, request generates unit and response generates unit；
The priority selector unit, as shown in figure 4, the rest-set flip-flop and a digit counter that are made of nor gate form,
The rest-set flip-flop (as shown in Figure 5) is made of two nor gates, works as input signalWithWhen different moments arrive,WithIt is terminated with the end R of rest-set flip-flop and S respectively into the output effective signal q0 and q1 of low level；One meter
Number device (as shown in Figure 6) the D trigger that is triggered by a failing edge and full adder form, the carry of full adder input (ci) and
Carry-out (co) is grounded, and input A terminates high level 1, the output Q of input B termination d type flip flop, output end SUM contact hair
The end device D, reset signalAccess the reset terminal of d type flip flop；Work as input signalWithWhen being carved into next at the same time,
WithBy one two input with behind the door be used as d type flip flop clock inputThe output signal Q of d type flip flop
As switch0,Pass through the output that one group of mos pipe is connected to rest-set flip-flop respectively as switch1, switch0 and switch1
On q0 and q1；Wherein, switch indicates control switch；The output signal Q of counter andIt alternately changes, control is alternately produced low
Level effective q0 and q1 pass to response as output and generate unit, wherein q0 effectively indicates wheel arbitration inputIt enjoys
There is priority, q1 effectively indicates wheel arbitration inputEnjoy priority；
The request generates unit, for generating request signal, as shown in fig. 7, input signalWithPass through one
A two input generates request signal with doorHaving an input signal is 0 (effective), just generates a request signal
(low level)；Two input signalsWithWhen being all 0 (effective), effective request signal is equally generated(low electricity
It is flat)；
The response generates unit and generates the request signal that unit generates according to requestAnd priority selector unit
Output signal q0, q1 generates answer signalOr
Further, the response generates unit, for generating answer signal, as shown in figure 8, by two three inputs or door
Constitute, two or input be respectivelyQ0 andQ1, it is describedIt is generated by request single
The request signal that member generatesGenerated after the delay of two-stage phase inverter, when or the input of door be low level when, have
The answer signal of effectOr
The priority selector unit, as shown in figure 4, working as input signalWithIt is defeated when different moments arrive
Enter signalWithIt is a bistable device and defeated for terminating respectively from the end R of rest-set flip-flop and S into, the rest-set flip-flop
Enter and holds low level effective；If input signalIt is 0,It is 1, then output signal q0 is 0, and output signal q1 is 1, if input
SignalIt is 1,It is 0, then output signal q0 is 1, and output signal q1 is 0；The unit is selected without priority at this time
It selects, does conventional judgement.If input signalWithFor low level, then rest-set flip-flop part enters nondeterministic statement simultaneously, this
When output signal q0 and q1 value by subsequent switch switch0 (Q) and switch1It determines；Switch0 and switch1
The effect of pullup or pulldown can be generated by two groups of mos pipes to control the value of the output q0 and q1 of rest-set flip-flop under metastable state.
Switch0 can the result q0 to front end rest-set flip-flop play the role of force pullup or pulldown, switch1 can be to front end RS
The result q1 of trigger play the role of force pullup or pulldown, the result always mutual exclusion of switch0 and switch1, q0 and
Q1 also always mutual exclusion, when ensure that conflict only one input effectively, when generate conflict for the first time when, the output Q of counter
(switch0) become 1,(switch1) become 0, as the 2nd time, the 3rd time, the 4th ... conflict arrive, counter is not turned off
Begin to count.Counter export Q (switch0) occur 0,1,0,1 ... alternately change,(switch1) occur 1,0,1,
0, it ... alternately changes.Control is alternately produced low level effective q0 and q1 as output and passes to response generation unit (Fig. 8).
Under conflict punching, q0 effectively indicates wheel arbitration inputPriority is enjoyed, q1 effectively indicates wheel arbitration inputIt enjoys
Priority.
The working timing figure of arbitration circuit based on circular priority is as shown in Figure 9.When occurring to conflict for the first time, althoughWithIt arrives simultaneously, butPriority is higher, soEffectively.Next timing nodeIt arrives first,After arrive, do not clash, arbitration circuit normally judges,Effectively.Second of conflict arrives later,With
Occur simultaneously, at this time reselecting due to priority selector unit,There is higher priority, soEffectively.Again
Secondary initiation can repeat this process when arbitrating, and then realize that circular priority reaches fair arbitration.
Specifically, as shown in figure 9,After being raised, circuit enters normal operating conditions, when initialWith
All it is 1, subsequently enters and conflict for the first time,WithEffective status is in for 0.Request unit (Fig. 7) is triggered at this time,
Request unit is constituted by one with door,WithAs input signal, as long as having an input signal is 0. output
As effectively,It is returned after two reversers are delayedDue toWithIt is simultaneously 0, a digit counter
(Fig. 6) is started counting, and Q is 0 at this time,It is 1, this makes switch0 be 0, switch1 1.Due toWithSimultaneously
Become 0, this makes rest-set flip-flop (Fig. 5) to enter metastable state, can not provide determining q0 and q1, but due to switch0 and
Switch1 can control two groups of mos pipes and force pull-up or pull down, since pull-up effect q1 is set to 1 in first round arbitration, by
0 is set in drop-down effect q0.Low level is effective at this timeWithAnd unit is generated collectively as response for 0 q0
The input of (Fig. 8) or to return low level effective door under the action ofThink that first round arbitration is completed at this time, this wheel
It is preferential to readData.Since q1 takes 1, can not return effectiveSoData be not read.
ThenIt is raised, onlyIt is effective for low level, enter normally judge state at this time.Request unit according to
It is old to generate one again effectivelyAnd it returnsDue to not having conflict to generate, a digit counter is without counting, no
Q0 and q1 can be interfered.Rest-set flip-flop does not also enter metastable state, and it be 0 is determining value that q0, which is 1q1,.So by response
Generate unit or gate action return useful signal
And be a subnormal judgement, process judged with last time it is similar, effectivelyAfter input, obtain effectiveCounter is still without counting.
Second of conflict judgement has been subsequently entered,WithAgain simultaneously it is 0, is all considered as effective input. RS
Trigger, which again goes into metastable state, can not provide determining q0 and q1.At this time byWithIt is simultaneously 0 influence,
Counter starts again at counting, and count results Q is 1,It is 0, it is exactly the opposite with last count results.So at this time
Switch0 is 1, switch0.So since pull-up effect q0 is set to 1 in the second wheel arbitration, since drop-down effect q1 is set to 0.This
Just produce the result opposite with first time conflict arbitration: this wheel is preferentially readData,It is invalid to be considered as.
It is last to have carried out a subnormal judgement again, with reference to the preceding course of work twice, effectivelyAfter input, obtain
EffectivelyCounter stops counting again.
So far, which has worked 5 times altogether, wherein being twice conflict arbitration.
Claims (3)
1. a kind of arbitration circuit for realizing fair arbitration based on circular priority, which is characterized in that by several arbitration unit structures
At the arbitration unit includes priority selector unit, request generates unit and response generates unit；
The priority selector unit, including rest-set flip-flop and a digit counter that nor gate is constituted, the rest-set flip-flop is by two
A nor gate is constituted, and works as input signalWithWhen different moments arrive,WithRespectively with the R of rest-set flip-flop
End and S are terminated into the output effective signal q0 and q1 of low level；One digit counter is triggered by the D that a failing edge triggers
Device and full adder composition, the carry input (ci) of full adder and carry-out (co) are grounded, and input A terminates high level 1, input
B terminates the output Q of d type flip flop, and output end SUM connects the end trigger D, reset signalAccess the reset terminal of d type flip flop；When defeated
Enter signalWithWhen being carved into next at the same time,WithBy one two input with behind the door as d type flip flop
Clock inputThe output end of d type flip flop passes through one group of mos pipe respectively and is connected on the output q0 and q1 of rest-set flip-flop；D triggering
The output signal Q of device andIt alternately changes, control is alternately produced low level effective q0 and q1 as output and passes to response production
Raw unit；Wherein, q0 effectively indicates wheel arbitration inputPriority is enjoyed, q1 effectively indicates wheel arbitration inputIt enjoys
There is priority；
The request generates unit, for generating request signal, input signalWithIt is generated by one two input with door
Request signalHaving an input signal is 0, just generates a request signalTwo input signalsWith
When being all 0, effective request signal is equally generated
The response generates unit and generates the request signal that unit generates according to requestAnd the output of priority selector unit
Signal q0, q1 generate answer signalOr
2. a kind of arbitration circuit for realizing fair arbitration based on circular priority as described in claim 1, which is characterized in that institute
Stating arbitration circuit is 2nThe n-layer binary tree shape and structure of -1 arbitration unit composition.
3. a kind of arbitration circuit for realizing fair arbitration based on circular priority as described in claim 1, which is characterized in that institute
State response generate unit, for generating answer signal, as shown in figure 8, by two three input or door constitute, two or input
RespectivelyQ0 andQ1, it is describedThe request signal that unit generates is generated by request
Generated after the delay of two-stage phase inverter, when or the input of door be low level when, generate effective answer signalOr
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| CN201910255693.1A CN110083563B (en) | 2019-04-01 | 2019-04-01 | Arbitration circuit for realizing fair arbitration based on cyclic priority |
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| CN201910255693.1A CN110083563B (en) | 2019-04-01 | 2019-04-01 | Arbitration circuit for realizing fair arbitration based on cyclic priority |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111211775A (en) * | 2020-01-14 | 2020-05-29 | 西安电子科技大学 | Three-input average arbitration circuit for dynamic vision sensor |
| CN112559403A (en) * | 2019-09-25 | 2021-03-26 | 阿里巴巴集团控股有限公司 | Processor and interrupt controller therein |
| CN113162606A (en) * | 2021-03-30 | 2021-07-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-priority control circuit |
| CN113160874A (en) * | 2021-04-23 | 2021-07-23 | 合肥恒烁半导体有限公司 | Segmented cycle counting output selection circuit and application thereof |
| CN113467999A (en) * | 2021-07-08 | 2021-10-01 | 西安航天动力试验技术研究所 | Active thermal redundancy monitoring dual-computer switching system and method |
| WO2024027133A1 (en) * | 2022-08-01 | 2024-02-08 | 声龙(新加坡)私人有限公司 | Priority grouping polling arbiter and arbitration method therefor, and crossbar and chip |
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Cited By (11)
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| CN112559403A (en) * | 2019-09-25 | 2021-03-26 | 阿里巴巴集团控股有限公司 | Processor and interrupt controller therein |
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| CN113162606A (en) * | 2021-03-30 | 2021-07-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-priority control circuit |
| CN113162606B (en) * | 2021-03-30 | 2023-04-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-priority control circuit |
| CN113160874A (en) * | 2021-04-23 | 2021-07-23 | 合肥恒烁半导体有限公司 | Segmented cycle counting output selection circuit and application thereof |
| CN113160874B (en) * | 2021-04-23 | 2023-12-12 | 恒烁半导体(合肥)股份有限公司 | Sectional type cycle count output selection circuit and application thereof |
| CN113467999A (en) * | 2021-07-08 | 2021-10-01 | 西安航天动力试验技术研究所 | Active thermal redundancy monitoring dual-computer switching system and method |
| CN113467999B (en) * | 2021-07-08 | 2022-12-09 | 西安航天动力试验技术研究所 | Active thermal redundancy monitoring dual-computer switching system and method |
| WO2024027133A1 (en) * | 2022-08-01 | 2024-02-08 | 声龙(新加坡)私人有限公司 | Priority grouping polling arbiter and arbitration method therefor, and crossbar and chip |
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| CN110083563B (en) | 2022-10-28 |
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