CN112667292B - Asynchronous micro-pipeline controller - Google Patents
Asynchronous micro-pipeline controller Download PDFInfo
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- CN112667292B CN112667292B CN202110101604.5A CN202110101604A CN112667292B CN 112667292 B CN112667292 B CN 112667292B CN 202110101604 A CN202110101604 A CN 202110101604A CN 112667292 B CN112667292 B CN 112667292B
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Abstract
The invention discloses an asynchronous micro pipeline controller, which comprises: an inverter, an exclusive-or gate, a flip-flop FF, and a data latch; the input end of the reverser is connected with the output end of the trigger; the input end of the exclusive-or gate inputs a Fill signal and a Drain signal, the input end of the exclusive-or gate comprises a first input end and a second input end, the first input end inputs the Drain signal, and the second input end inputs the Fill signal; the output end of the exclusive-OR gate is connected with the clock input end of the trigger; the data input end of the trigger is connected with the data reverse output end of the trigger, and the data output end of the trigger is connected with the input end of the reverser and the next-stage pipeline; the input end of the data latch is used for inputting output data of a previous stage pipeline, and the output end of the data latch is connected with the input end of the combinational logic module in a next stage pipeline; the pulse input end of the data latch is connected with the input end of the exclusive or gate input Fill signal. The invention simplifies the whole structure of the pipeline control circuit and reduces the turnover of the control signals of the data latch.
Description
Technical Field
The invention relates to the field of asynchronous micro-pipelines, in particular to an asynchronous micro-pipeline controller.
Background
The asynchronous micro pipeline comprises a plurality of stages of controllers, each stage of controllers is a Click unit, the control of a data path is generally realized among each stage of controllers through handshake signals, and the Click units are used for controlling the data path of the pipeline. However, the circuit structure of the existing Click unit is slightly complex, and the data path register in the existing Click unit is controlled by four signals, so that the turnover frequency of the control signals of the data path register is increased, the data transmission speed is slow, and the data transmission efficiency is low.
Disclosure of Invention
The invention aims to provide an asynchronous micro-pipeline controller to solve the problems of low data transmission speed and low data transmission efficiency of the traditional Click unit.
In order to achieve the above object, the present invention provides the following solutions:
the invention relates to an asynchronous micro pipeline controller, comprising: an inverter INV, an exclusive or gate XOR, a flip-flop FF and a data latch;
the input end of the inverter INV is connected with the output end of the trigger FF;
the input end of the exclusive or gate XOR inputs a Fill signal and a Drain signal, the input end of the exclusive or gate XOR comprises a first input end and a second input end, the first input end inputs the Drain signal, and the second input end inputs the Fill signal; the output end of the exclusive or gate XOR is connected with the clock input end of the trigger FF;
the data input end of the flip-flop FF is connected with the data inverting output end of the flip-flop FFThe data output end Q of the flip-flop FF is connected with the input end of the inverter INV and the next stage pipeline;
the input end of the data latch is used for inputting output data of a previous stage pipeline, and the output end of the data latch is connected with the input end of a combinational logic module in a next stage pipeline; the pulse input end of the data latch is connected with the input end of the exclusive or gate XOR for inputting the Fill signal; the Fill signal and the Drain signal generate clock signals through the exclusive OR gate XOR, the clock signals are input to the flip-flop FF, the flip-flop FF is triggered to output a FULL signal, and the FULL signal of the flip-flop FF is input to the inverter INV and the next-stage pipeline; the Fill signal is also input to the data latch; the asynchronous micro pipeline controller controls the turnover times of the data latch by using the Fill signal and the output data of the upper stage pipeline.
Optionally, the data output terminal Q of the flip-flop FF outputs a Full signal.
Optionally, after the Full signal is inverted by the inverter INV, an Empty signal is output.
Optionally, the Empty signal is input to the previous stage pipeline as a response signal of the previous stage pipeline.
Optionally, the Full signal is used as a request signal of the next stage pipeline.
Optionally, when the reset port of the flip-flop FF is 0, the flip-flop FF is reset, and the data output terminal Q of the flip-flop FF outputs 0.
Optionally, the test port of the flip-flop FF is used for testing the current working state of the flip-flop FF; the current working state comprises a normal working state and an abnormal working state.
Optionally, the time when the Fill signal is input to the exclusive or gate XOR is earlier than the time when the Drain signal is input to the exclusive or gate XOR.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses an asynchronous micro-pipeline controller, wherein a data latch in the asynchronous micro-pipeline controller is controlled by two signals, so that the turnover times of control signals of the data latch are reduced, the speed of data transmission is improved, and the data transmission efficiency in a data path is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an asynchronous micro pipeline controller according to the present invention.
Symbol description: an inverter-INV; exclusive or gate-XOR; flip-flop-FF; a data latch; a data output terminal-Q; data reverse output endThe method comprises the steps of carrying out a first treatment on the surface of the A data input-D; reset port-CLR; test port-SET; output data-Date out of the upper stage pipeline; the output data of the data latch, date in.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide an asynchronous micro-pipeline controller to solve the problems of low data transmission speed and low data transmission efficiency of the traditional Click unit.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
FIG. 1 is a schematic diagram of an asynchronous micro-pipeline controller of the present invention, as shown in FIG. 1, comprising: an inverter INV, an exclusive or gate XOR, a flip-flop FF and a data latch.
An input end of the inverter INV is connected with an output end of the flip-flop FF.
The input end of the exclusive or gate XOR inputs a Fill signal and a Drain signal, the input end of the exclusive or gate XOR comprises a first input end and a second input end, the first input end inputs the Drain signal, and the second input end inputs the Fill signal; the output end of the exclusive or gate XOR is connected with the clock input end of the flip-flop FF.
The data input end of the flip-flop FF is connected with the data inverting output end of the flip-flop FFThe data output end Q of the flip-flop FF is connected with the inverterAn input end of the INV and a next stage pipeline.
The input end of the data latch is used for inputting output data Date out of a previous stage pipeline, and output data Date in of the data latch is input to the input end of a combinational logic module in a next stage pipeline; the pulse input end of the data latch is connected with the second input end of the exclusive or gate XOR; the FULL signal and the Drain signal generate clock signals through exclusive OR gate XOR, the clock signals are input to the flip-flop FF, the flip-flop FF is triggered to output FULL signals, and the FULL signals of the flip-flop FF are input to the inverter INV and the next-stage pipeline; the Fill signal is also input to the data latch; and controlling the turnover times of the data latch by using the Fill signal and the output data of the upper-stage pipeline.
As an alternative embodiment, the data output Q of the flip-flop FF outputs a Full signal.
As an alternative implementation manner, the Full signal is inverted through the inverter INV, and then the Empty signal is output.
As an alternative embodiment, the Empty signal is input to the previous stage pipeline as a response signal of the previous stage pipeline.
As an alternative embodiment, the Full signal is used as the request signal of the next stage pipeline.
As an alternative embodiment, when the reset port of the flip-flop FF is 0, the flip-flop FF is reset, and the data output terminal Q of the flip-flop FF outputs 0.
As an alternative embodiment, the test port of the flip-flop FF is used for testing the current working state of the flip-flop FF; the current working state comprises a normal working state and an abnormal working state.
As an alternative embodiment, the Fill signal is input to the exclusive or gate XOR at a time earlier than the Drain signal is input to the exclusive or gate XOR.
Compared with the existing micro-pipeline controller, the asynchronous micro-pipeline controller has the advantages of simple structure, higher speed and adjustable delay of each stage of the controlled pipeline.
The invention has the specific functions that an improved click unit is used as a controller of each stage of a pipeline, and the control of a data path of the pipeline is achieved by two input signals, namely a Fill signal, a Drain signal, two output signals, namely a Full signal and an Empty signal. The improved click unit consists of an inverter, an exclusive-or gate and a flip-flop with an output inverted Q tied back to the input. The method comprises the steps that a request signal from a previous stage pipeline and a response signal of a next stage pipeline generate four local clock signals through an exclusive or gate, the output Q of a trigger is controlled to be turned over through a trigger signal and a reset signal which are realized by a group of rising and falling edges, the output Q of the trigger is used as a request signal Full of the next stage, and the inverted Empty is used as a response signal of the previous stage pipeline. For each stage of pipeline control signals, the Fill signal is required to be earlier in time than the Drain signal is arriving to meet this timing constraint.
The asynchronous micro pipeline controller disclosed by the invention is an improved click unit, compared with the traditional click unit, the whole structure of a pipeline control circuit is simplified, and the inversion of a data path latch control signal is reduced.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (8)
1. An asynchronous micro pipeline controller, the asynchronous micro pipeline controller comprising: an inverter INV, an exclusive or gate XOR, a flip-flop FF and a data latch;
the input end of the inverter INV is connected with the output end of the trigger FF;
the input end of the exclusive or gate XOR inputs a Fill signal and a Drain signal, the input end of the exclusive or gate XOR comprises a first input end and a second input end, the first input end inputs the Drain signal, and the second input end inputs the Fill signal; the output end of the exclusive or gate XOR is connected with the clock input end of the trigger FF;
the data input end of the flip-flop FF is connected with the data inverting output end of the flip-flop FFThe data output end Q of the flip-flop FF is connected with the input end of the inverter INV and the next stage pipeline;
the input end of the data latch is used for inputting output data of a previous stage pipeline, and the output end of the data latch is connected with the input end of a combinational logic module in a next stage pipeline; the pulse input end of the data latch is connected with the input end of the exclusive or gate XOR for inputting the Fill signal; the Fill signal and the Drain signal generate clock signals through the exclusive OR gate XOR, the clock signals are input to the flip-flop FF, the flip-flop FF is triggered to output a FULL signal, and the FULL signal of the flip-flop FF is input to the inverter INV and the next-stage pipeline; the Fill signal is also input to the data latch; the asynchronous micro pipeline controller controls the turnover times of the data latch by using the Fill signal and the output data of the upper stage pipeline.
2. The asynchronous micro pipeline controller according to claim 1, wherein the data output terminal Q of the flip-flop FF outputs a Full signal.
3. The asynchronous micro pipeline controller according to claim 2, wherein the Full signal outputs the Empty signal after being inverted through the inverter INV.
4. The asynchronous micro pipeline controller of claim 3, wherein the Empty signal is input to the previous stage pipeline as a reply signal to the previous stage pipeline.
5. The asynchronous micro pipeline controller of claim 4, wherein the Full signal is used as a request signal for the next stage pipeline.
6. The asynchronous micro pipeline controller according to claim 1, wherein when the reset port of the flip-flop FF is 0, the flip-flop FF is reset, and the data output terminal Q of the flip-flop FF outputs 0.
7. The asynchronous micro pipeline controller according to claim 1, wherein a test port of the flip-flop FF is used to test a current operating state of the flip-flop FF; the current working state comprises a normal working state and an abnormal working state.
8. The asynchronous micro pipeline controller of claim 1, wherein the Fill signal is input to the exclusive or gate XOR earlier than the Drain signal is input to the exclusive or gate XOR.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113407239B (en) * | 2021-06-09 | 2023-06-13 | 中山大学 | Pipeline processor based on asynchronous monorail |
| CN113485671B (en) * | 2021-07-06 | 2024-01-30 | 北京中科芯蕊科技有限公司 | Click controller and asynchronous micro-pipeline data flow controller |
| CN113489482B (en) * | 2021-07-06 | 2023-10-20 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline data flow controller based on Mouserap |
| CN113590200B (en) * | 2021-08-03 | 2024-01-30 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline controller based on SR latch |
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