CN106776423A - Using the asynchronous arbitration tree circuit of priority automatic switchover arbitration unit - Google Patents
Using the asynchronous arbitration tree circuit of priority automatic switchover arbitration unit Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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Abstract
The present invention relates to integrated circuit fields, to provide the asynchronous arbitration tree circuit that a kind of priority can automatically switch, it is used to realize the arbitration mechanism of justice so that each request signal fair can be received and response, the right to use of the acquisition bus of justice.For this, the technical solution adopted by the present invention is, using the asynchronous arbitration tree circuit of priority automatic switchover arbitration unit, tree-like arbitration structure, include N number of arbitration level altogether, from low to high, a total of 2N is asked input port to arbitration rank, 2N response output port, the arbitration unit that 1 priority of 2N automatically switches.Present invention is mainly applied to IC design occasions that manufacture.
Description
Technical field
The present invention relates to integrated circuit fields, there are an arbitration tree circuits of multiple requests, more particularly to a kind of priority is automatic
Switching arbitration circuit.
Background technology
In traditional fixed priority arbitration circuit, when multiple requests are received simultaneously, when there is request collision, arbitrate
Device can respond the request of certain signal according to the priority for pre-setting, and be the right to use of its distribution bus, other request signals
Do not received then, as invalidation request.Obviously this is a kind of inequitable arbitration mechanism, once there is request collision, some are low
The request signal of priority is always at disarmed state, it is impossible to obtain the right to use of bus, is so irrational.Generally speaking
The subject matter of this traditional fixed priority arbitration circuit is can not balancedly to respond the request signal in a period of time.
The content of the invention
To overcome the deficiencies in the prior art, the present invention is intended to provide the asynchronous arbitration tree that a kind of priority can automatically switch
Circuit, is used to realize the arbitration mechanism of justice so that each request signal fair can be received and response, fair acquisition
The right to use of bus.Therefore, the technical solution adopted by the present invention is, using the asynchronous arbitration of priority automatic switchover arbitration unit
Tree circuit, tree-like arbitration structure, altogether including N number of arbitration level, from low to high, a total of 2N is asked input to arbitration rank
Mouthful, 2N response output port, the arbitration unit that 2N-1 priority automatically switches；
The structure of arbitration unit includes priority selector unit, arbitration unit, request propagation unit and response unit four
Part, input signal includes nreq0, nreq1 and nack, and output signal includes nack0, nack1 and nreq, each several part logic work(
Energy and annexation are as follows：
(1) priority selector unit：Request signal nreq0 by the 1st phase inverter be linked into first NAND gate be used as it is defeated
Enter, then be input into as another by being linked into the 1st NAND gate after 3 phase inverters, the 1st NAND gate output signal np0 please
Signal nreq1 is asked to produce signal np1 in an identical manner；Np0 and np1 produces signal cp, cp triggering D to touch by a nor gate
Hair device, the output of d type flip flop is linked into the nor gate and is input into by the 2nd phase inverter, is produced by two q signal inverters
Q signals, q signals and cp signals produce ps signals by first with door, and the Main Function of priority selector unit is to receive to ask
Ask signal nreq0 and nreq1, produce nr0 and nr1 signals, and according to the number of times of request collision, export ps signals, nr0, nr1 and
Ps signals are as the input of subsequent arbitration unit；Nreq0, nreq1, nr0 and nr1 signal be it is low effectively, ps signals for height
Effectively, np0, np1, cp and q signal are M signals；When without request collision, there are two kinds of situations：Nreq0=0, nreq1=1
Or nreq0=1, nreq1=0；It is low level at the 1st output of phase inverter, in the presence of phase inverter in the case of the first
Prolong, described still to keep high level for a period of time by being linked into the junction of the 1st NAND gate after 3 phase inverters again, nr0=
0 effectively, therefore np0 can produce a low pulse, but now np1 is always high level, so cp=0, d type flip flop cannot be touched
Hair, ps=0 is invalid；Similarly, in the case of second, effectively, ps=0 is invalid for nr1=0；When there is request collision, also there are two kinds
Situation：Odd-times conflicts and even-times conflict：When there is request collision, np0 and np1 produces a low pulse simultaneously, then cp
Signal can produce a high impulse, d type flip flop triggering, due to the presence time delay of phase inverter, the cp signals of the change generation of q signals
Afterwards, so when odd-times conflicts, ps=0 is invalid, when even-times conflicts, ps=1, effectively；
(2) arbitration unit：Signal nr0 and nr1 are each linked on rest-set flip-flop by an arbitration unit phase inverter, RS
A NAND gate in trigger is three inputs, and nr1 and ps is its input；The Main Function of arbitration unit is to receive excellent
The nr0 that first level select unit is produced, nr1 and ps signals produce nx0 and nx1 signals, as the input of follow-up response unit；It is secondary
Cut out unit truth table as shown in Table 1；When clashing, nx0=0, then it represents that the priority of request signal nreq0 is higher；nx0
=1, then it represents that the priority of request signal nreq1 is higher；When i.e. odd-times conflicts, the priority of request signal nreq0 is higher；
When even-times conflicts, the priority of request signal nreq1 is higher；
The arbitration unit truth table of table one
| nr0 | nr1 | Request collision | ps | nx0 | nx1 |
| 1 | 1 | Nothing | 0 | 1 | 1 |
| 0 | 1 | Nothing | 0 | 0 | 1 |
| 1 | 0 | Nothing | 0 | 1 | 0 |
| 0 | 0 | Odd-times | 0 | 0 | 1 |
| 0 | 0 | Even-times | 1 | 1 | 0 |
(3) propagation unit is asked：Request signal nreq0 and nreq1 produces one by a request propagation unit and door
Nreq signals；When any one is effective as request signal nreq0 and nreq1, a new request signal nreq can be produced, passed
It is delivered in higher leveled arbitration and is arbitrated, one instance arbitration high can produces corresponding answer signal nack when effective, and nack is low to be had
Effect；
(4) response unit：Signal nreq0, nx0 and nack signal produce a nack0 to believe by one three input OR gate
Number；Signal nreq1, nx1 and nack signal produce a nack1 signal by one three input OR gate；Response unit it is main
Effect is the request signal higher for priority, produces corresponding answer signal nack0 or nack1, is low effectively；If
The priority of nreq0 is higher, during nreq0=0, nr0=0, nack=0, then nack0=0；If the priority of nreq1 is higher,
During nreq1=0, nr1=0, nack=0, then nack1=0；
Prime is generally input into request signal by by the arbitration unit that above-mentioned this priority can automatically switch
Nreq0 and nreq1 after arbitration unit treatment by producing rear class request signal nreq, the request signal of two neighboring arbitration unit
Next stage arbitration unit is input to again, as two input request signals；Connect step by step in this manner, to the last one-level,
The output request of afterbody is shorted together with input validation signal nack, for feedback acknowledgment signal；Confirmation signal
Nack produces two output confirmation signals of nack0 and nack1, the two signals to connect respectively by afterbody arbitration unit
To the confirmation signal input part of two arbitration units of upper level；Connect step by step in this manner, so as to produce institute in the first order
The confirmation signal for needing.
N=16.
The features of the present invention and beneficial effect are：
By the arbitration tree circuit that can be automatically switched using above-mentioned this priority, it is possible to achieve fair arbitration machine
System, makes the request signal received in a period of time average as far as possible between each input signal, so that each signal is obtained
Obtain the chance of access bus on an equal basis.
Brief description of the drawings：
Fig. 1 input arbitration tree circuit structures.
Fig. 2 arbitration unit structures.
Fig. 3 priority selector unit structures.
Fig. 4 ps signal intensities.
Fig. 5 arbitration units.
Fig. 6 asks propagation unit.
Fig. 7 response units.
Fig. 8 priority selector unit working timing figures.
Specific embodiment
What the present invention was designed is the asynchronous arbitration tree circuit that a kind of priority can automatically switch.It uses tree-like secondary
Structure is cut out, altogether including N number of arbitration level, arbitration rank is from low to high.A total of 2N request input port, 2N response is defeated
Exit port is, it is necessary to the 2N-1 arbitration unit of priority automatic switchover.
The core for arbitrating tree circuit is arbitration unit, and the structure of arbitration unit is as shown in Figure 2.It is mainly selected including priority
Unit, arbitration unit, four parts of request propagation unit and response unit are selected, input signal includes nreq0, nreq1 and nack,
Output signal includes nack0, nack1 and nreq, and each several part logic function and annexation are as follows：
(1) priority selector unit：Its structure is as shown in figure 3, request signal nreq0 is linked into one by 1 phase inverter
NAND gate is input into as input, then by being linked into same NAND gate after 3 phase inverters as another, NAND gate output letter
Number np0.Request signal nreq1 produces signal np1 in an identical manner.Np0 and np1 produces signal cp by a nor gate,
Cp triggers d type flip flop, and the output of d type flip flop is linked into its input, produces q to believe by two phase inverters by a phase inverter
Number, q signals and cp signals produce ps signals by one with door.The Main Function of priority selector unit is to receive request signal
Nreq0 and nreq1, produces nr0 and nr1 signals, and according to the number of times of request collision, exports ps signals.Nr0, nr1 and ps signal
As the input of subsequent arbitration unit.Nreq0, nreq1, nr0 and nr1 signal be it is low effectively, ps signals be it is high effectively,
Np0, np1, cp and q signal are M signals.When without request collision, there are two kinds of situations：Nreq0=0, nreq1=1 or
Nreq0=1, nreq1=0.It is low level at 1 in the case of the first, electricity high can be still kept because phase inverter has time delay, at 2
Flat a period of time, nr0=0 is effective, therefore np0 can produce a low pulse, but now np1 is always high level, so cp=
0, d type flip flop cannot be triggered, and ps=0 is invalid.Similarly, in the case of second, effectively, ps=0 is invalid for nr1=0.When there is request
During conflict, also there are two kinds of situations：Odd-times conflicts and even-times conflict.When there is request collision, according to analysis above, can
Know that np0 and np1 produces a low pulse simultaneously, then cp signals can produce a high impulse, d type flip flop triggering, due to phase inverter
Presence time delay, q signals change occur cp signals after, so odd-times conflict when, ps=0 is invalid, even-times conflict
When, ps=1, effectively.The change of q, cp, ps signal is as shown in Figure 4.
(2) arbitration unit：Its structure is as shown in figure 5, signal nr0 and nr1 are each linked into RS triggerings by a phase inverter
On device, a NAND gate in rest-set flip-flop is three inputs, and nr1 and ps is its input.The Main Function of arbitration unit
It is the nr0 for receiving priority selector unit generation, nr1 and ps signals produce nx0 and nx1 signals, as follow-up response unit
Input.According to the structure of Fig. 5, we can easily draw its truth table, as shown in Table 1.When clashing, nx0=
0, then it represents that the priority of request signal nreq0 is higher；Nx0=1, then it represents that the priority of request signal nreq1 is higher.It is i.e. strange
When conflicting for several times, the priority of request signal nreq0 is higher；When even-times conflicts, the priority of request signal nreq1 is higher.
Thus arbitrated out the priority of request signal, and can automatic switching request signal priority.
The arbitration unit truth table of table one
| nr0 | nr1 | Request collision | ps | nx0 | nx1 |
| 1 | 1 | Nothing | 0 | 1 | 1 |
| 0 | 1 | Nothing | 0 | 0 | 1 |
| 1 | 0 | Nothing | 0 | 1 | 0 |
| 0 | 0 | Odd-times | 0 | 0 | 1 |
| 0 | 0 | Even-times | 1 | 1 | 0 |
(3) propagation unit is asked：Its structure is as shown in fig. 6, request signal nreq0 and nreq1 produces one by one with door
Individual nreq signals.When any one is effective as request signal nreq0 and nreq1, a new request signal nreq can be produced,
It is delivered in higher leveled arbitration and is arbitrated, one instance arbitration high can produces corresponding answer signal nack when effective, and nack is low
Effectively.
(4) response unit：Its structure is as shown in fig. 7, signal nreq0, nx0 and nack signal are by one three input OR gate
Produce a nack0 signal；Signal nreq1, nx1 and nack signal produce a nack1 signal by one three input OR gate.
The Main Function of response unit is the request signal higher for priority, produces corresponding answer signal nack0 or nack1,
It is low effectively.If the priority of nreq0 is higher, during nreq0=0, nr0=0, nack=0, then nack0=0；If nreq1's
Priority is higher, during nreq1=0, nr1=0, nack=0, then nack1=0.
Prime is generally input into request signal by by the arbitration unit that above-mentioned this priority can automatically switch
Nreq0 and nreq1 after arbitration unit treatment by producing rear class request signal nreq, the request signal of two neighboring arbitration unit
Next stage arbitration unit is input to again, as two input request signals；Connect step by step in this manner, to the last one-level,
The output request of afterbody is shorted together with input validation signal nack, for feedback acknowledgment signal；Confirmation signal
Nack produces two output confirmation signals of nack0 and nack1, the two signals to connect respectively by afterbody arbitration unit
To the confirmation signal input part of two arbitration units of upper level；Connect step by step in this manner, so as to produce institute in the first order
The confirmation signal for needing.The structure is set similar to tree as arbitration.Arbitration tree construction for example shown in Fig. 1, it is possible to real
Now to 16 fair arbitrations of input signal.
When core of the invention is the work of the arbitration unit, wherein priority selector unit that priority can automatically switch
Sequence is as shown in Figure 8.By the time delay and the number of phase inverter of rational configuration phase inverter, when realizing that odd-times conflicts, request letter
The priority of number nreq0 is higher；When even-times conflicts, the priority of request signal nreq1 is higher.Then it is such by 2N-1
Arbitration unit is configured to include the arbitration tree circuit of N number of arbitration level.Specifically first configure two arbitration trees of level, Ran Houli
Three arbitration trees of level are configured to the arbitration tree of this two levels, can be configured by that analogy including N number of level
Arbitration tree circuit, so as to constitute arbitration tree.
Claims (2)
1. a kind of asynchronous arbitration tree circuit of use priority automatic switchover arbitration unit, it is characterized in that, altogether including N number of arbitration
Level, arbitrates rank from low to high, a total of 2N request input port, 2N response output port, and 2N-1 priority is certainly
The arbitration unit of dynamic switching；
The structure of arbitration unit includes priority selector unit, arbitration unit, four parts of request propagation unit and response unit,
Input signal include nreq0, nreq1 and nack, output signal include nack0, nack1 and nreq, each several part logic function and
Annexation is as follows：
(1) priority selector unit：Request signal nreq0 is linked into first NAND gate and is used as input by the 1st phase inverter,
It is input into as another by being linked into the 1st NAND gate after 3 phase inverters again, the 1st NAND gate output signal np0, request
Signal nreq1 produces signal np1 in an identical manner；Np0 and np1 produces signal cp, cp triggering D triggerings by a nor gate
Device, the output of d type flip flop is linked into the nor gate and is input into by the 2nd phase inverter, and q is produced by two q signal inverters
Signal, q signals and cp signals produce ps signals by first with door, and the Main Function of priority selector unit is to receive request
Signal nreq0 and nreq1, produce nr0 and nr1 signals, and according to the number of times of request collision, export ps signals, nr0, nr1 and ps
Signal is as the input of subsequent arbitration unit；Nreq0, nreq1, nr0 and nr1 signal be it is low effectively, ps signals have for height
Effect, np0, np1, cp and q signal are M signals；When without request collision, there are two kinds of situations：Nreq0=0, nreq1=1 or
Nreq0=1, nreq1=0；It is low level at the 1st output of phase inverter, in the presence of phase inverter in the case of the first
Prolong, described still to keep high level for a period of time by being linked into the junction of the 1st NAND gate after 3 phase inverters again, nr0=
0 effectively, therefore np0 can produce a low pulse, but now np1 is always high level, so cp=0, d type flip flop cannot be touched
Hair, ps=0 is invalid；Similarly, in the case of second, effectively, ps=0 is invalid for nr1=0；When there is request collision, also there are two kinds
Situation：Odd-times conflicts and even-times conflict：When there is request collision, np0 and np1 produces a low pulse simultaneously, then cp
Signal can produce a high impulse, d type flip flop triggering, due to the presence time delay of phase inverter, the cp signals of the change generation of q signals
Afterwards, so when odd-times conflicts, ps=0 is invalid, when even-times conflicts, ps=1, effectively；
(2) arbitration unit：Signal nr0 and nr1 are each linked on rest-set flip-flop by an arbitration unit phase inverter, RS triggerings
A NAND gate in device is three inputs, and nr1 and ps is its input；The Main Function of arbitration unit is to receive priority
The nr0 that select unit is produced, nr1 and ps signals produce nx0 and nx1 signals, as the input of follow-up response unit；Arbitration is single
First truth table is as shown in Table 1；When clashing, nx0=0, then it represents that the priority of request signal nreq0 is higher；Nx0=1,
Then represent that the priority of request signal nreq1 is higher；When i.e. odd-times conflicts, the priority of request signal nreq0 is higher；Even number
During secondary conflict, the priority of request signal nreq1 is higher；
The arbitration unit truth table of table one
(3) propagation unit is asked：Request signal nreq0 and nreq1 produces a nreq to believe by a request propagation unit and door
Number；When any one is effective as request signal nreq0 and nreq1, a new request signal nreq can be produced, be delivered to height
Arbitrated in the arbitration of one-level, one instance arbitration high can produce corresponding answer signal nack when effective, and nack is low effectively；
(4) response unit：Signal nreq0, nx0 and nack signal produce a nack0 signal by one three input OR gate；Letter
Number nreq1, nx1 and nack signal produces a nack1 signal by one three input OR gate；The Main Function of response unit is
The request signal higher for priority, produces corresponding answer signal nack0 or nack1, is low effectively；If nreq0's
Priority is higher, during nreq0=0, nr0=0, nack=0, then nack0=0；If the priority of nreq1 is higher, nreq1=0
When, nr1=0, nack=0, then nack1=0；
By arbitration unit that above-mentioned this priority can automatically switch generally by prime be input into request signal nreq0 and
Nreq1 after arbitration unit treatment by producing rear class request signal nreq, the request signal of two neighboring arbitration unit to be input into again
To next stage arbitration unit, as two input request signals；Connect step by step in this manner, to the last one-level, will be last
The output request of one-level is shorted together with input validation signal nack, for feedback acknowledgment signal；Confirmation signal nack passes through
Afterbody arbitration unit, produces two output confirmation signals of nack0 and nack1, the two signals to be connected respectively to upper level
Two arbitration units confirmation signal input part；Connect step by step in this manner, so as to the confirmation needed for being produced in the first order
Signal.
2. as claimed in claim 1 using the asynchronous arbitration tree circuit of priority automatic switchover arbitration unit, it is characterized in that, N
=16.
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| CN201611062444.3A CN106776423B (en) | 2016-11-25 | 2016-11-25 | Automatically switch the asynchronous arbitration tree circuit of arbitration unit using priority |
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| CN111211775A (en) * | 2020-01-14 | 2020-05-29 | 西安电子科技大学 | Three-input average arbitration circuit for dynamic vision sensor |
| CN113162606A (en) * | 2021-03-30 | 2021-07-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-priority control circuit |
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| CN111211775B (en) * | 2020-01-14 | 2023-05-30 | 西安电子科技大学 | Three-input average arbitration circuit for dynamic vision sensor |
| CN113162606A (en) * | 2021-03-30 | 2021-07-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-priority control circuit |
| CN113162606B (en) * | 2021-03-30 | 2023-04-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multi-priority control circuit |
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