CN101344871A - Bus arbitration unit for guaranteeing access sequence and its implementing method - Google Patents
Bus arbitration unit for guaranteeing access sequence and its implementing method Download PDFInfo
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Abstract
The invention relates to a bus arbitration unit which ensures access precedence, and a realization method thereof. The bus arbitration unit comprises a queue memory which is used for storing request packets sent at different time, a bit mask unit which is used for masking the earliest request packet so as to mask off the request which is responded, and an arbitration unit which is used for arbitrating the masked request packet so as to select one of the requests for response. By ensuring that the request arriving first and sent by a plurality of modules at different time is first responded, the unit and the method of the invention arbitrate according to the precedence of a plurality of requests arriving simultaneously, thereby ensuring that the precedence of multiple modules for accessing the memory is not disorganized and meeting the correctness of the team work of a plurality of modules.
Description
Technical field
The present invention relates to a kind of bus arbiter unit and its implementation that guarantees to visit sequencing.
Background technology
In on-chip integration system (SoC), there are a plurality of functional modules that need reference-to storage, as a plurality of processors in the sheet, DMA, hardware accelerator module etc.The memory resource of system comprises chip external memory, as SDRAM, and DDR, NOR.In order to reduce access delay, also has the shared storage in the sheet, simultaneously as SRAM.
In the SoC system, processor and other functional modules are independent operating separately, and cooperatively interacting as required visits the various types of memory resource.So each memory resource all might be simultaneously by a plurality of functional module request of access.But according to the physical characteristics of storer, jumbo storer generally only allows to carry out simultaneously a read and write access.Therefore, a plurality of functional modules need realize by bus arbiter unit the visit of same storer.Bus arbiter unit will be authorized the module that this storer is visited in some requests to the access rights of storer according to certain selection strategy, and hang up the request of access of other modules temporarily, till handling current all request of access.
In the SoC of complexity chip, the data between a plurality of modules are generally all shared transmission by storer.Such as, processor 1 takes out the raw data of A position from a storer, after the intermediate operations process finishes operation result is deposited go back to storer B position.Then, certain specific position to storer carries out write operation again, obtains the intermediate operations result from the B position as the input data with notification processor 2, carries out next step computing.The pattern that this multimode is carried out collaborative work by shared storage, needs guarantee not upset the access order of storer, otherwise the computing meeting of data stream makes mistakes.
But because bus arbiter unit may receive the request of a lot of modules about reference-to storage simultaneously, the request of processor 1 and processor 2 may be hung up by bus arbiter unit simultaneously and wait for.For traditional bus arbiter unit, the request that is suspended wait after arbitration unit allows application, all requests that will be considered to send simultaneously, and will produce application result according to the resolving strategy of certain priority.Do the actual sequencing that might upset the raw data request of access like this, and if a plurality of module accesses be same address, mistake will appear in net result so.
For example, processor 1 sends the request of B position in the memory write, and interval very short time preprocessor 2 sends the request of B position in the memory read then.If these two requests are all hung up by bus arbiter unit, so when bus arbiter unit is idle, operation that processor 2 reads B might occurs and write B prior to processor 1 and meet with a response.So, the data of processor 2 possible readout errors.
Summary of the invention
The invention provides bus arbiter unit and its implementation of a kind of assurance visit sequencing that can overcome the above problems.
In first aspect, the invention provides a kind of bus arbitration method that guarantees to visit sequencing, comprising: the request grouping that difference is sent is constantly stored; Moment request group is the earliest carried out shielding processing to mask the request that has been responded; And to the shielding after the request group arbitrate to select one of them request to respond.
In a first aspect of the present invention, preferably, described storing step comprises: difference request group is constantly arranged by first-in first-out (FIFO) formation.
In a first aspect of the present invention, preferably, described each request group is represented that by n request position the original state of all request positions represents not have request, the number of modules that the n representative has bus arbiter unit to connect.
In a first aspect of the present invention, preferably, described arbitration step comprises: the priority according to each request in the request group after the shielding is selected, and described priority is pre-configured fixing.
In a first aspect of the present invention, preferably, described response is represented by n response bit, the number of modules that the n representative has bus arbiter unit to connect.
In a first aspect of the present invention, preferably, described shielding processing is to be undertaken by n mask bit, and the original state of all mask bits is represented not conductively-closed of corresponding requests, the number of modules that the n representative has bus arbiter unit to connect.
In a first aspect of the present invention, preferably, described shielding processing comprises: according to the logical relation of described request position and described mask bit, and the request that shielding has been responded.
In a first aspect of the present invention, preferably, all requests in a request group are all by after the response, and this request group is disabled, and can handle next request group constantly.
In a first aspect of the present invention, preferably, described invalidation step comprises: request position in the described queue unit and corresponding mask bit thereof are reset to original state respectively.
In second aspect, the invention provides a kind of bus arbiter unit that guarantees to visit sequencing, comprising: queue memory, the request grouping that is used for difference is sent is constantly stored; The bit mask unit is used for moment request group is the earliest carried out shielding processing to mask the request that has been responded; And arbitration unit, be used for the request group after the shielding is arbitrated to select one of them request to respond.
In a second aspect of the present invention, preferably, described queue memory is first-in first-out (FIFO) queue memory, and a total n queue unit, each queue unit are stored all requests in a certain moment, the number of modules that the n representative has bus arbiter unit to connect.
In a second aspect of the present invention, preferably, described queue unit is the register that n request position arranged, and the original state of all request positions represents not have request, the number of modules that the n representative has bus arbiter unit to connect.
In a second aspect of the present invention, preferably, described bit mask unit is the register that n mask bit arranged, and the original state of all mask bits represents that corresponding requests is not responded, the number of modules that the n representative has bus arbiter unit to connect.
In a second aspect of the present invention, preferably, described bus arbiter unit also comprises the logic gate unit, is used for the logical relation according to described request position and described mask bit, the request that shielding has been responded.
The present invention sends the first response of arriving first of request by guaranteeing the different moment by a plurality of modules, and then the priority of a plurality of requests that arrive according to synchronization is again arbitrated, the sequencing that has guaranteed the multimode reference-to storage is not upset, and has satisfied the correctness of a plurality of module cooperative work.
Description of drawings
Below with reference to accompanying drawings specific embodiments of the present invention is described in detail, in the accompanying drawings:
Fig. 1 is the block diagram according to bus arbiter unit of the present invention;
Fig. 2 is the logic diagram of bit mask and each moment unit of FIFO; And
Fig. 3 is the block diagram of the comparer tree of arbitrated logic realization.
Embodiment
The present invention has designed a kind of like this bus arbiter unit: when bus arbiter unit is idle, if when a plurality of request is arranged simultaneously, produce application result according to certain priority arbitration strategy, other requests that do not responded are suspended, and preserve.When bus arbiter unit is busy, the request of follow-up arrival will directly be suspended, and after guaranteeing that this moment, all requests before all disposed, could handle all requests that this cycle arrives.In brief, this bus arbiter unit can guarantee the first response of arriving first of a plurality of module requests, considers the priority of each module self again, has guaranteed that the sequencing of multimode reference-to storage is not upset, and has satisfied the correctness of a plurality of module cooperative work.
Fig. 1 is the block diagram according to bus president of the present invention unit.
As shown in Figure 1, comprise first-in first-out (FIFO) queue memory, bit mask unit, arbitrated logic according to bus president of the present invention unit.
First-in first-out (FIFO) queue memory one total n level, the number of modules that the n representative has bus arbiter unit to connect, all effective requests that each grade a certain moment of preservation sends.Worst situation is that each module is sent request in the different moment, and busy all modules that cause of bus arbiter all can not get asking to finish response.Because module must be waited for its current request and just can send next request after finishing.So, need only preserve n request constantly at the most for the system of n module.All, the logical depth n of FIFO preferably equals total number of modules and gets final product.Every grade of queue unit of fifo queue storer is the register of a n position, and on behalf of its respective modules, each in the register whether send request of access at current time.Should be pointed out that described first-in first-out (FIFO) queue memory can be that any one can realize the queue memory that request divided into groups by constantly.
When bus finds that certain module is sent request, will send a request pulse (Request_unmasked), this request pulse is a clock cycle.This has a plurality of modules constantly and sends request simultaneously, and the fifo queue storer will be immediately writes fifo queue with all requests of current time as a unit so, is about to the unit that these all requests constantly write fifo queue.Such as, realize that the register of each queue unit has 5, corresponding respectively 5 modules that are connected to bus arbiter unit.When 1,2,3 modules are sent request, when 4,5 modules were not sent request, according to the request pulse that bus is sent, it was 1,1,1,0,0 that the request of register writes the result, and they can be referred to as not carry out the request position before the shielding processing.
When in the fifo queue storer certain waits for that unit finds that there is not effective unit in front (mean all requests dispose in the unit of this waits unit previous moment), this wait unit will be by ejection (beginning to handle request wherein).At first, bit mask (mask) being carried out in all requests wherein handles.Then, will issue arbitrated logic (Arbiter) through all (n position) requests (Request_masked) after the shielding processing.Arbitrated logic is arbitrated according to the fixed priority of module, and provides arbitration result (arbiter result).Should be pointed out that in the arbitrated logic of bus president unit, each module all has priority register, can be by good its fixing priority of software arrangements, so that accept arbitration.Arbitration result (arbiter result) also is the n position, and the number of modules that the n representative has bus arbiter unit to connect is 1 by the response bit of respond module, and other positions are 0.
According to this arbitration result, bus arbiter unit will feed back to by the handshake ready of respond module and be changed to effectively.By this effective handshake, thought that by respond module current accessed is processed, can send next request of access.
In like manner, bus arbiter unit will feed back to be not changed to by the handshake ready of respond module invalid.By this invalid handshake,, cannot send next request of access for being thought that by respond module current accessed is suspended.
If request requires the storer of visit busy, then bus arbiter unit will be closed, and can think simply that bus arbiter unit is by " hang-up ".At this moment, waiting list must be waited for and add to the request of access of all arrivals all.As mentioned above, this waiting list is a fifo queue, comprises a plurality of unit, and its corresponding all not processed requests are constantly all preserved in each unit.When the storer of request requirement visit was idle, the request elder generation that arrives (synchronization arrival) earlier ejected from waiting list, accepts the processing of bus arbiter unit.Wait for that all requests in the residue unit are suspended in the sequence, corresponding module is waited for.
When storer finishes current accessed or storer when idle, bus arbiter unit is resumed work.Bus arbiter unit is at first checked all requests of waiting in the unit that ejects in the sequence, and gives the highest request of certain priority with response according to the priority of module.And, if a certain request is responded, so in the request of the correspondence position that ejects the unit with conductively-closed.
Simultaneously, other requests in this unit continue to be suspended, till a last visit finishes.Should be pointed out that the described request that other are suspended (not responded) still is in waits for the unit that ejects in the sequence, so will preferentially obtain handling when bus arbiter unit is idle next time.In other words, other requests that current time does not meet with a response will continue to accept arbitration according to the fixed priority of module and select, till all ask all to dispose up to this moment when bus next time is idle.
As mentioned above, a first-in first-out fifo queue is formed in a plurality of unit in the wait sequence.Therefore, wait for that each unit in the sequence will eject according to the principle (request sequential) of first-in first-out to arbitrated logic, till waiting for that sequence is sky.In other words, the request that arrives constantly in the back will be accepted arbitration according to fixed priority and is selected after will waiting for all processed the finishing of all requests of previous moment when bus next time is idle.
Like this, with regard to strict guarantee elder generation constantly handle according to request, in the request of synchronization, arbitrate then according to module priority.
Fig. 2 is the logic diagram of bit mask and each moment unit of FIFO.
The effect that bit mask is handled is: when there is a plurality of request in a cell fifo, need carry out shielding processing earlier to these requests, arbitrate, wherein, have only the request of not conductively-closed just to accept arbitration.Whenever handle the request of a module, need to ask to give arbiter again after the shielding (cancellation), to avoid repetitive requests.Be readily appreciated that when cell fifo was for the first time processed, all requests are not conductively-closed all, can accept arbitration all.
In order to realize that the mask bit that bit mask is handled is a n bit register, wherein each equals 0 and represents respective modules to be responded in the request in this moment, should conductively-closed.Equal 1 and represent respective modules also not responded, can send request in the request in this moment.All mask bits are 1 under the default situations.
For instance, n=5, the number of modules that representative has bus arbiter unit to connect is 5.Suppose from request_unmasked_0 to request_unmasked_5 all to be 1, represent these 5 modules of synchronization all to send request.When representing this unit constantly by At time of eject, 5 mask bits of its correspondence should be 1 all, represent the request of these 5 modules all also not responded, and can send request.Each not the request position (request_unmasked) of shielding processing and mask bit (mask) by judge output shielding processed request position (request_masked) with door.Under above-mentioned hypothesis, all request_masked are 1, represent all requests all will send into arbitrated logic, accept the selection according to module priority, and the module that priority is the highest meets with a response.According to the arbitration result of sending by arbitrated logic (arbiter) (arbiter result),, represent the request of this module correspondence to be responded with the screening-off position 0 of processed request correspondence.Like this, when selecting, this request conductively-closed (its request_unmasked and mask with gate logic judged result be 0) no longer participates in arbitration and selects next time.
So go round and begin again, when the request after the shielding only surplus one effectively and the pairing request quilt in this position when responding (request_masked==arbiter result), represent the interior all effective requests of current cell fifo all processed.At this moment, Request_unmasked positions all in this cell fifo are by clear 0 (being labeled as clear_all_request) among the figure, and all corresponding mask bits are put 1 (being labeled as set_all_mask among the figure), promptly this cell fifo become invalid.That is to say that after all processed the finishing of all requests in a last moment, the fifo queue storer can begin to handle next cell fifo constantly.
The selection that should be pointed out that the expression meaning of each above-mentioned register-bit and logic gate is not restrictive but optionally, they can be realized by other expressions and other logic gates.
Fig. 3 is the block diagram of the comparer tree of arbitrated logic realization.
Arbitrated logic is not handled new request of access during memory access.When storer is idle, to arbitrate according to the priority of each module, the module that the numerical value of priority register is minimum (module that priority is the highest) obtains access rights.If exist a plurality of module priority to equate and all be in the situation of current limit priority, then select one of them module by the hardware link position, be exactly the module of directly choosing the left side in two modules in the drawings.
As shown in Figure 3, the tree end of the comparer tree that arbitrated logic is realized has a plurality of nodes, each node to represent the priority of a module and the request of sending thereof.Arbitrated logic is by being close to comparing in twos of 2 nodes, and module that the two medium priority is higher and the request of sending thereof are as the node of following one deck.Such as, the priority of module 0 is A, the priority of module 1 is B, by relatively judging (A＞=B).When A＞B, generate node, the priority of its representation module 0 and the request of sending thereof of one deck down.When A=B, select a module in 0,1 by the hardware link position, with this module and the request of sending thereof node as time one deck.Simultaneously, other adjacent blocks are also comparing, other nodes under generating in one deck.Like this, the tree root in this comparer tree has just drawn the highest module of all these module medium priorities at last, selects the request that it sent to respond then.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited by described claims.
Claims (14)
1. bus arbitration method that guarantees to visit sequencing comprises:
The request grouping that difference is sent is constantly stored;
Moment request group is the earliest carried out shielding processing to mask the request that has been responded; And
Request group after the shielding is arbitrated to select one of them request to respond.
2. according to the bus arbitration method of claim 1, wherein, described storing step comprises:
Difference request group is constantly arranged by first-in first-out (FIFO) formation.
3. according to the bus arbitration method of claim 1, wherein, described each request group is represented that by n request position the original state of all request positions represents not have request, the number of modules that the n representative has bus arbiter unit to connect.
4. according to the bus arbitration method of claim 1, wherein, described arbitration step comprises:
Priority according to each request in the request group after the shielding is selected, and described priority is pre-configured fixing.
5. according to the bus arbitration method of claim 1, wherein, described response is represented by n response bit, the number of modules that the n representative has bus arbiter unit to connect.
6. according to the bus arbitration method of claim 1, wherein, described shielding processing is to be undertaken by n mask bit, and the original state of all mask bits is represented not conductively-closed of corresponding requests, the number of modules that the n representative has bus arbiter unit to connect.
7. according to the bus arbitration method of claim 3 or 6, wherein, described shielding processing comprises:
According to the logical relation of described request position and described mask bit, the request that shielding has been responded.
8. according to the bus arbitration method of claim 4, also comprise:
All requests in a request group are all by after the response, and this request group is disabled, and can handle next request group constantly.
9. according to any one bus arbitration method in the claim 3,6,8, wherein, described invalidation step comprises:
Request position in the described queue unit and corresponding mask bit thereof are reset to original state respectively.
10. bus arbiter unit that guarantees to visit sequencing comprises:
Queue memory, the request grouping that is used for difference is sent is constantly stored;
The bit mask unit is used for moment request group is the earliest carried out shielding processing to mask the request that has been responded; And
Arbitration unit is used for the request group after the shielding is arbitrated to select one of them request to respond.
11. bus arbiter unit according to claim 10, wherein, described queue memory is first-in first-out (FIFO) queue memory, a total n queue unit, each queue unit is stored all requests in a certain moment, the number of modules that the n representative has bus arbiter unit to connect.
12. according to claim 11 bus arbiter unit, wherein, described queue unit is the register that n request position arranged, the original state of all request positions represents not have request, the number of modules that the n representative has bus arbiter unit to connect.
13. according to the bus arbiter unit of claim 10, wherein, described bit mask unit is the register that n mask bit arranged, the original state of all mask bits represents that corresponding requests is not responded, the number of modules that the n representative has bus arbiter unit to connect.
14. the bus arbiter unit according to claim 12 or 13 also comprises:
The logic gate unit is used for the logical relation according to described request position and described mask bit, the request that shielding has been responded.
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| CNA2008101185940A CN101344871A (en) | 2008-08-20 | 2008-08-20 | Bus arbitration unit for guaranteeing access sequence and its implementing method |
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| CN102129412A (en) * | 2010-01-18 | 2011-07-20 | 厄塞勒拉特公司 | Access scheduler |
| CN103218326A (en) * | 2013-04-24 | 2013-07-24 | 上海华力创通半导体有限公司 | Comprehensive arbiter device |
| CN103914413A (en) * | 2014-04-18 | 2014-07-09 | 东南大学 | External-storage access interface for coarseness reconfigurable system and access method of external-storage access interface |
| CN104346303A (en) * | 2013-08-08 | 2015-02-11 | 中兴通讯股份有限公司 | Bus arbitration method and device |
| CN106155952A (en) * | 2016-06-24 | 2016-11-23 | 武汉光迅科技股份有限公司 | A kind of I2C multi-computer communication method with priority arbitration mechanism |
| CN106484531A (en) * | 2016-09-18 | 2017-03-08 | 上海顺久电子科技有限公司 | One memory visit and arbitration method, circuit and device |
| CN106776390A (en) * | 2016-12-06 | 2017-05-31 | 中国电子科技集团公司第三十二研究所 | Method for realizing memory access of multiple devices |
| CN106776423A (en) * | 2016-11-25 | 2017-05-31 | 天津大学 | Using the asynchronous arbitration tree circuit of priority automatic switchover arbitration unit |
| CN106951391A (en) * | 2017-02-15 | 2017-07-14 | 合肥芯荣微电子有限公司 | Point-to-point interconnection bus access mask system and method in a kind of chip |
| CN106953896A (en) * | 2017-02-21 | 2017-07-14 | 深圳市智物联网络有限公司 | The data transmission method and adapter of adapter |
| CN108415860A (en) * | 2017-02-09 | 2018-08-17 | 慧与发展有限责任合伙企业 | Main equipment task is distributed between bus queue |
| CN110875867A (en) * | 2020-01-20 | 2020-03-10 | 南京凌鸥创芯电子有限公司 | Bus access arbitration device and method |
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| CN102129412A (en) * | 2010-01-18 | 2011-07-20 | 厄塞勒拉特公司 | Access scheduler |
| CN103218326A (en) * | 2013-04-24 | 2013-07-24 | 上海华力创通半导体有限公司 | Comprehensive arbiter device |
| CN103218326B (en) * | 2013-04-24 | 2016-11-23 | 上海华力创通半导体有限公司 | Comprehensive arbiter device |
| CN104346303A (en) * | 2013-08-08 | 2015-02-11 | 中兴通讯股份有限公司 | Bus arbitration method and device |
| CN103914413A (en) * | 2014-04-18 | 2014-07-09 | 东南大学 | External-storage access interface for coarseness reconfigurable system and access method of external-storage access interface |
| CN106155952B (en) * | 2016-06-24 | 2019-04-09 | 武汉光迅科技股份有限公司 | A kind of I2C multi-computer communication method with priority arbitration mechanism |
| CN106155952A (en) * | 2016-06-24 | 2016-11-23 | 武汉光迅科技股份有限公司 | A kind of I2C multi-computer communication method with priority arbitration mechanism |
| CN106484531A (en) * | 2016-09-18 | 2017-03-08 | 上海顺久电子科技有限公司 | One memory visit and arbitration method, circuit and device |
| CN106484531B (en) * | 2016-09-18 | 2019-12-24 | 上海顺久电子科技有限公司 | Memory access arbitration method, circuit and device |
| CN106776423B (en) * | 2016-11-25 | 2019-08-20 | 天津大学 | Automatically switch the asynchronous arbitration tree circuit of arbitration unit using priority |
| CN106776423A (en) * | 2016-11-25 | 2017-05-31 | 天津大学 | Using the asynchronous arbitration tree circuit of priority automatic switchover arbitration unit |
| CN106776390A (en) * | 2016-12-06 | 2017-05-31 | 中国电子科技集团公司第三十二研究所 | Method for realizing memory access of multiple devices |
| CN108415860B (en) * | 2017-02-09 | 2021-06-04 | 慧与发展有限责任合伙企业 | Machine-readable storage medium, computing system, and method of master device of computing system |
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| CN106951391A (en) * | 2017-02-15 | 2017-07-14 | 合肥芯荣微电子有限公司 | Point-to-point interconnection bus access mask system and method in a kind of chip |
| CN106951391B (en) * | 2017-02-15 | 2020-02-11 | 合肥芯荣微电子有限公司 | System and method for shielding access of point-to-point interconnection bus in chip |
| CN106953896B (en) * | 2017-02-21 | 2020-05-01 | 深圳市智物联网络有限公司 | Data transmission method of adapter and adapter |
| CN106953896A (en) * | 2017-02-21 | 2017-07-14 | 深圳市智物联网络有限公司 | The data transmission method and adapter of adapter |
| CN110875867A (en) * | 2020-01-20 | 2020-03-10 | 南京凌鸥创芯电子有限公司 | Bus access arbitration device and method |
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| CN111830872B (en) * | 2020-07-17 | 2022-02-25 | 珠海格力智能装备有限公司 | Robot control method, device, storage medium and processor |
| CN113791892A (en) * | 2021-07-30 | 2021-12-14 | 北京智芯微电子科技有限公司 | Data path arbitration method, data path arbitration device and chip |
| CN113791892B (en) * | 2021-07-30 | 2024-03-26 | 北京智芯微电子科技有限公司 | Data path arbitration method, data path arbitration device and chip |
| CN114138706A (en) * | 2021-10-29 | 2022-03-04 | 北京中科昊芯科技有限公司 | Multifunctional arbiter, arbitration method, chip and product |
| CN114138706B (en) * | 2021-10-29 | 2022-07-08 | 北京中科昊芯科技有限公司 | Multifunctional arbiter, arbitration method, chip and product |
| CN115186251A (en) * | 2022-09-09 | 2022-10-14 | 北京紫光芯能科技有限公司 | Matrix network verification method and device |
| CN116521097A (en) * | 2023-07-03 | 2023-08-01 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
| CN116521097B (en) * | 2023-07-03 | 2023-09-08 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
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