CN104834629B - The central processing unit of bus-type - Google Patents
The central processing unit of bus-type Download PDFInfo
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- CN104834629B CN104834629B CN201510284847.1A CN201510284847A CN104834629B CN 104834629 B CN104834629 B CN 104834629B CN 201510284847 A CN201510284847 A CN 201510284847A CN 104834629 B CN104834629 B CN 104834629B
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Abstract
The present invention discloses a kind of central processing unit of bus-type, including controller, at least one function module, bus and bus control unit, wherein：The bus connects the controller and the function module；The bus control unit connects the bus, is used for the interaction of described information with the corresponding bus of information type selection that the function module interacts according to the controller.The central processing unit of the bus-type of the present invention is largely used for the circuit of point-to-point connection without setting on the controller, various signals can be transmitted by class in bus, prevent rear end wiring from congestion problems occur, so that the architectural framework of central processing unit becomes simple, regular, when signal transmission, also can quickly, orderly.
Description
Technical field
The present invention relates to central processing unit more particularly to a kind of central processing units of bus-type.
Background technology
With the high speed development of electronic chip technology, CPU (central processing unit) is designed towards high complexity and high density side
To development.While CPU design difficulty increases, the high complexity and high density of CPU bring the reliability of its performance and set
The problems such as operability of meter.Wherein, the architecture design of CPU become influence one of its reliability and operability it is leading because
Element.Traditional CPU design technology has been difficult to the needs for meeting modern development.
Fig. 1 is traditional CPU architecture schematic diagram.With reference to Fig. 1, traditional CPU architecture mainly includes controller 1, decoding module
2nd, execution module 3, result buffer module 4 and result treatment module 5.Wherein, using point-to-point between controller and these modules
Connection mode.Modules are directly shaken hands, and signal uses point-to-point mode, is directly transmitted to another mould by a module
Block.As shown in Figure 1, the controller in CPU directly sends signal, and receive the signal returned from these modules to these modules.
In addition, the type of flow of the data-signal between modules is also point-to-point mode.For example, decoding module 2 will be from control
The signal that device receives after execution module 3 has performed the instruction of signal, will perform knot into execution module 3 is sent to after row decoding
Fruit is sent to result buffer module 4, and as a result buffer module 4 sends the signal to result treatment module 5 again.Due to traditional CPU framves
The limitation of point-to-point connection mode in structure, signal transmission can only also use point-to-point communication mode.Including address signal,
All signals including data-signal and control signal are sent out from a module, directly reach another receiving module.This point
To the design structure of point, the circuit directly being connect in CPU with controller is more, and not only resulting in the architectural framework of CPU becomes multiple
It is miscellaneous and in disorder, and the signal of data transmission can be caused chaotic.This can increase the difficulty and time cost of design CPU architecture.With
Being continuously increased for CPU scales, this influence is further apparent.Especially for for the CPU of million gate leves or ten million gate leve, by biography
The problems such as system mode carries out will appear congestion during the wiring of rear end.
Invention content
For problems of the prior art, according to an aspect of the invention, there is provided a kind of center of bus-type
Processor, including controller, at least one function module, bus and bus control unit, wherein：The bus connects the control
Device processed and the function module；The bus control unit connects the bus, according to the controller and the function module
Interactive information type selects interaction of the corresponding bus for described information.
The central processing unit of the present invention is largely used for the circuit of point-to-point connection, various letters without setting on the controller
It number can be transmitted in bus by class, prevent rear end wiring from congestion problems occur so that the architectural framework of central processing unit becomes
Simply, it is regular, during signal transmission also can quickly, it is orderly.
In some embodiments, the ground that the bus control unit is transmitted according to the controller and the function module
Location signal and/or data-signal and/or the type for controlling signal are corresponding to select address bus and/or data/address bus and/or control
Bus.
Different signals is sent and received by different buses so that address signal, data-signal and control letter
Number will not be chaotic in transmission, improve the speed and precision of signal transmission.
The bus that in some embodiments, the controller is selected by the bus control unit and decoding module,
Execution module, result buffer module and result treatment module interactive information.
In some embodiments, each function module is added by way of connecting bus or being removed from bus
Enter in the general frame of CPU or removed from the framework.
Each function module in present embodiment can freely in CPU increase or removal, not only facilitate to CPU's
Design is changed and follow-up R＆D work, and the CPU designed is very simple clear on physics framework, processing and making
It is very convenient, efficient.
In some embodiments, the item number of the bus is at least 3, including at least an address bus, a number
According to bus and a controlling bus.
In some embodiments, the bus uses TDMA (Time division multiplex access, the time-division
Multiple access) mode address bus, data/address bus and controlling bus are merged into 1 or 2 buses.Wherein, TDMA is in net
It is applied in network with a line transmission multichannel data, the technology based on application circuit at times.
Pass through the design method of flexible bus so that the circuit of CPU is more regular, expands its accommodation.
According to another aspect of the present invention, a kind of central processing unit of bus-type is provided, including controller, Duo Gegong
Energy module and bus unit, wherein, the bus unit includes bus and bus control unit, the bus control unit connection
The bus is used for described information according to the controller with the corresponding bus of information type selection that each function module interacts
Interaction.
In some embodiments, the bus unit further includes the interface for connecting the controller and the function module
Module and timing coordination module.
In the present embodiment, bus and bus control unit and interface module and timing coordination module can be integrated in bus
In unit, this modular Integrated design mode is not only very convenient in production and use, but also causes high density and height
The CPU of complexity is simpler, regular in design.
The central processing unit of the present invention is largely used for the circuit of point-to-point connection, various letters without setting on the controller
It number can be transmitted in bus by class, prevent rear end wiring from congestion problems occur so that the architectural framework of central processing unit becomes
Simply, it is regular, during signal transmission also can quickly, it is orderly.
Description of the drawings
Fig. 1 is traditional CPU architecture schematic diagram；
Fig. 2 is the CPU architecture schematic diagram of an embodiment of the present invention；
Fig. 3 is the address response circuit diagram of an embodiment of the present invention；
Fig. 4 is the register group module of an embodiment of the present invention and the schematic diagram of three data bus communications；
Fig. 5 is the CPU architecture schematic diagram of another embodiment of the present invention；
Fig. 6 is the timing coordination module diagram of an embodiment of the present invention.
Specific embodiment
The invention will now be described in further detail with reference to the accompanying drawings.
Fig. 2 is the CPU architecture schematic diagram of an embodiment of the present invention.The present invention proposes a kind of completely new CPU architecture design
Pattern.As shown in Fig. 2, CPU of the present invention includes controller 1, function module 2, bus 3 and bus control unit 4.Wherein, function
Module 2 includes decoding module 21, execution module 22, result buffer module 23, result treatment module 24 this four function modules.Control
Device 1 processed is connect with each function module 2 by bus 3.Bus control unit 4 connects the bus 3.
The present invention in traditional CPU architecture by increasing bus 3 and bus control unit 4.Bus control unit 4 controls
The transmission mode of signal in bus 3, plays the role of the central hub of signal transfer control.According to bus-type in the present embodiment
CPU design mode, this multiple function module can be considered as multiple IP Core (Intellectual Property core,
IP core, hereinafter referred to as IP kernel).Wherein IP kernel is the circuit function with specific function described with hardware description language
Module, this circuit function module, which can be transplanted in different semiconductor technologies, carries out IC Chip Production.
The framework of above-mentioned CPU changes traditional CPU and sets similar to the pattern of SoC (System On Chip system level chips)
The internal modules of meter are directly shaken hands, and signal is directly transmitted to the design method of another module, substitution tradition by a module
Each function module of modules inside CPU.Each function module in the present invention is also referred to as " IP like module ".
Each function module in present embodiment freely can increase or remove in CPU, not only facilitate to CPU's
Design modification and follow-up R＆D work, and the CPU designed is very simple clear in physics framework, processing and make nor
It is often convenient, efficient.
Proposed by the present invention is a kind of new CPU architecture, though each function module 2 is referred to as " IP like mould inside CPU
Block ", but it is different from existing IP modules, and therefore, previous ripe bussing technique cannot adapt to the needs of the present invention completely.Cause
This, the present invention is devised and a kind of meets CPU design requirement of the present invention according to the functional characteristics of function module 2 each inside CPU
Bus.
In some embodiments, the item number of the bus is at least 3, including at least an address bus, a number
According to bus and a controlling bus.In some embodiments, the bus is total by address bus, data by the way of TDMA
Line and controlling bus are merged into 1 or 2 buses.Wherein, TDMA is applied in a network with a line transmission multichannel
Data, the technology based on application circuit at times.In the present embodiment, bus 3 employs three-bus structure, which has three always
Line respectively transmits the address bus of address signal, transmits the data/address bus of data-signal, and the control of transmission of control signals is total
Line.Bus control unit 4 according to address signal, data-signal and control signal type, select respectively corresponding address bus,
Data/address bus and controlling bus are classified the signal in controller 1 and four function modules, interaction quickly, orderly.By
Each " IP like module " can take the mode of " playing with building blocks " to add in CPU's in the convenience of IP kernel module transplanting, the present invention
It is removed in general frame or from the framework.
The details that an embodiment illustrates that needs are paid close attention to during the specific design of CPU is set forth below：
First, design CPU inside each function module (such as decoding module, execution module, result buffer module and
Result treatment module when) when, mainly consider its inside and outside design.
About the interior design of each function module, according to the logical architecture of each Functional Design module, using Hardware description language
Its function is described in speech, its determining function is verified by functional simulation.Bus-type CPU then takes the side similar to broadcast
Formula is carried out orderly " calling " by bus control unit, and each function module takes the mode of " response " to complete and CPU
Communication.This just needs to be designed the element of Address Recognition.The element of so-called Address Recognition is exactly function module to address
The response circuit of bus.
Fig. 3 is the address response circuit diagram of an embodiment of the present invention.The address of each function module is in design
Just it has been determined that and among these addresses are solidificated in its hardware related circuit, which is known as module curing address.Such as Fig. 3
Shown, when response bus address, bus address is compared with module curing address by comparison circuit, and output is compared
As a result.If the two addresses are consistent, address matching is correct, and response circuit notifies this function module to perform relevant action,
Otherwise relevant action is not performed.
For designing the element of Address Recognition of execution unit.When instruction data flow arrival execution unit, need to perform
When, bus control unit is according to the control transmission data address of control unit.This address can reach any one extension
The function module being loaded in bus, but the component of only appropriate address identification can just identify this address, then perform corresponding
Operation.In circuit level, the element of Address Recognition is mainly realized by a comparison circuit.By the address in bus and work(
Energy inside modules address is compared by a comparison circuit.If the two matches, the transmission work of data is carried out, it is no
Then, corresponding function module is not responding to.
Bus-type CPU and tradition CPU difference lies in, traditional CPU directly controls function module by control unit,
The transmission of signal is transmitted and controlled including address, and bus-type CPU exchanges information by bus.About the outer of each function module
Portion designs, and is designed primarily directed to the external interface of module, this needs is adapted with bus-type CPU design.Specifically, due to
These modules work in a manner that carry is in bus, and therefore, the external interface of these modules is required to same CPU's
Bus signals match, i.e., the bus signals of CPU will meet the requirement of each function module interface.Using instruct execution module as
Example, normal work need to perform enable signal, address date input signal, data input signal and data output signal,
So data/address bus, address bus and controlling bus will can provide enable signal, address signal and data-signal.Such ability
Ensure the normal work of module.
This construction characteristic of bus-type CPU makes it in design without connecting various types of circuits on the controller,
During can alleviating or avoiding back-end realization it is possible that the problems such as local wiring congestion.So that the architectural framework of CPU
Become simple, regular, it also can quickly, orderly during signal transmission.
In addition, the function module increase in the CPU of the present invention is very simple and convenient, the design to CPU is not only facilitated to change
With follow-up R＆D work, and so that CPU is very simple clear on physics framework, processing and making are convenient to and high
Effect.
For convenience of description, four function modules are only devised in the present embodiment, can also be increased according to actual needs
Add deduct less specific module, such as increases accumulator module, arithmetical operation module etc..In addition, three total knot in the present embodiment
Structure can also be modified according to actual conditions.For example, data/address bus, address bus and controlling bus are merged, this master
It applies in some CPU designs of less demanding for operating rate.For speed it is of less demanding when, address, data and
Control signal need not provide parallel.At this moment, three buses can be merged into one or two buses, TDMA is taken by control unit
Mode.I.e. for completing a cpu function, in same bus, different ground is provided respectively in different processing stages
Location, data or control signal can reduce the complexity of circuit design in this way.
On the contrary, in the CPU design high to rate request, the quantity of same type bus can be increased.It is for example, more having
It reads to write in the CPU of structure register group more, data/address bus can be increased by one as a plurality of read-write bus.Refer in this way in execution
When order, the multichannel data by register group may be used parallel form and reach corresponding function module, so as to improve
The data throughput capabilities of system, and then improve processing speed.Without departing from the concept of the premise of the invention, to bus structures
The several modifications and improvements made, these belong to protection scope of the present invention.An embodiment is enumerated below illustrates three datas
The realization method that bus communicates with register group module.
Fig. 4 is the register group module of an embodiment of the present invention and the schematic diagram of three data bus communications.Such as Fig. 4 institutes
Show, register group includes two data reading ports and one is write data port.Two data reading ports are total with two datas respectively
Line connects, for reading data therein.It writes data port for one to connect with remaining a data bus, for writing into it
Enter data.Wherein register group is a storing mechanism using register architecture, for storing data or instruction, function class
It is similar to memory.
Fig. 5 is the CPU architecture schematic diagram of the bus-type of another embodiment of the present invention.The CPU includes controller 1, more work(
It can module 2 and bus unit 5.The structure of the CPU of present embodiment has following area compared with the embodiment in above-mentioned Fig. 2
Not：On the one hand, bus 3, bus control unit 4 are subjected to integrated processing in present embodiment, form bus unit 5, the opposing party
Face increases interface module 6 and timing coordination module 7.
Modular Integrated design mode, it is not only very convenient in production and use, but also high density and height are answered
It is simpler, regular during the CPU design of miscellaneous degree.
Wherein, when designing CPU architecture, bus 3 employs above-mentioned three-bus structure, including to transmit address, data
With address bus, data/address bus and the controlling bus of control signal.The transmission and exchange of signal are required for through this three-bus.
Bus-type CPU architecture proposed by the invention connects the module inside CPU in the form of " IP like module " with bus
It connects, completes its corresponding function.When designing the structure module, because different function modules is due to the characteristic of itself, operation speed
Degree differs.Such as the arithmetic unit inside CPU, particularly multiplying unit, in general speed is slow, is the sequential bottle of system
Neck.Present embodiment is to coordinate the sequential that all parts are generated by service speed difference by setting timing coordination module 7
Problem.
Fig. 6 is the timing coordination module diagram of an embodiment of the present invention.As shown in fig. 6, timing coordination module 7 includes
For judging the sequential decision circuitry 71 of data time sequence priority, delay circuit 72 and output circuit 73.Wherein, sequential decision circuitry
71 be the circuit of a routine in CPU design.When designing tradition CPU, sequential decision circuitry 71 is arranged in the control of CPU
In device, judge come the work schedule to CPU.And the sequential decision circuitry of the present invention is arranged among timing coordination module,
A relatively independent unit is made, for coordinating the work schedule of CPU.Sequential decision circuitry 71 is comprehensive in setting
Consider the timing conditions of CPU in all cases, the timing requirements of design are solidificated among circuit in the form of hardware.Example
Such as：CPU continuously performs multiplying order and data movement instruction.When the execution of data movement instruction needs front multiplying order to perform
Result when, due to multiplying order, to perform speed slower relative to the data movement instruction of back, multiplication during data transmission
The result of instruction generates not yet, this when, sequence problem just produced.In such cases, the data of back is needed to transmit to refer to
The execution for waiting for front multiplying order is enabled, until multiplying order generates correct result.For another example：CPU performs multi-cycle instructions (i.e.
Performing an instruction needs the time of multiple clock cycle.) when, the execution of associated instruction is but the monocycle, is being instructed
It performs the monocycle and multi-cycle instructions whens will generate confusion in sequential, the problem of so as to bring in sequential.It is at this point, single
Cycles per instruction needs that multi-cycle instructions is waited for perform completion.
Timing coordination module 7 coordinate CPU sequential mode be：Decision circuitry 71 acquires current needs and performs and be carrying out
Hardware circuit signal (such as control signal and data signal), believe with the timing requirements that are solidificated in inside sequential decision circuitry 71
(this comparison procedure can be realized by conventional comparison circuit) number is compared, result by comparing obtains：If letter
It number needs to postpone, postpones signal is sent to delay circuit 72, signal does appropriate delay in delay circuit 72, then passes through
73 output signal of output circuit；If signal does not need to postpone, non-delayed circuit signal is passed through to the bypass of delay circuit 72
Output circuit 73 is sent to, 73 output signal of output circuit is used for late-class circuit.
An example is set forth below and illustrates the realization method that sequential adjusting is carried out by timing coordination module 7.It is flowing
In the CPU of waterline design, multiplier is typically device very slow in a sequential, and multiplication operation of execution generally requires several
The time of clock cycle.In this way, when the faster device of sequential is after its operation is quickly performed, need to obtain the knot of multiplication operation
Fruit just produces the mismatch problem in sequential.At this moment sequential adjustment module 7 can to sequential faster device sequential into
Line delay is adjusted so that their sequential matches.
It, can be with when design selection and specific design in order to reach quick, high reliability the design requirement of bus
With reference to the characteristics of each unit, targetedly it is designed.Bus unit connects CPU internal controllers and multiple function moulds
Block, therefore, interface module 6 can according to the functional characteristics of modules come planning and designing module interface, can with it is three total
The good docking of line.
Therefore, the overall frame of the mode that plays with building blocks from CPU can be taken by being each considered as the function module of IP kernel module
It is increased or decreased in structure.Therefore the function module increase in the CPU of the present invention is very simple and convenient, not only facilitates and CPU is set
Meter modification and follow-up R＆D work, and so that CPU is very simple clear on physics framework, processing and making are also very square
Just and efficiently.It is relatively easy neat in the CPU structures, CPU is also made to ensure that design is realized easy to operate on architectural framework
Property and work on reliability.To adapt to the requirement that current CPU increasingly develops to high complexity and high density direction.
In addition, signal is transmitted by the bus 3 controlled by bus control unit 4.This design is without in controller
The various types of circuits of upper connection, during preventing back-end realization it is possible that the problems such as routing congestion.So that the body of CPU
System structure becomes simple, regular, also can quickly, orderly during signal transmission.
Above-described is only some embodiments of the present invention.For those of ordinary skill in the art, not
Under the premise of being detached from the invention design, various modifications and improvements can be made, these belong to the protection model of the present invention
It encloses.
Claims (9)
1. a kind of central processing unit of bus-type, including controller, at least one function module, bus and bus control unit,
Wherein：
The controller is connect with each function module by the bus；
The bus control unit connects the bus, is selected according to the information type that the controller is interacted with the function module
Interaction of the corresponding bus for described information is selected, wherein, described information type is address signal, data-signal and control signal
In one kind.
2. central processing unit according to claim 1, wherein,
The controller passes through the bus that the bus control unit selects and decoding module, execution module, result buffer module
With result treatment module interactive information.
3. central processing unit according to claim 1 or 2, wherein,
The function module adds in the main frame of the central processing unit by way of connecting bus or being removed from bus
It is removed in structure or from the framework.
4. central processing unit according to claim 3, wherein,
The bus includes at least an address bus, a data bus and a controlling bus.
5. central processing unit according to claim 4, wherein,
Described address bus, data/address bus and controlling bus are by the way of time division multiple acess.
6. central processing unit according to claim 3, wherein,
The function module includes decoding module, execution module, result buffer module and result treatment module, wherein,
The command signal of the controller is exported after the decoding of the decoding module to execution module, and the execution module is held
The implementing result that row described instruction signal obtains is exported through the result buffer module to the result treatment module, feeds back to institute
State controller.
7. a kind of bus-type central processing unit, including controller, multiple function modules, bus unit, wherein,
The bus unit includes bus and bus control unit, and the controller passes through described total with the multiple function module
Line connects；
The bus control unit connects the bus, is selected according to the information type that the controller is interacted with each function module
Interaction of the corresponding bus for described information is selected, wherein, described information type is address signal, data-signal and control signal
In one kind.
8. central processing unit according to claim 7, wherein,
The bus unit, which further includes, connects the controller and the interface module of the function module and timing coordination module.
9. central processing unit according to claim 8, wherein,
The timing coordination module includes for judging the sequential decision circuitry of data time sequence priority, handling for data delay
Delay circuit and output circuit.
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