CN103914413A - External-storage access interface for coarseness reconfigurable system and access method of external-storage access interface - Google Patents
External-storage access interface for coarseness reconfigurable system and access method of external-storage access interface Download PDFInfo
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Abstract
The invention discloses an external-storage access interface for a coarseness reconfigurable system and an access method of the external-storage access interface. The interface comprises an access request input interface unit, a first-level arbitration module, a second-level arbitration module, a control-enabling-signal output interface unit, an access request analysis module and an access request output interface unit. According to the access method, access to an external storage is completed through packaging, priority setting and priority resetting of the first-level arbitration module and priority arbitration and processing of the second-level arbitration module. By the external-storage access interface and the access method thereof, efficiency of accessing to the external storage by computing arrays of the coarseness reconfigurable system is improved, and system blocking caused by serious imbalance of external-data access rights of multiple computing arrays is avoided.
Description
Technical field
The present invention relates to a kind of external memory access interface and access method thereof for coarseness reconfigurable system.
Background technology
At present, the appearance of Reconfiguration Technologies has changed the method for traditional embedded design greatly, restructural calculates the computation schema as a kind of novel time-space domain, has application prospect widely in embedded and high performance calculating field, has become the trend of current embedded system development.
In recent years, restructural calculates and has been widely used in all kinds of engineering applications, mainly comprises: video image processing, digital signal processing, radio communication, data encryption etc.Along with the requirement of all kinds of software application is more and more higher, corresponding, also more and more higher to the performance requirement of reconfigurable system.In order to meet more and more higher performance requirement, the array scale of reconfigurable system is also tending towards expanding.
In general embedded system, often adopt based on SDRAM(synchronous DRAM) external memory storage.In essence, the storage chip of SDRAM structure can not be called direct access device, because its engineering three-dimensional tissue structures (storage block, row, column) makes the access time of inner different storage unit also different.This is mainly postponed to cause by precharge and activation.Data are read and will in sense amplifier, be carried out, a full line at the data place that will read, the process that leaves sense amplifier in is called line activating.Each storage block only has a sense amplifier, namely can only have data line in the state of being activated.When other row data are read, need to carry out line precharge, the content of sense amplifier is write back in memory bank, the row data that reactivation need to read.Therefore, when SDRAM chip conducts interviews, external memory access interface must send different orders according to the state of current operation address corresponding stored piece: if do not gone in state of activation in this storage block, first activate row corresponding to current operation address; Then row corresponding to current operation address are carried out to read-write operation; If have row in this storage block in state of activation (each storage block only may have a line activating), if the row having activated is exactly row corresponding to current operation address, row corresponding to current operation address operated; If activated capable be not row corresponding to current operation address, this storage block is carried out to precharge, the row having activated is closed; Next activate row corresponding to current operation address; Finally row corresponding to current operation address are operated.
As can be seen here, when this ranks tissue characteristics of SDRAM makes to access the storage unit of different rows, owing to need to carrying out the line feed operation of precharge and activation, cause memory unit access asynchronism(-nization), the time delay that line feed process is brought may be several times to tens times of the time of reading, and its time delay meeting causes the reduction of performance.Therefore, in reconfigurable system, for the external memory of SDRAM structure, always there is a minimum delay X cycle in the new accessing operation that reads once, and X is determined by the external memory storage self attributes of reconfigurable system and the clock frequency of system memory access.
Along with the expansion of reconfigurable system scale, in same reconfigurable system, may there are multiple computing arrays, each computing array may conduct interviews to external memory storage.In the time having multiple computing arrays external memory storage to be sent to request of access, just need external memory interface to carry out arbitration access right to these request of access simultaneously.In traditional design, often adopt the arbitration mechanism of fixed priority, but there is defect in this arbitration mechanism, such as in the time that system is carried out every kind of algorithm, need computing array 1 and computing array 2 to access in a large number external memory storage, suppose that the priority of computing array 1 is higher than computing array 2, the data access of computing array 2 can be stoped by the data access of computing array 1 so, cause two computing arrays seriously uneven to the access right of external data, thereby finally cause the computation process of whole system to get clogged.
Summary of the invention
The object of the invention is provides a kind of external memory access interface and access method thereof for coarseness reconfigurable system for the deficiencies in the prior art, not only improve the efficiency of coarseness reconfigurable system computing array access external memory, the system congestion causing because of the serious imbalance of access right while simultaneously avoiding multiple computing arrays simultaneously to external memory access.
In order to realize goal of the invention, the invention discloses a kind of external memory access interface for coarseness reconfigurable system, described interface comprises request of access input interface unit, first order arbitration modules, second level arbitration modules, controls permission signal output interface unit, request of access parsing module and request of access output interface unit; Described request of access input interface unit is for receiving the external memory request of access of coarseness reconfigurable system; Described first order arbitration modules is for by the external memory request of access subpackage between two of request of access input interface unit and be each request of access priority that is responsible for assigning; Described second level arbitration modules is for two input requests in arbitrating access request bag, and the reading in advance of control inputs request; Described control allows signal output interface unit to be used for exporting and controls permission signal; Described request of access parsing module is used for resolving request of access; Described request of access output interface unit is for exporting the request of access of having resolved.
As preferably, for the external memory requirements for access to different is reasonably processed, improve as far as possible the work efficiency of described external memory access interface and access method thereof, need to by test access request number, subpackage, to request of access be responsible for assigning priority, the priority of request of access bag carried out to rotation reset the steps such as processings to the current external memory requirements for access adaptation of classifying, so that post-processed.Described first order arbitration modules comprises request of access subpackage module, request of access packet priority steering logic unit, rotation priority arbitration module; Described request of access subpackage module, for by the subpackage between two at random of current all request of access, becomes separately bag by remaining one if remain request of access number deficiency; Described request of access packet priority steering logic unit is for random request of access of the giving request of access subpackage module structure priority that is responsible for assigning, and responds priority modification signal the priority of request of access bag is modified; Described rotation priority arbitration module, for the priority of arbitrating access request bag, is sent request of access bag the highest current priority into second level arbitration modules, and is returned to priority modification signal to request of access packet priority steering logic unit.
As preferably, minimum delay while accessing based on SDRAM structure external memory in order to eliminate as far as possible, and prevent because different computing arrays cause the computation process of whole system to get clogged to the serious imbalance of the access right of external memory storage, described second level arbitration modules comprises fixed priority arbitration modules, request of access priority look-up table unit, submits judge module in advance to; Described fixed priority arbitration modules is used for the request of access of the request of access bag current first order arbitration modules being sent by queried access Request Priority look-up table unit and carries out priority arbitration, and request of access the highest priority is sent to request of access parsing module; Described request of access priority look-up table unit is for queried access request implicit precedence level; Described pre-submission judge module is for the pre-submission of access control request, if request of access for writing, direct gating, request of access enters next stage; If request of access, for reading, is counted M-X to it, wherein M is that current ongoing reading and writing data is accessed required periodicity, and X is the minimum delay of access based on SDRAM structure external memory.
In order further to realize goal of the invention, the invention also discloses a kind of access method, comprise the following steps: (1) is if request of access input interface unit has detected n request of access, if n=1, forward step (4) to, otherwise request of access subpackage is between two formed request of access bag by first order arbitration modules, and to the request of access priority that is responsible for assigning; (2) the request of access bag of limit priority is sent to second level arbitration modules by first order arbitration modules, carries out priority modification simultaneously; Request of access higher priority is committed to request of access parsing module by second level arbitration modules; (3) if also have untreated request of access to continue to analyze this request of access in request of access bag; Judge request of access type, if read, wait for M-X clock period, wherein M is the remaining periodicity of current accessed, X is the minimum delay periodicity of access based on SDRAM structure external memory, otherwise waits for M clock period, and wherein M is the remaining periodicity of current accessed; (4) current accessed request is committed to request of access parsing module, and judges whether request of access is all disposed, and finishes if be disposed, otherwise get back to step (2).
The present invention compared with prior art, not only can eliminate the inherent delay existing when external memory storage is conducted interviews as far as possible, improve the efficiency of coarseness reconfigurable system computing array access external memory, also the system congestion having caused because access right is serious uneven while having avoided multiple computing arrays simultaneously to external memory access, thus optimize the track performance of whole system.
Accompanying drawing explanation
Fig. 1 is external memory access interface structural representation of the present invention;
Fig. 2 is the browsing process schematic diagram of external memory access interface of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
As shown in Figure 1, restructural computing unit is connected with the chip external memory of SDRAM by external reference interface of the present invention; Restructural computing unit has comprised several reconfigureable computing arrays.External memory access interface of the present invention comprises request of access input interface, the first arbitration modules, the second arbitration modules, controls permission information output interface, request of access parsing module and request of access output interface, restructural computing unit is connected with external reference interface by request of access input interface, and the request of access of restructural computing unit is sent to first order arbitration modules by request of access input interface.First order arbitration modules comprises request of access subpackage module, rotation priority arbitration module and request of access packet priority steering logic, the request of access that request of access subpackage module is sent request of access input interface is packaged into request of access bag between two, if the number of request of access be odd number a remaining request of access become separately bag, request of access packet priority steering logic is for random request of access of the giving request of access subpackage module structure priority that is responsible for assigning; Rotation priority arbitration module sends to second level arbitration modules by request of access bag the highest priority and allows request of access packet priority steering logic again to the request of access priority that is responsible for assigning.Second level arbitration modules comprises fixed priority arbitration modules, request of access priority look-up table unit, the pre-judge module of submitting to, the request of access in the request of access bag that fixed priority arbitration modules is sent first order arbitration modules is carried out priority arbitration and request of access the highest priority is sent to request of access parsing module; The pre-pre-submission of submitting to judge module to be used for access control request, if request of access is for writing, counts M to it; If request of access, for reading, is counted M-X to it, wherein M is that current ongoing reading and writing data is accessed required periodicity, and X is the minimum delay of access based on SDRAM structure external memory.
Be illustrated in figure 2 the workflow diagram of external memory access interface of the present invention, first judged whether request of access, if there is request of access, if the quantity of request of access only has 1, request of access is committed to request of access parsing module, otherwise n request of access is sent to first order arbitration modules and is packaged between two request of access bag, if being even number, request of access bag is divided at random n/2 request of access bag, otherwise be divided at random (n+1)/2 request of access bag, wherein 1 request of access bag only has a request of access, then packed request of access bag being entered to row stochastic priority distributes, then choose the request of access bag that priority is the highest and be sent to second level arbitration modules and replacement request of access packet priority, second level arbitration modules is carried out quantity detection to the request of access bag sending, if 1 request of access is directly committed to request of access parsing module, otherwise request of access high priority is committed to request of access parsing module and analyzes the read-write type that remains request of access, if request of access type is waited for M-X clock period for reading, wherein M is the remaining periodicity of current accessed, X is the minimum delay periodicity of access based on SDRAM structure external memory, otherwise wait for M clock period, wherein M is the remaining periodicity of current accessed.
Below in conjunction with embodiment, the present invention is further described.
The present embodiment is to the H.264 decoding of agreement high-definition digital video, adopts following system: the restructural computing unit that comprises 8 reconfigurable arrays, the chip external memory based on SDRAM and external memory access interface of the present invention; Wherein, each reconfigurable arrays all contains 8 × 8 restructural basic calculating unit and monocyclic 16 arithmetical operations and logical operation can be supported in each restructural basic calculating unit; Chip external memory based on SDRAM has been selected embedded external memory storage DDR SDRAM, supports the data access bit wide of 64bit, and once the required minimum delay of new read access is 6 cycles.In this system-based, after external memory access interface of the present invention and legacy interface are tested, experimental result shows, periodicity that macro block consumes of average every decoding, while adopting legacy interface, it was 1533 cycles, while adopting external memory access interface of the present invention, be 1147 cycles, the access speed of external memory has been promoted to 25.1%, visible external memory access efficiency has improved more than 1.25 times.
More than describe the preferred embodiment of the present invention in detail; but the present invention is not limited to the detail in above-mentioned embodiment, within the scope of technical conceive of the present invention; can carry out multiple equivalents to technical scheme of the present invention, these equivalents all belong to protection scope of the present invention.
It should be noted that in addition each the concrete technical characterictic described in above-mentioned embodiment, in reconcilable situation, can combine by any suitable mode.For fear of unnecessary repetition, the present invention is to the explanation no longer separately of various possible array modes.
Claims (4)
1. for an external memory access interface for coarseness reconfigurable system, it comprises:
Request of access input interface unit, for receiving the external memory request of access of described coarseness reconfigurable system;
First order arbitration modules for the described external memory request of access subpackage between two of described request of access input interface unit is formed to request of access bag, and is described each request of access priority that is responsible for assigning;
Second level arbitration modules, for arbitrating two input requests in described request of access bag, and controls reading in advance of described input request;
Control and allow signal output interface unit, allow signal for exporting to control;
Request of access parsing module, for resolving request of access;
Request of access output interface unit, for exporting described parsing request of access.
2. a kind of external memory access interface for coarseness reconfigurable system as claimed in claim 1, wherein, described first order arbitration modules comprises:
Request of access subpackage module, for by the subpackage between two at random of current all request of access, if remain request of access number deficiency, becomes separately bag by remaining one;
Request of access packet priority steering logic unit, for random request of access of the giving request of access subpackage module structure priority that is responsible for assigning, and responds priority modification signal the priority of request of access bag is modified;
Rotation priority arbitration module, for the priority of arbitrating access request bag, sends request of access bag the highest current priority into second level arbitration modules, and returns to priority modification signal to request of access packet priority steering logic unit.
3. a kind of external memory access interface for coarseness reconfigurable system as claimed in claim 1, wherein, described second level arbitration modules comprises:
Fixed priority arbitration modules, the request of access that is used for the request of access bag current first order arbitration modules being sent by queried access Request Priority look-up table unit is carried out priority arbitration, and request of access the highest priority is sent to request of access parsing module;
Request of access priority look-up table unit, for queried access request implicit precedence level;
The pre-judge module of submitting to, for the pre-submission of access control request, if request of access is for writing, direct gating, request of access enters next stage; If request of access, for reading, is counted M-X to it, wherein M is that current ongoing reading and writing data is accessed required periodicity, and X is the minimum delay of access based on SDRAM structure external memory.
4. the access method based on external memory access interface described in claim 1, is characterized in that, comprises the following steps:
(1), if request of access input interface unit has detected n request of access, if n=1 forwards step (4) to, otherwise request of access subpackage is between two formed request of access bag by first order arbitration modules, and to the request of access priority that is responsible for assigning;
(2) the request of access bag of limit priority is sent to second level arbitration modules by first order arbitration modules, carries out priority modification simultaneously; Request of access higher priority is committed to request of access parsing module by second level arbitration modules;
(3) if also have untreated request of access to continue to analyze this request of access in request of access bag; Judge request of access type, if read, wait for M-X clock period, wherein M is the remaining periodicity of current accessed, X is the minimum delay periodicity of access based on SDRAM structure external memory, otherwise waits for M clock period, and wherein M is the remaining periodicity of current accessed;
(4) current accessed request is committed to request of access parsing module, and judges whether request of access is all disposed, and finishes if be disposed, otherwise get back to step (2).
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Application publication date: 20140709 |