CN1952916A - An arbitration device and method for accessing internal storage - Google Patents
An arbitration device and method for accessing internal storage Download PDFInfo
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Abstract
This invention discloses a memory visit and arbitration device, which comprises memory visit and arbitration module, visit and interval control module and memory interface control module. This invention also discloses one memory visit and arbitration method, which comprises the following steps: a, hardware module delivers read or write require with priority information through bus interface; b, according to the priority list, judging whether to permit the require on memory; if yes then for step c; if not then making the bus interface at wait status to step a; c, according to the require processing relative read or write operation.
Description
Technical field
The present invention relates to internal memory control technology field, particularly a kind of internal storage access arbitration device and method.
Background technology
Along with SOC (system on a chip) (System on Chip, SOC) development of chip technology, module integrated on one chips is more and more, these modules comprise central processing unit (CPU), digital signal processor (Digital Signal Processor, DSP), special hardware circuit etc., therefore need the support of high capacity internal memory.
In the process of a hardware module access memory, other hardware module is also wanted access memory, and this situation just is called a plurality of hardware modules internal memory is conducted interviews simultaneously.In this case, must adopt certain method that these access tasks are dispatched, just can make these hardware modules access memory correctly.At present usually the method that adopts is: in a plurality of hardware modules simultaneously under the situation of access memory, these access tasks according to the time sequencing operation of ranking, and are carried out these accessing operations according to this queue sequence successively.
Though this method according to the queue sequence access memory has guaranteed a plurality of hardware modules access memory correctly, treatment effeciency is not high.For example, task A and task B access memory is simultaneously arranged, wherein task B is the hot job with higher priority, requires to finish as early as possible, and task A is non-hot job, and priority is lower.If but task A submits to earlier, ability access memory after then task B must wait task A be finished to the visit of internal memory.
Therefore, the problem that the prior art scheme exists is: can not make very much the task with higher priority in time obtain the access control right of internal memory, may influence the response speed of hardware module, and then cause system effectiveness to reduce.
Summary of the invention
In view of this, the objective of the invention is to, propose a kind of internal storage access arbitration device, can make the timely access memory of the task with higher priority, improve the response speed of hardware module.This device comprises:
The internal storage access arbitration modules is used to receive the read request that has precedence information, judges whether to allow described read request access memory according to described precedence information, and judged result is sent to described bus interface;
The memory interface control module is used for internally depositing into the row access operation according to the read from described bus interface.
Described internal storage access arbitration modules comprises:
2
n-1 comparing unit is divided into the n level, and the 1st grade comparing unit is used to receive the read request of two bus interface modules, and the read request that will have higher priority is sent to the 2nd grade of comparing unit; I level comparing unit is used to receive the read request from two i-1 level comparing units, and the read request that will have higher priority is sent to i+1 level comparing unit, l＜i＜n; N level comparing unit is used to receive the read request from two n-1 level comparing units, and the read request that will have higher priority is sent to the arbitration result generation unit;
The arbitration result generation unit is used for the pairing hardware interface of the read request of being received is generated the permission interrogation signal, generates the disable access signal for other bus interface of sending the read request.
Preferably, this device comprises that further visit interrupts control module, be used for when receiving that the judged result from the internal storage access arbitration modules is when allowing visit, priority and current internal storage state according to described bus interface, judge whether to interrupt current accessing operation, and interrupt signal to the transmission of internal memory interface control module according to judged result to internal memory;
Then described memory interface control module is further used for interrupting current accessing operation to internal memory according to the described signal that interrupts.
Preferably, this device further comprises:
The priority control module, be used for memory priority level table, reception is dynamically adjusted the priority list of being stored, and adjusted priority list is sent to the internal storage access arbitration modules from the arbitration result of internal storage access arbitration modules and from the read request of each bus interface;
Then described internal storage access arbitration modules judges whether to allow described read request access memory to be according to described precedence information: inquire about described priority list according to described precedence information, judge whether to allow described read request access memory according to Query Result.
Described priority control module further comprises waiting timer, is used to set the wait duration that arbitration result is the read request of disable access;
Then described priority control module is used for when the arbitration result of receiving the read request is disable access, starts and the corresponding waiting timer of described read request, when the overtime priority that then improves described read request of described waiting timer.
The duration of described waiting timer is decided according to the priority of described read request, and the high more then duration of priority is short more.
Save as synchronous dynamic random internal memory SDRAM in described.
The present invention also aims to, propose a kind of one memory visit and arbitration method, can make the timely access memory of the task with higher priority, improve the response speed of hardware module.This method comprises the steps:
A, hardware module are submitted the read request that has precedence information to by bus interface;
B, according to described precedence information and priority list, judge whether to allow described read request access memory, if execution in step C otherwise makes described bus interface be in waiting status and goes to steps A;
C, according to described read request internally deposit into the row corresponding read/write operation.
Further comprise after the described judgement of step B:, described priority list is dynamically adjusted according to the read request and/or the described judged result of each hardware module.
Described priority list is dynamically adjusted comprises:
If described read request and current accessing operation to internal memory are in memory address with in the delegation, then improve the priority of described read request;
Perhaps, if described read request does not obtain access rights in waiting for duration, then improve the priority of described read request.
Before the described C, further comprise: according to the precedence information and the internal storage state of described bus interface, judge whether to allow described read request to interrupt current read operation to internal memory, if then interrupt current read operation to internal memory, and execution in step C; Otherwise direct execution in step C.
As can be seen from the above technical solutions, make request of access have precedence information to internal memory, the order of each request of access that decision is submitted to simultaneously according to priority, and the request of access of high priority can interrupt current just at the accessing operation of the low priority of access memory where necessary, thereby make the request of access of high priority in time meet with a response, can improve the response speed of hardware module.And the present invention program's control circuit is simple, the dirigibility height.
Description of drawings
Fig. 1 is an embodiment of the invention internal storage access arbitration device synoptic diagram;
Fig. 2 is an embodiment of the invention internal storage access arbitration modules internal logic structure synoptic diagram;
Fig. 3 is an embodiment of the invention processing flow chart.
Embodiment
The present invention proposes to carry out according to priority the internal memory referee method of task queue, realizes internally depositing into row accessing operation in time.Below save as the synchronous dynamic random internal memory (Synchronous Dynamicrandom access memory SDRAM) be example, and the present invention program is elaborated with interior.
In the solution of the present invention, corresponding certain other priority of level of the memory access request that internally deposits into row access that hardware module is sent, the different memory access request that internally deposit into row access are simultaneously determined the sequencing of visit according to its corresponding priority level; Under certain condition, the request of access with higher priority can be interrupted the request of access of current lower priority and the preferential access right that obtains internal memory.
The structure of apparatus of the present invention as shown in Figure 1, wherein, bus interface module is the read/write channel of hardware module and the interface between the SDRAM, different hardware modules has corresponding bus interface module.Bus interface is supported the bus protocol of access sdram, and the read/write actions of hardware module is resolved to request of access and the read that SDRAM can support.Specifically, at first bus interface module sends read to internal memory access arbitration device, if described internal storage access arbitration device returns the permission interrogation signal, then send read, and realize corresponding read/write operation SDRAM to described internal storage access arbitration device; If described internal storage access arbitration device returns the disable access signal, then described bus interface module enters waiting status, up to receiving the permission interrogation signal.
Described internal storage access arbitration device comprises as lower module:
Specifically, this module can be stored a static priority table, provides the visit order of the request of access of different priorities in the described static priority table.This module can also be according to each bus interface module current time and next request constantly and the arbitration result of each moment internal storage access arbitration modules, on the basis of described static priority table, dynamically adjust priority list according to certain algorithm, and described adjusted priority list is sent to internal storage access arbitration modules 102.
Described dynamic adjustment priority list can comprise following mode:
A, raising reference address and current accessed are in the priority of SDRAM address with the request of access in the delegation.If in general the address, can not need to go to close and pre-charge process with the visit in the delegation at SDRAM.Therefore can improve access bandwidth to SDRAM.Therefore when the visit of the module that does not press for access rights arrives, can improve the path access privileges that links to each other with the address of current read operation.
B, if request of access can not get response in the default time, then improve the priority of this request of access.Specifically, in the priority control module 101 waiting timer is set, if receive that the arbitration result of read request is a disable access, then start and the corresponding waiting timer of described read request, judge whether described waiting timer receives the arbitration result to permission visit that should the read request before overtime, if then stop described waiting timer, otherwise the priority of described read request is improved one-level and restarts described waiting timer.Corresponding to each priority, the duration of described waiting timer can be all inequality, and the duration of the high more then waiting timer of priority is short more.
Internal storage access arbitration modules 102, be used for according to priority list from priority control module 101, to the arbitration that conducts interviews of the read of the bus interface of hardware module, judge whether to allow this read to conduct interviews, and arbitration result is sent to priority control module 101 and the bus interface of sending described read respectively.Described arbitration result comprises: allow visit or disable access.If arbitration result for allowing visit, then also will be sent to this arbitration result visit and interrupt control module 103.Fig. 1 for simplicity, the bus interface of only drawing, in fact, each hardware module has with it corresponding bus interface respectively.
After if the read request of described bus interface has been allowed to visit, this bus interface is sent a read request constantly again at next, then to be defaulted as also be to allow visit in this read request, therefore can save arbitration operation to this read request, and bus interface directly sends to priority control module 101 with this read request, because the address of this read request is in the same delegation of SDRAM usually with the address of a last read request that is allowed to visit, therefore priority control module 101 can dynamically be adjusted priority list according to aforesaid way a, and hardware module sends read to internal memory interface control module 104 simultaneously.
Internal storage access arbitration modules 102 must be used the short as far as possible time to produce arbitration result, otherwise can't support the demand of high-speed bus when the multichannel request arrive, and in general realizes design with the simplest combinational logic.This module can adopt multilevel logic relatively, selects a higher comparison that participation is follow-up of priority in per 2 read requests, and n-level logic can compare 2
nThe read request on road.
Fig. 2 is the internal storage access arbitration modules synoptic diagram with the read request arbitration of 3 grades of logic realization 8 tunnel bus interface, and the annexation of other module in internal storage access arbitration modules and the internal storage access arbitration device is not shown among Fig. 2.As shown in Figure 2, the internal storage access arbitration modules comprises that 7 comparing units fall into three classes, the first order has 4 comparing units, be respectively applied for the read request that receives two bus interface, compare the priority of these two read requests, the read request that will have higher priority exports partial comparing unit to; The second level comprises two comparing units, be respectively applied for two the read requests of reception from first order comparing unit, compare the priority of two read requests that received, the read request that will have higher priority exports the comparing unit of the third level to; The third level comprises a comparing unit, be used to receive two read requests from second level comparing unit, compare the priority of two read requests that received, the read request that will have higher priority exports the arbitration result generation unit to; The arbitration result that the arbitration result generation unit returns for the pairing bus interface of being received of read request is visited for allowing, and the arbitration result of returning for other bus interface is disable access.In the example shown in Figure 2, numeral on the arrow of each comparing unit output is the sequence number of the bus interface of permission visit, the sequence number of third level comparing unit output is 1, and then the arbitration result generation unit returns to bus interface 1 and allows visit, all returns disable access to other bus interface.
Visit interrupts control module 103, be used for when the permission interrogation signal received from internal storage access arbitration modules 102, according to the status signal of described bus interface and the Access status of current SDRAM, judge whether to interrupt current access control operation, interrupt signal if then send to internal memory interface control module 104 to SDRAM.
Memory interface control module 104 is used to receive the read from bus interface, and SDRAM is carried out corresponding read/write operation.If receive the signal that interrupts that interrupts control module 103 from visit, then before carrying out described read/write operation, end current other accessing operation to SDRAM.
The flow process of the embodiment of the invention comprises the steps: as shown in Figure 3
Step 301: hardware module submits to requirement to carry out the read request that SDRAM is visited by bus interface to internal memory access arbitration module, and described read request has precedence information and reference address.
Step 302: the internal storage access arbitration modules is according to the precedence information and the priority list of the read request of being received, judge whether to allow described read request access sdram, if then to bus interface, visit interrupts control module and the priority control module is returned the permission interrogation signal, and carries out subsequent step; Otherwise return the disable access signal to bus interface and priority control module, bus interface receives that the disable access signal then is in waiting status, and goes to step 301.In the present embodiment, arbitration result is for allowing visit.
Step 303: two sub-steps that comprise executed in parallel:
Whether the address of judging the read of the reference address of described read request and current accessed SDRAM is in the same delegation of SDRAM address, if then increase the priority of described read request;
Perhaps, after described bus interface is submitted the read request to, in the default time, do not obtain visit and allow power, then improve the priority of this read request.Specifically, if receive that the arbitration result of read request is a disable access, then start and the corresponding waiting timer of described read request, judge whether described waiting timer receives the arbitration result to permission visit that should the read request before overtime, if then stop described waiting timer, otherwise the priority of described read request is improved one-level and restarts described waiting timer.The duration of described waiting timer is decided according to the priority of described read request, and the high more then duration of priority is short more.
Step 304: after bus interface is received the arbitration result that allows visit, send read to the internal memory interface control module;
Step 305: the memory interface control module is received look-at-me, then interrupts the accessing operation of current SDRAM, and according to the read of being received SDRAM is carried out corresponding read/write operation.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1, a kind of internal storage access arbitration device is characterized in that, this device comprises:
The internal storage access arbitration modules is used to receive the read request that has precedence information, judges whether to allow described read request access memory according to described precedence information, and judged result is sent to described bus interface;
The memory interface control module is used for internally depositing into the row access operation according to the read from described bus interface.
2, device according to claim 1 is characterized in that, described internal storage access arbitration modules comprises:
2
n-1 comparing unit is divided into the n level, and the 1st grade comparing unit is used to receive the read request of two bus interface modules, and the read request that will have higher priority is sent to the 2nd grade of comparing unit; I level comparing unit is used to receive the read request from two i-1 level comparing units, and the read request that will have higher priority is sent to i+1 level comparing unit, 1＜i＜n; N level comparing unit is used to receive the read request from two n-1 level comparing units, and the read request that will have higher priority is sent to the arbitration result generation unit;
The arbitration result generation unit is used for the pairing hardware interface of the read request of being received is generated the permission interrogation signal, generates the disable access signal for other bus interface of sending the read request.
3, device according to claim 1, it is characterized in that, this device comprises that further visit interrupts control module, be used for when receiving that the judged result from the internal storage access arbitration modules is when allowing visit, priority and current internal storage state according to described bus interface, judge whether to interrupt current accessing operation, and interrupt signal to the transmission of internal memory interface control module according to judged result to internal memory;
Then described memory interface control module is further used for interrupting current accessing operation to internal memory according to the described signal that interrupts.
4, device according to claim 1 is characterized in that, this device further comprises:
The priority control module, be used for memory priority level table, reception is dynamically adjusted the priority list of being stored, and adjusted priority list is sent to the internal storage access arbitration modules from the arbitration result of internal storage access arbitration modules and from the read request of each bus interface;
Then described internal storage access arbitration modules judges whether to allow described read request access memory to be according to described precedence information: inquire about described priority list according to described precedence information, judge whether to allow described read request access memory according to Query Result.
5, device according to claim 4 is characterized in that, described priority control module further comprises waiting timer, is used to set the wait duration that arbitration result is the read request of disable access;
Then described priority control module is used for when the arbitration result of receiving the read request is disable access, starts and the corresponding waiting timer of described read request, when the overtime priority that then improves described read request of described waiting timer.
6, device according to claim 5 is characterized in that, the duration of described waiting timer is decided according to the priority of described read request, and the high more then duration of priority is short more.
7, according to each described device of claim 1 to 6, it is characterized in that, save as synchronous dynamic random internal memory SDRAM in described.
8, a kind of one memory visit and arbitration method is characterized in that, comprises the steps:
A, hardware module are submitted the read request that has precedence information to by bus interface;
B, according to described precedence information and priority list, judge whether to allow described read request access memory, if execution in step C otherwise makes described bus interface be in waiting status and goes to steps A;
C, according to described read request internally deposit into the row corresponding read/write operation.
9, method according to claim 8 is characterized in that, further comprises after the described judgement of step B: according to the read request and/or the described judged result of each hardware module, described priority list is dynamically adjusted.
10, method according to claim 9 is characterized in that, described priority list is dynamically adjusted comprises:
If described read request and current accessing operation to internal memory are in memory address with in the delegation, then improve the priority of described read request;
Perhaps, if described read request does not obtain access rights in waiting for duration, then improve the priority of described read request.
11, according to Claim 89 or 10 described methods,, it is characterized in that, before the described C, further comprise: according to the precedence information and the internal storage state of described bus interface, judge whether to allow described read request to interrupt current read operation to internal memory, if then interrupt current read operation, and execution in step C to internal memory; Otherwise direct execution in step C.
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| CN102184139A (en) * | 2010-06-22 | 2011-09-14 | 上海盈方微电子有限公司 | Method and system for managing hardware dynamic memory pool |
| CN102323913A (en) * | 2011-09-01 | 2012-01-18 | 记忆科技(深圳)有限公司 | Data readout method and system for solid state disk |
| CN102331977A (en) * | 2011-09-07 | 2012-01-25 | 上海交通大学 | Memory controller, processor system and memory access control method |
| CN102402422A (en) * | 2010-09-10 | 2012-04-04 | 北京中星微电子有限公司 | Processor component and memory sharing method thereof |
| CN103309841A (en) * | 2012-03-16 | 2013-09-18 | 英飞凌科技股份有限公司 | Method and system for timeout monitoring |
| CN103914413A (en) * | 2014-04-18 | 2014-07-09 | 东南大学 | External-storage access interface for coarseness reconfigurable system and access method of external-storage access interface |
| CN105718394A (en) * | 2016-01-25 | 2016-06-29 | 东南大学 | On-chip cache memory access interface of coarse-grained reconfigurable system and access method thereof |
| CN109144898A (en) * | 2017-06-19 | 2019-01-04 | 深圳市中兴微电子技术有限公司 | A kind of Installed System Memory managing device and Installed System Memory management method |
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Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4400771A (en) * | 1975-12-04 | 1983-08-23 | Tokyo Shibaura Electric Co., Ltd. | Multi-processor system with programmable memory-access priority control |
| US20050144401A1 (en) * | 2003-12-30 | 2005-06-30 | Pantalone Brett A. | Multiprocessor mobile terminal with shared memory arbitration |
| CN100345128C (en) * | 2004-02-25 | 2007-10-24 | 中国科学院计算技术研究所 | Bus arbiter based on dynamic priority and method for dynamic changing priority |
| CN1770125A (en) * | 2004-11-04 | 2006-05-10 | 华为技术有限公司 | Memory allocation method |
-
2006
- 2006-11-28 CN CNB200610145941XA patent/CN100444143C/en not_active Expired - Fee Related
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| CN102184139A (en) * | 2010-06-22 | 2011-09-14 | 上海盈方微电子有限公司 | Method and system for managing hardware dynamic memory pool |
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| CN102402422B (en) * | 2010-09-10 | 2016-04-13 | 北京中星微电子有限公司 | The method that processor module and this assembly internal memory are shared |
| CN102323913A (en) * | 2011-09-01 | 2012-01-18 | 记忆科技(深圳)有限公司 | Data readout method and system for solid state disk |
| CN102323913B (en) * | 2011-09-01 | 2014-08-20 | 记忆科技(深圳)有限公司 | Data readout method and system for solid state disk |
| CN102331977A (en) * | 2011-09-07 | 2012-01-25 | 上海交通大学 | Memory controller, processor system and memory access control method |
| US10191795B2 (en) | 2012-03-16 | 2019-01-29 | Infineon Technologies Ag | Method and system for timeout monitoring |
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| CN115659379A (en) * | 2022-12-15 | 2023-01-31 | 芯动微电子科技(珠海)有限公司 | Bus access authority control method and device |
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