CN102402422B - The method that processor module and this assembly internal memory are shared - Google Patents
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Abstract
The invention provides a kind of processor module, comprise internal memory, coprocessor assembly and application processor assembly, this internal memory comprises coprocessor component accesses district, application processor component accesses district and shared region; This coprocessor assembly comprises coprocessor, sends the read/write access request with prioritization of access information; First internal memory moderator, receives the request of access that coprocessor sends; This application processor assembly comprises coprocessor control device, receives the request of access that the first internal memory moderator sends; Application processor, sends the read/write access request with prioritization of access information; Second internal memory moderator, receive the request of access of association's processing controller or application processor transmission, and according to priority grade sorts to request of access; Memory Controller Hub, receives the request of access that the second internal memory moderator sends, and conducts interviews to the respective regions of internal memory.A kind of method that the present invention also provides processor module internal memory to share.
Description
Technical field
The present invention relates to processor, particularly relate to the method that the structure of application processor in embedded system and coprocessor and internal memory are shared.
Background technology
Along with the development of computer microprocessor and network technology, the function of embedded system is powerful gradually, and range of application is also more and more extensive.In embedded systems, more additional function is all exist with the form of the peripheral circuit of processor, therefore needs a large amount of discrete components, and need all kinds of input and output expansions, processor also needs to increase the structures such as interface accordingly, and structure is comparatively complicated, is not easy to realize.
The appearance of coprocessor solves this problem, but, under normal circumstances, in embedded systems, coprocessor and application processor are all provided with each self-corresponding Memory Controller Hub and internal memory, the Memory Controller Hub that coprocessor is corresponding controls the exchanges data between coprocessor and internal memory, and the Memory control that application processor is corresponding controls the exchanges data between application processor and internal memory, and the communication between two processors is then selected by selector switch.Therefore, in this kind of embedded system, need to arrange selector switch between.Because the internal memory corresponding to two processors is separate, be not easy to the exchanging visit between two processors.In addition, because the usual required internal memory of coprocessor is less, if separately for coprocessor configures an internal memory, it often can't take all told of this internal memory in use, so just can cause the waste that internal memory uses, and is unfavorable for reducing cost.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of method that in processor module and this assembly, internal memory is shared, and can realize application processor and assist the internal memory between processing to share, reduce costs.
In order to solve the problem, the invention discloses a kind of processor module, comprise internal memory, coprocessor assembly and application processor assembly, this internal memory comprises coprocessor component accesses district, application processor component accesses district and shared region; This coprocessor assembly comprises coprocessor, sends the read/write access request with prioritization of access information; First internal memory moderator, receives the read/write access request with prioritization of access information that coprocessor sends; This application processor assembly comprises coprocessor control device, receives the read/write access request with prioritization of access information that the first internal memory moderator sends; Application processor, sends the read/write access request with prioritization of access information; Second internal memory moderator, receive the read/write access request with prioritization of access information of association's processing controller or application processor transmission, and according to priority grade sorts to request of access; Memory Controller Hub, receive the request of access that the second internal memory moderator sends, and the respective regions of access control request to internal memory conducts interviews.
Further, this coprocessor assembly also comprises at least one controller, sends the read/write access request with prioritization of access information to the first internal memory moderator.
Further, this application processor assembly also comprises at least one controller, sends the read/write access request with prioritization of access information to the second internal memory moderator.
Further, in this first internal memory moderator, there is priority control module, priority list and signal generation unit is previously stored with in described priority control module, priority list sorts to it according to information such as the request time of the read/write access request received and priority levels, the read/write access request with highest priority level is generated interrogation signal by signal generation unit, and other read/write access request generates disable access signal.
Further, in this second internal memory moderator, there is priority control module, priority list and signal generation unit is stored in described priority control module, priority list sorts to it according to information such as the request time of the read/write access request received and priority levels, the read/write access request with highest priority level is generated interrogation signal by signal generation unit, and other read/write access request generates disable access signal.
The method that the present invention also provides the internal memory of above-mentioned processor module to share, comprise A. and deposit into row subregion to interior, internal memory is divided into the application processor component accesses district for application processor access, the coprocessor access region for coprocessor component accesses and the two all addressable shared region; B. coprocessor sends with the read/write access request of prioritization of access information to the first internal memory moderator, first internal memory moderator sends to coprocessor control device after the read/write access request received being sorted according to priority level, the read/write access request received is sent to the second internal memory moderator by coprocessor control device again, and application processor sends the read/write access request with prioritization of access information to the second internal memory moderator; C. the second internal memory moderator sends received read/write access request to Memory Controller Hub successively according to priority level; D. Memory Controller Hub to received read/write access request carry out analyze and the respective regions of access control request to internal memory conduct interviews.
Further, also comprising at least one controller in this step B sends with the read/write access request of prioritization of access information to the first internal memory moderator, if the read/write access request not having other devices to send in the first internal memory moderator, then this read/write access request is directly sent to coprocessor moderator by the first internal memory moderator, if also have the read/write access request that other devices send in the first internal memory moderator, then the first internal memory moderator sorts according to priority level to wherein all read/write access requests according to priority level, and send to coprocessor control device, the read/write access request received is sent to the second internal memory moderator by association's processing controller again.
Further, also comprising at least one controller in this step B sends with the read/write access request of prioritization of access information to the second internal memory moderator, if the read/write access request not having other devices to send in the second internal memory moderator, then this read/write access request is directly sent to Memory Controller Hub by the second internal memory moderator; If also have the read/write access request that other devices send in the second internal memory moderator, then the second internal memory moderator sorts according to priority level to wherein all read/write access requests.
Further, also comprise in this step B: the first internal memory moderator and the second internal memory moderator are according to information such as the request time of read/write access request and priority levels, with reference to the priority level table prestored, request of access is sorted, determine the read/write access request with limit priority, and the read/write access request with limit priority is generated interrogation signal, other read/write access request generates disable access signal, is in waiting status.
Further, also comprise in this D step: the visit information of Memory Controller Hub to the read/write access request received judges, if visit information mistake, then stops the access to internal memory; If visit information is correct, then allow this request of access to the access of internal memory respective regions.
Compared with prior art, the present invention has the following advantages:
By internally depositing into row subregion, internal memory is divided into the application processor access region for application processor component accesses, the coprocessor access region for coprocessor component accesses and the two all addressable shared region.Because the internal memory shared by coprocessor assembly is general less, therefore only need the wherein sub-fraction capacity being originally used for the internal memory of application processor assembly to be divided into coprocessor access region and shared region, just can meet the demand of coprocessor assembly to internal memory.Simultaneously, coprocessor control device is set in application processor assembly, request of access in coprocessor assembly internally to be deposited via the second internal memory moderator and Memory Controller Hub by coprocessor control device conduct interviews, therefore, an internal memory just can meet the requirements for access of coprocessor assembly and application processor assembly simultaneously, without the need to respectively arranging an independent memory for coprocessor assembly and application processor assembly, save the quantity of internal memory, reduce cost, and decrease the space taken on multi circuit board because arranging multiple internal memory.Meanwhile, the priority list in the second internal memory moderator, can ensure to assist the request of access of processing components to have higher priority level, therefore, the request of access of coprocessor assembly can be processed in time, improves the response speed of corresponding hardware.In addition, the two shares an internal memory, when needing to carry out data interaction therebetween, wherein a side can directly by the shared region of this data write memory, and the opposing party directly reads this data from shared region, without the need to being transferred by intermediate link, the exchanging visit of the two is convenient, improves access efficiency.
Accompanying drawing explanation
Fig. 1 is the structural representation of the processor module of the embodiment of the present invention.
Fig. 2 is the process flow diagram of the processor module internal memory sharing method of the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Refer to Fig. 1, a kind of processor module 100, comprise internal memory 10, association's processing components 30 and application processor assembly 50.
Internal memory 10 comprises the coprocessor component accesses district accessed for coprocessor assembly 30, the application processor component accesses district supplying application processor assembly 50 to access and the two all addressable shared region.
Coprocessor assembly 30 comprises the controller 35 of the first internal memory moderator 31, coprocessor 33 and direct access internal memory.Coprocessor 33 and controller 35 send the read/write access request with prioritization of access information to the first internal memory moderator 31.First internal memory moderator 31 has priority control module, be stored with priority list, first internal memory moderator 31 can according to the information such as request time and priority level of the read/write access request from coprocessor 33 and controller 35 received, and the grade first set according to priority list sorts to request of access.First internal memory moderator 31 also comprises signal generation unit, the information of the request of access after sequence is sent to signal generation unit by priority control module, the request of access with highest ranking can be generated interrogation signal by signal generation unit, request of access for other then generates disable access signal, be in waiting status, wait for lower minor sort.The quantity of controller 35 can be one, two or more, and its quantity is determined according to the quantity of the actual external devices connected of process.
Application processor assembly 50 comprises the controller 59 of coprocessor control device 51, application processor 53, second internal memory moderator 55, Memory Controller Hub 57 and direct access internal memory.Coprocessor control device 51 is for receiving the read/write access request with prioritization of access information of the first internal memory moderator 31 transmission and sending request of access to second internal memory moderator 55.Application processor 53 and controller 59 send the read/write access request with prioritization of access information to the second internal memory moderator 55.Second internal memory moderator 55 has priority control module, be stored with priority list, second internal memory moderator 55 can according to information such as the request time of the read/write access request from coprocessor control device 51, application processor 53 and controller 59 received and priority levels, and the grade first set according to priority list sorts to request of access.Second internal memory moderator 55 also comprises signal generation unit, the information of the request of access after sequence is sent to signal generation unit by priority control module, the request of access with highest ranking can be generated interrogation signal by signal generation unit, request of access for other then generates disable access signal, be in waiting status, wait for lower minor sort.The quantity of controller 59 can be one, two or more, and its quantity is determined according to the quantity of the actual external devices connected of process.
Please refer to Fig. 2, the internal memory sharing method of this processor module 100, comprises the following steps:
S101, carries out subregion to internal memory 10, internal memory 10 is divided into the application processor access region accessed for application processor assembly 50, the coprocessor access region supplying coprocessor assembly 30 to access and the two all addressable shared region.
S102, controller 35 or coprocessor 33 send the read/write access request with prioritization of access information to the first internal memory moderator 31.First first internal memory moderator 31 judges whether there is the request of multichannel read/write access simultaneously, if only have a road, then sends this read/write access request directly to coprocessor control device 51; If have multichannel simultaneously, priority list then by presetting sorts to the request of multichannel read/write access, and send association's processing controller 51 to after the request of access after sequence with highest priority level being generated interrogation signal by signal generation unit, remaining then generates disable access signal, waits for that previous interrogation signal sorts after exporting again.Coprocessor control device 51, application processor 53 or controller 59 are all that read/write access request is sent to the second internal memory moderator 55.Second internal memory moderator 55 first also can judge whether there is the request of multichannel read/write access simultaneously, if only have a road, then sends this read/write access request directly to Memory Controller Hub 57; If have multichannel simultaneously, priority list then by presetting sorts to this multichannel read/write access request, and send Memory Controller Hub to after the request of access after sequence with highest priority level being generated interrogation signal by signal generation unit, remaining then generates disable access signal, waits for that last visit sorts after terminating again.
S103, the second internal memory moderator 55 sends the read/write access request after sequence to Memory Controller Hub successively according to priority level.
S104, Memory Controller Hub 57 carries out analyzing to received read/write access request and access control request conducts interviews to the respective regions in internal memory 10.Such as, from the request of access of coprocessor 33, the application processor access region in request access internal memory 10, then Memory Controller Hub 57 can judge this access request error, refusal this visit.If from the request of access of coprocessor 33, the coprocessor access region in request access internal memory 10, then can judge that this visit request is correct, allow this visit.
Because under normal circumstances, the priority of the read/write access request of coprocessor assembly 30 can higher than the read/write access request of application processor assembly 50, and the request of access for coprocessor assembly 30 generally takes the mode with arriving with access.Therefore in the method that the processor module 100 in the embodiment of the present invention and this processor module internal memory are shared, in the priority list arranged in the second internal memory moderator 55, the priority of the request of access of coprocessor assembly 30 can higher than the request of access of application processor assembly 50.When both request of access arrive the second internal memory moderator 55 simultaneously, the request of access of coprocessor assembly 30 can preferentially conduct interviews.If when the request of access of coprocessor assembly 30 arrives the second internal memory moderator 55, the request of access of existing application processor assembly 50 is bide one's time waiting above, now the second internal memory moderator 55 to the rearrangement of all request of access, can enable the request of access priority processing of coprocessor assembly 30.The priority list arranged in second internal memory moderator 55 can ensure carrying out smoothly of this kind of process, thus ensures that the request of access of coprocessor assembly 30 can be processed timely, and system can normally work.
In addition, because the internal memory shared by coprocessor assembly 30 is general all less, by carrying out subregion to the internal memory 10 being originally used for application processor assembly, the wherein sub-fraction capacity of internal memory 10 is divided into coprocessor access region and shared region, just can meets the demand of coprocessor assembly 30 pairs of internal memories.Simultaneously, coprocessor control device 51 is set in application processor assembly 50, request of access in coprocessor assembly 30 is conducted interviews via the second internal memory moderator 55 of application processor assembly 50 and Memory Controller Hub 57 pairs of internal memories 10 by coprocessor control device 51, therefore, an internal memory just can meet the requirements for access of coprocessor assembly 30 and application processor assembly 50 simultaneously, without the need to respectively arranging an internal memory for coprocessor assembly 30 and application processor assembly 50 separately, save the quantity of internal memory, reduce cost, and decrease the space taken on multi circuit board because arranging multiple internal memory.Simultaneously, by the priority level of the request of access of coprocessor assembly 30 being set in the priority list in the second internal memory moderator 55 priority level of the request of access higher than application processor assembly 50, can ensure to assist the request of access of processing components 30 to be processed in time, improve the response speed of corresponding hardware, avoid the problem of the request of access waits for too long caused because of total internal memory.
Further, the shared region that coprocessor assembly 30 and application processor assembly 50 can be accessed simultaneously is provided with in internal memory 10, when needing to carry out data interaction therebetween, wherein a side can directly by the shared region of this data write memory 10, and the opposing party directly reads this data from shared region, and without the need to being transferred by intermediate link, the exchanging visit of the two is convenient, improve access efficiency.This kind of mode can also save the structure such as interchanger for translation data, makes the structure of this processor module 100 more simple, and reduces cost.
Above to the method that a kind of processor module provided by the present invention and this processor module internal memory are shared, be described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a processor module, comprises internal memory, coprocessor assembly and application processor assembly, it is characterized in that,
This internal memory comprises: coprocessor component accesses district, application processor component accesses district and shared region; Save as in described originally for the internal memory of application processor assembly, described internal memory is divided into coprocessor component accesses district, application processor component accesses district and shared region;
This coprocessor assembly comprises:
Coprocessor, sends the read/write access request with prioritization of access information;
First internal memory moderator, receives the read/write access request with prioritization of access information that coprocessor sends;
This application processor assembly comprises:
Coprocessor control device, receives the read/write access request with prioritization of access information that the first internal memory moderator sends;
Application processor, sends the read/write access request with prioritization of access information;
Second internal memory moderator, receive the read/write access request with prioritization of access information of coprocessor control device or application processor transmission, and according to priority grade sorts to request of access;
Memory Controller Hub, receive the request of access that the second internal memory moderator sends, and the respective regions of access control request to internal memory conducts interviews;
Wherein, described coprocessor control device makes the request of access in coprocessor assembly internally deposit via the second internal memory moderator of application processor assembly and Memory Controller Hub by coprocessor control device to conduct interviews;
Meanwhile, by the priority level of the request of access of coprocessor assembly being set in the priority list in the second internal memory moderator the priority level of the request of access higher than application processor assembly.
2. processor module as claimed in claim 1, it is characterized in that, described coprocessor assembly also comprises at least one controller, sends the read/write access request with prioritization of access information to the first internal memory moderator.
3. processor module as claimed in claim 1, it is characterized in that, described application processor assembly also comprises at least one controller, sends the read/write access request with prioritization of access information to the second internal memory moderator.
4. processor module as claimed in claim 1, it is characterized in that, in described first internal memory moderator, there is priority control module, priority list and signal generation unit is previously stored with in described priority control module, priority list sorts to it according to the request time of the read/write access request received and priority level information, the read/write access request with highest priority level is generated interrogation signal by signal generation unit, and other read/write access request generates disable access signal.
5. processor module as claimed in claim 1, it is characterized in that, in described second internal memory moderator, there is priority control module, priority list and signal generation unit is stored in described priority control module, priority list sorts to it according to the request time of the read/write access request received and priority level information, the read/write access request with highest priority level is generated interrogation signal by signal generation unit, and other read/write access request generates disable access signal.
6. the method that processor module internal memory is shared, it is characterized in that, described method comprises:
A. deposit into row subregion to interior, internal memory is divided into the application processor component accesses district for application processor access, the coprocessor access region for coprocessor component accesses and the two all addressable shared region; Save as in described originally for the internal memory of application processor assembly, described internal memory is divided into coprocessor access region, application processor component accesses district and shared region;
B. coprocessor sends with the read/write access request of prioritization of access information to the first internal memory moderator, first internal memory moderator sends to coprocessor control device after the read/write access request received being sorted according to priority level, the read/write access request received is sent to the second internal memory moderator by coprocessor control device again, and application processor sends the read/write access request with prioritization of access information to the second internal memory moderator;
C. the second internal memory moderator sends received read/write access request to Memory Controller Hub successively according to priority level;
D. Memory Controller Hub to received read/write access request carry out analyze and the respective regions of access control request to internal memory conduct interviews;
Wherein, described coprocessor control device makes the request of access in coprocessor assembly internally deposit via the second internal memory moderator of application processor assembly and Memory Controller Hub by coprocessor control device to conduct interviews;
Meanwhile, by the priority level of the request of access of coprocessor assembly being set in the priority list in the second internal memory moderator the priority level of the request of access higher than application processor assembly.
7. method as claimed in claim 6, it is characterized in that, also comprise in described step B: at least one controller sends the read/write access request with prioritization of access information to the first internal memory moderator, if the read/write access request not having other devices to send in the first internal memory moderator, then this read/write access request is directly sent to coprocessor moderator by the first internal memory moderator, if also have the read/write access request that other devices send in the first internal memory moderator, then the first internal memory moderator sorts according to priority level to wherein all read/write access requests according to priority level, and send to coprocessor control device, the read/write access request received is sent to the second internal memory moderator by coprocessor control device again.
8. method as claimed in claim 6, it is characterized in that, also comprise in described step B: at least one controller sends the read/write access request with prioritization of access information to the second internal memory moderator, if the read/write access request not having other devices to send in the second internal memory moderator, then this read/write access request is directly sent to Memory Controller Hub by the second internal memory moderator; If also have the read/write access request that other devices send in the second internal memory moderator, then the second internal memory moderator sorts according to priority level to wherein all read/write access requests.
9. method as claimed in claim 6, it is characterized in that, also comprise in described step B: the first internal memory moderator and the second internal memory moderator are according to the request time of read/write access request and priority level information, with reference to the priority level table prestored, request of access is sorted, determine the read/write access request with limit priority, and the read/write access request with limit priority is generated interrogation signal, other read/write access request generates disable access signal, is in waiting status.
10. method as claimed in claim 6, is characterized in that, also comprise in described D step: the visit information of Memory Controller Hub to the read/write access request received judges, if visit information mistake, then stops the access to internal memory; If visit information is correct, then allow this request of access to the access of internal memory respective regions.
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| US9652270B2 (en) * | 2014-03-21 | 2017-05-16 | Intel Corporation | Apparatus and method for virtualized computing |
| TWI553483B (en) * | 2014-10-13 | 2016-10-11 | 瑞昱半導體股份有限公司 | Processor and method for accessing memory |
| CN105787360B (en) * | 2016-03-02 | 2019-01-04 | 杭州字节信息技术有限公司 | A kind of Implementation Technology of embedded system memory safe access control |
| CN106484531B (en) * | 2016-09-18 | 2019-12-24 | 上海顺久电子科技有限公司 | Memory access arbitration method, circuit and device |
| TW201926147A (en) * | 2017-12-01 | 2019-07-01 | 阿比特電子科技有限公司 | Electronic device, accelerator, accelerating method applicable to neural network computation, and neural network accelerating system |
| CN112100090A (en) * | 2020-09-16 | 2020-12-18 | 浪潮(北京)电子信息产业有限公司 | Data access request processing method, device, medium and memory mapping controller |
| CN113312303B (en) * | 2021-04-30 | 2022-10-21 | 展讯通信（上海）有限公司 | Micro-architecture system of processor, soC chip and low-power-consumption intelligent equipment |
| CN113806244B (en) * | 2021-11-18 | 2022-02-08 | 深圳比特微电子科技有限公司 | Memory management method for system on chip and device based on system on chip |
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