CN100505676C - Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method - Google Patents
Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method Download PDFInfo
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- CN100505676C CN100505676C CNB2006101481625A CN200610148162A CN100505676C CN 100505676 C CN100505676 C CN 100505676C CN B2006101481625 A CNB2006101481625 A CN B2006101481625A CN 200610148162 A CN200610148162 A CN 200610148162A CN 100505676 C CN100505676 C CN 100505676C
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Abstract
Multiple buffer areas are realized by a piece of sharing memory unit in hardware, and managed by unified access arbitrator and allocation table of buffer area in order to provide high performance multiple buffer areas for buffer area access unit. When buffer areas are requested to access, the access arbitrator determines whether there is space allowed to assigning to buffer area requested first based on allocation table; if yes, the access is authorized, and corresponding update is made for the allocation table of buffer area. Buffer area is recovered in real time after its use is ended. The invention raises use ratio of whole memory unit, real time operation and throughput of buffer area.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of centralized dispatching controller of multi buffer management, relate in particular to a kind of dynamic dispatching method of centralized dispatching and performance optimization of intelligent multi buffer management.
Background technology
In traditional data communication system, a plurality of transmissions generally all can be arranged and receive buffering area.Send buffering area in order to temporary data to be sent, on transmitter distributes after data, can be at once obtain data and send, and needn't wait for that data source provides data from sending buffering area, if send buffering area be empty, and then representing does not currently have data to need transmission.Receive the then data that receive of temporal data receiving system of buffering area, memory space fast is provided, often need to compare the longer time of data that receives because take data away, if the data that receive can not in time be kept in, then receiving system can't continue to receive data, will cause the loss with efficiency of transmission of losing of information.
Because in data communication system, data of different types is often arranged alternately, thus generally all need the buffering area of a plurality of transmissions and reception, as in the usb communication model, just can support to be up to 16 and send and receive buffering area, in order to handle the data of different types bag.Typical buffering area control system as shown in Figure 1.
The workflow of typical data buffer system is, in receiving path, receiver (101) is received data from the outside, be deposited in the reception buffering area (103) by data/address bus (102), functional unit (105) is the user of data, it has detected storage in buffering area the time, by data/address bus (104) data is read away from buffering area.In transmission path, data source (110) provides data, writes data by data/address bus (109) to sending buffering area (108), when transmitter (106) has detected data and is written into buffering area, then data are read out from buffering area by data/address bus (107), mail to external equipment.
In this typical data buffering system, we have generally used the buffering area of a plurality of transmissions and reception as we can see from the figure, but when real work, synchronization often has only a transmission or reception buffering area to be used, and other buffer storage unit that is not used will be by idle.This just causes the utilance of memory cell very low, and because the capacity of single buffering area can not be very big under this structure, so the throughput of communication system also is restricted.The number of buffer that in system, exists more for a long time, the throughput of system will seriously be affected.
In present SOC system, the data communication part generally all has a plurality of buffering areas, and typical buffering area scheme can not adapt to the demand of existing system.
Summary of the invention
The object of the present invention is to provide the centralized dispatching controller of the intelligent multi buffer management in a kind of data communication system that is applied to a plurality of buffering areas, and a kind of dynamic dispatching method that multiple buffer is carried out centralized dispatching and its performance is optimized, to improve throughput and the utilization ratio of storage resources in the system communication process, that reduces buffering area can not the response time, guarantee the bandwidth requirement of transfer of data, maximization improves the overall performance of System on Chip/SoC.
The centralized dispatching controller of intelligent multi buffer management provided by the invention comprises:
The shared data of multiple buffer are write incoming interface, are used for switching at a plurality of buffering areas, and the data that receive at the purpose buffering area write request and data;
The shared data of multiple buffer are read interface, are used for switching at a plurality of buffering areas, and acceptance is at the request of reading of the data of purpose buffering area and data output is provided;
The switch control unit of two different buffering area access request is used to select appointed buffer, to carry out data read-write operation;
A plurality of control signal wires that link to each other with memory with each control module cooperate the transmission data that each device communication module is controlled.
Control module and memory in the centralized dispatching controller of intelligent multi buffer management of the present invention are specific as follows:
An access arbitration device can be used for arbitrating the access request to different buffering areas, and whether decision authorizes or denied access.In granted access, check and renewal buffering area allocation table, used later at buffering area and reclaim memory space by the mode of upgrading allocation table;
A buffering area allocation table, the situation that the mode record storage unit of employing chain list index is put each buffering area of dispensing, each buffer blocks is corresponding clauses and subclauses in allocation table, are managed by the access arbitration device;
An address pointer holding unit keeps the initial address of different buffering areas dynamically, when the visit to certain buffering area is authorized to, obtains the first address of this buffering area memory from this unit.
The storage allocation location of a dynamic dispatching buffering area in the time distributing new memory space will for certain buffering area, is checked available memory space address by this unit, and the notice moderator is authorized visit, and upgrades corresponding memory block distribution table;
A memory cell gatherer that dynamically reclaims used buffering area, after the part or all of data of buffering area were read out, this unit upgraded the data that table is distributed in corresponding memory block, and these memory blocks of notice moderator can be reallocated use.
The centralised storage district that shared two passages of support of all buffering areas are visited simultaneously is used to store actual data, and the data organization mode is in strict accordance with the indicated chain structure storage of allocation table;
A kind of dynamic dispatching method that utilizes above-mentioned focal length scheduling controller that multiple buffer is carried out centralized dispatching and its performance is optimized, with the buffering area allocation table serves as to handle core, automatically the scheduling of carrying out the memory block when work distributes and recovery, it is characterized in that, comprises that the following step poly-:
At first access end is initiated the write data requests to certain buffering area;
The access arbitration device is inquired about the situation of current memory block distribution table then, whether determines granted access according to the access privileges of each end points;
The access arbitration device for it distributes new storage address, and upgrades the corresponding buffer region allocation table for the visit of having authorized;
When certain buffering area is read out, the access arbitration device is regained this piece storage area at once, and the corresponding buffer region allocation table is emptied, and uses for other buffering area with slot milling;
Data structure in the buffering area allocation table is the chain structure of multiple-limb, the corresponding chained list of each buffering area;
Because each buffering area is managed by allocation table, therefore the address of single buffering area does not need can separate continuously, as long as the sensing in the allocation table is managed, therefore can utilize storage space to greatest extent.
Original advantage of the present invention is: the centralized dispatching controller of intelligent multi buffer management can be arbitrated the buffering area access request automatically, manage by access arbitration device and the unification of buffering district's distribution table, in order to offer the high performance multiple buffer service of buffering area addressed location, to improve throughput and the utilization ratio of storage resources in the system communication process, that reduces buffering area can not the response time, guarantee the bandwidth requirement of transfer of data, maximization improves the overall performance of System on Chip/SoC.
Description of drawings
Fig. 1 is the system configuration schematic diagram that traditional buffer management cell controller receives path;
Fig. 2 is the system configuration schematic diagram of traditional buffer management cell controller transmission path;
Fig. 3 is the system configuration schematic diagram of the intelligent buffer district administrative unit of this paper;
Fig. 4 is the example of storage allocation table described in Fig. 3.
Fig. 5 is the data transfer mode flow process diagram of centralized dispatching controller of the present invention.
Number in the figure: 101 is receiver, and 102 is connecting bus, and 103 is buffer set, and 104 is connecting bus, 105 is data processing unit, and 106 is data transmission blocks (as USB), and 107 is connecting bus, 108 is buffer set, and 109 is connecting bus, and 110 is DSN.301 are external data reception and transmitting element, 302 are the centralized dispatching controller, 303 is the internal data transmitting element, 401 is the data transmit-receive module write request, and 402 for judging when front space, and whether 403 for judging for this buffering area allocation space, 404 is write operation, 405 is updated stored district allocation table, and whether 406 for having number to can read judgement, and 407 is updated stored district allocation table.
Embodiment
Following with reference to accompanying drawing detailed description the specific embodiment of the present invention.
Fig. 3 is the system construction drawing that other module of centralized dispatching controller and system of intelligent multi buffer management of the present invention is connected, and centralized dispatching controller (302) is as follows with the annexation of each module of system:
Receive and transmitting element (301) with external data: external data receives and transmitting element can send the access request that reads or write to the centralized dispatching controller, can indicate the buffering area that it will be visited by the end points input after the request of external data reception transmitting element is authorized to;
With internal data Transmit-Receive Unit (303): internal data receives and transmitting element can send the access request that reads or write to the centralized dispatching controller, can indicate the buffering area that it will be visited by end points input after the request that internal data receives transmitting element is authorized to;
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises the shared data of a multiple buffer and writes incoming interface, is used for switching at a plurality of buffering areas, and the data that receive at the purpose buffering area write request and data;
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises the shared data of a multiple buffer and reads interface, is used for switching at a plurality of buffering areas, and acceptance is to the request of reading of the data of purpose buffering area and data output is provided;
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises the switch control unit of two different buffering area access request, is used to select appointed buffer, to carry out data read-write operation;
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises a plurality of control signal wires that link to each other with memory with each control module, cooperates the transmission data that each device communication module is controlled.
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises an access arbitration device, is used to arbitrate the access request to different buffering areas, and whether decision authorizes or denied access.In granted access, check and renewal buffering area allocation table, used later at buffering area and reclaim memory space by the mode of upgrading allocation table;
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises and has a buffering area allocation table, the situation that the mode record storage unit of employing chain list index is put each buffering area of dispensing, each buffer blocks is corresponding clauses and subclauses in allocation table, are managed by the access arbitration device;
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises and has an address pointer holding unit, the dynamic initial address that keeps different buffering areas when the visit to certain buffering area is authorized to, obtains the first address of this buffering area memory from this unit.
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises the storage allocation location of a dynamic dispatching buffering area, in the time distributing new memory space will for certain buffering area, check available memory space address by this unit, the notice moderator is authorized visit, and upgrades corresponding memory block distribution table;
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises a memory cell gatherer that dynamically reclaims used buffering area, after the part or all of data of buffering area are read out, this unit upgrades the data that table is distributed in corresponding memory block, and these memory blocks of notice moderator can be reallocated use.
In the present invention, the centralized dispatching controller of intelligent multi buffer management comprises the centralised storage district that shared two passages of support of all buffering areas are visited simultaneously, be used to store actual data, the data organization mode is in strict accordance with the indicated chain structure storage of allocation table;
Fig. 4 is the example that table is distributed in the described memory block of Fig. 3, has indicated a plurality of buffering areas how to be managed by a buffering area allocation table, has indicated the chained list annexation that the present invention uses with illustrated mode.
Fig. 5 is the data transfer mode flow chart of the centralized dispatching controller control of intelligent multi buffer management of the present invention, and the step of its work is as follows:
401: the access arbitration device is received the write request to certain buffering area, and this finishes by control line special between controller and the data transmit-receive unit;
402: controller judges whether the current not usage space of distributing to this end points enough receives the bag of this complete end points maximum packet length, if enough, then authorize normal visit, and it is constant to keep original allocation table entries content.
403:, then judge whether to give this end points to distribute new space if controller finds that the current space of distributing to this end points is once transmitted inadequately or unallocated space still.If the write access contention resource of higher priority is arranged, for maximize throughput, under the situation of inadequate resource, will refuse this time write access, provide the full signal of buffering area.
404: by after arbitration and asking resource, the address of indicating according to the address pointer generation unit begins to carry out write operation to the buffering area write request smoothly;
405: access arbitration device notice memory block distribution table module is upgraded corresponding clauses and subclauses, is 1 with their extreme higher position, and low 7 area codes that then write continuous next RAM piece in order form a chain structure.
406: the access arbitration device is received the read request to certain buffering area, checks allocation of space situation and corresponding read-write pointer when forward terminal, and seeing if there is data can be read out.If the read-write pointer equates, show free of data in this buffering area, return buffer empty signal; If do not wait the read operation that then wraps.
407: in the read operation process, carry out the recovery of memory block, whenever read away the content of a complete memory block, it is the region of memory that read pointer leaves the allocation table entries correspondence of original sensing, the access arbitration device just notifies memory block distribution table to regain this clauses and subclauses, is its extreme higher position 0, uses for other end points to discharge ram space.
Claims (2)
1, a kind of centralized dispatching controller of intelligent multi buffer management is characterized in that, comprising:
The shared data of multiple buffer are write incoming interface, are used for switching at a plurality of buffering areas, and the data that receive at the purpose buffering area write request and data;
The shared data of multiple buffer are read interface, are used for switching at a plurality of buffering areas, and reception is at the request of reading of the data of purpose buffering area and data output is provided;
The switch control unit of two different buffering area access request is used to select appointed buffer, to carry out data read-write operation;
A plurality of control signal wires that link to each other with memory with each control module cooperate the transmission data that each device communication module is controlled;
Described control module is specific as follows:
An access arbitration device is used to arbitrate the access request to different buffering areas, and whether decision authorizes or denied access; In granted access, check and renewal buffering area allocation table, used later at buffering area and reclaim memory space by the mode of upgrading allocation table;
An address pointer holding unit keeps the initial address of different buffering areas dynamically, when the visit to certain buffering area is authorized to, obtains the first address of this buffering area memory from this unit;
The storage allocation location of a dynamic dispatching buffering area in the time distributing new memory space will for certain buffering area, is checked available memory space address by this unit, and the notice moderator is authorized visit, and upgrades corresponding memory block distribution table;
A memory cell gatherer that dynamically reclaims used buffering area, after the part or all of data of buffering area were read out, this unit upgraded the data that table is distributed in corresponding memory block, and these memory blocks of notice moderator can be reallocated use;
Described memory is specific as follows:
The centralised storage district that shared two passages of support of all buffering areas are visited simultaneously is used to store actual data, and the data organization mode is in strict accordance with the indicated chain structure storage of allocation table;
A buffering area allocation table, the mode record storage unit of employing chain list index is distributed to the situation of each buffering area, and each buffer blocks is corresponding clauses and subclauses in allocation table, are managed by the access arbitration device.
2, a kind of centralized dispatching controller of intelligent multi buffer management as claimed in claim 1 that uses is concentrated the method for dynamic dispatching to multiple buffer, with the buffering area allocation table serves as to handle core, automatically the scheduling of carrying out the memory block when work distributes and recovery, it is characterized in that, comprise the steps:
(1) access end is initiated the write data requests to certain buffering area;
(2) the access arbitration device is inquired about the situation of current memory block distribution table, whether determines granted access according to the access privileges of each end points;
(3) the access arbitration device for it distributes new storage address, and upgrades the corresponding buffer region allocation table for the visit of having authorized;
(4) be read out when certain buffering area, the access arbitration device is regained this piece storage area at once, and the corresponding buffer region allocation table is emptied, and uses for other buffering area with slot milling;
(5) data structure in the buffering area allocation table is the chain structure of multiple-limb, the corresponding chained list of each buffering area.
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| CNB2006101481625A CN100505676C (en) | 2006-12-28 | 2006-12-28 | Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method |
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| CNB2006101481625A CN100505676C (en) | 2006-12-28 | 2006-12-28 | Centralized scheduling controller for intelligent multi buffer management and dynamic scheduting method |
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| CN100505676C true CN100505676C (en) | 2009-06-24 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101252519B (en) * | 2008-03-21 | 2010-10-27 | 华为技术有限公司 | Apparatus and method for scheduling data |
| CN101287177B (en) * | 2008-06-05 | 2011-06-15 | 北京佳讯飞鸿电气股份有限公司 | Method for fail call prompt by short message of multimedia dispatching station |
| JP2010003067A (en) * | 2008-06-19 | 2010-01-07 | Sony Corp | Memory system, access control method therefor, and computer program |
| US8823719B2 (en) * | 2010-05-13 | 2014-09-02 | Mediatek Inc. | Graphics processing method applied to a plurality of buffers and graphics processing apparatus thereof |
| CN102739818B (en) * | 2012-06-21 | 2015-05-27 | 华为技术有限公司 | Address scheduling method, device and system |
| CN103259745A (en) * | 2013-05-31 | 2013-08-21 | 东蓝数码股份有限公司 | Design method for improving memory usage rate of buffer area in network programming |
| CN111475438B (en) * | 2015-08-12 | 2021-12-10 | 北京忆恒创源科技股份有限公司 | IO request processing method and device for providing quality of service |
| CN108153679A (en) * | 2016-12-05 | 2018-06-12 | 腾讯科技（深圳）有限公司 | A kind of data loading, the method, apparatus and equipment of data processing |
| CN107888512B (en) * | 2017-10-20 | 2021-08-03 | 常州楠菲微电子有限公司 | Dynamic shared buffer memory and switch |
| CN111259375A (en) * | 2020-01-09 | 2020-06-09 | 青岛海尔科技有限公司 | Processing method and device for access request applied to operating system of Internet of things |
| CN113868292A (en) * | 2020-06-30 | 2021-12-31 | 华为技术有限公司 | Data reading method, data writing method, device and system |
| CN113032302A (en) * | 2021-04-07 | 2021-06-25 | 杭州共有科技有限公司 | Method for improving arbitration performance of chained data |
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