CN107888512B - Dynamic shared buffer memory and switch - Google Patents

Dynamic shared buffer memory and switch Download PDF

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Publication number
CN107888512B
CN107888512B CN201710986164.XA CN201710986164A CN107888512B CN 107888512 B CN107888512 B CN 107888512B CN 201710986164 A CN201710986164 A CN 201710986164A CN 107888512 B CN107888512 B CN 107888512B
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read
write
data
address
request
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CN107888512A (en
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王克非
张鹤影
黄文斌
屈银东
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Changzhou Nanfei Microelectronics Co., Ltd.
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Changzhou Nanfei Microelectronics Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/548—Queue

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  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)

Abstract

The embodiment of the invention provides a dynamic shared buffer memory and a switch, belonging to the field of message queue management of computer network switches. The dynamic shared buffer memory comprises a data input port, a read data processing unit, an address access management unit, a queue management unit, a data buffer area and a data output port which are matched to realize read-write requests, read-write addresses and data transmission. The embodiment of the invention designs a dynamic shared buffer area capable of supporting thousands of queues, can eliminate various access conflicts generated when a write buffer area and a read buffer area occur simultaneously, and can support a continuous write buffer area and a continuous read buffer area. In addition, the embodiment of the invention also realizes that the memories of one read port and one write port support two write requests and two read requests by adopting the idle address pre-writing and pre-reading modes.

Description

Dynamic shared buffer memory and switch
Technical Field
The invention relates to the field of message queue management of computer network switches, in particular to a dynamic shared buffer memory supporting thousands of queues and a switch with the dynamic shared buffer memory.
Background
The switches of computer networks usually store the messages waiting to be forwarded in a centralized buffering manner. Specifically, a message is input into the switch from an input port, processed by an inlet pipeline, table look-up is carried out to obtain an output port of the message, the message is stored in a centralized buffer area, and meanwhile, message description information is sent to a scheduler to wait for being scheduled and output. The message description information usually includes scheduling information required by the scheduler, such as an output port of the message, a storage location in the centralized buffer, a length, a priority, and the like. The scheduler distributes the messages to different queues of a target output port according to the message priority, then links the message description information to the message linked list of the corresponding queue, and then sequentially schedules the message description information from the head of the queue linked list. Then, the centralized buffer obtains the position of message storage from the scheduled message description information, reads out the message from the corresponding position, and sends the message to the output port, thereby completing the message forwarding process.
To provide finer granularity of quality of service, a plurality of queues of different priorities, e.g. 16, 32, 48, or even 64, are provided per output port. If 16 ports share a scheduler, it is necessary to support management and scheduling of 1024 queues. The message description information of the queues of the same scheduler is stored in a shared data buffer area, and the message description information of the queues are mutually linked to form a linked list. The message description information quantity of different queues is different, and in order to reduce the depth of a data buffer area and save the chip area, the data buffer area is used among the queues in a dynamic sharing mode.
The multi-queue dynamic shared buffer is a common buffer allocation and management mode, in the previous implementation, only a few queues share the buffer, for example, 4, 6 or 8, the state information of the queues, for example, a head pointer, a tail pointer, a queue length, and the like, are implemented by using registers, and when in use, the corresponding registers are directly used. However, when the conventional implementation is extended to support thousands of queues, the queue status information to be stored increases rapidly, and it is not possible to store the information in a register, and it is necessary to solve the conflict between the storage and quick access of the status information such as the queue head pointer, tail pointer, and queue length, and the access to the head pointer, tail pointer, queue length, and address buffer when the data writing into the buffer and the data reading from the buffer occur simultaneously.
Accordingly, a new scheme for implementing multi-queue dynamic shared buffer needs to be proposed.
Disclosure of Invention
Embodiments of the present invention provide a dynamic shared buffer and a switch, which are used to solve the problem that a shared buffer of an existing switch cannot support thousands of queues.
In order to achieve the above object, an embodiment of the present invention provides a dynamic shared buffer memory, including:
the data input port is used for writing message description information containing a write request and written data; a write data processing unit connected to the data input port, configured to extract a queue number W from the written data, and use the written data as write data D, and configured to perform write operation according to the write request, the queue number W, and a queue length L corresponding to the queue number WWGenerating a write request IH, generating a write request N when the write request is valid and the write request IH is invalid, and generating a read request I, a write request T and a write request D according to the write request;
a read data processing unit for inputting a read request and a read queue number, taking the read queue number as a queue number R, sending the queue number R to the write data processing unit to assist in judging the validity of the write request IH, and determining a queue length L corresponding to the queue number R when the read request is validRIf the number of the read requests is larger than 1, generating a read request N;
the address access management unit is used for receiving the read request I and the write request N from the write data processing unit, receiving the read request and the read request N from the read data processing unit, taking the read request as the write request I, and outputting read data N, read data D and/or read data I according to addresses corresponding to the requests;
a queue management unit comprising a queue head pointer memory, a queue tail pointer memory, and a queue length memory, for: receiving a queue number W, a write request T and a write request IH from the write data processing unit, taking the queue number W as a read address, a write address IH, a read address T and a write address T, receiving a queue number R as a read address H from the read data processing unit, and receiving a read request as a write request OH; reading out data from the queue tail pointer memory according to the read address T as read data T, and sending the read data T to the address access management unit as a write ground of the next dataWhen the write request T is valid, storing the read data I output by the address access management unit as write data T in a position corresponding to the write address T in the queue tail pointer memory; according to the write request IH, writing the read data I output by the address access management unit as write data IH into a position corresponding to a write address IH in the queue head pointer memory, reading data from a position corresponding to a read address H in the queue head pointer memory as read data H, sending the read data H to the address access management unit as write data I of a released free address and a read address N of an address where next data is read, receiving the read data N from the address access management unit as write data OH, and writing the write data OH into a position corresponding to a write address OH in the queue head pointer memory when the write request OH is valid; and a queue length L according to the write request, the queue number W, the read request, the queue number R and the queue number WWAnd queue length L of queue number RRGenerating a write request IL, a write address IL and write data IL or generating a write request OL, a write address OL and write data OL, and sending the write request OL, the write address OL and the write data OL to the queue length memory, so that the queue length memory writes the write data IL and/or the write data OL according to the effectiveness of the write request IL and the write request OL;
a data buffer for receiving a write request D and write data D from the write data processing unit, receiving read data I from the address access management unit, and regarding the read data I as a write address D, and storing the write data D in a memory cell corresponding to the write address D in the data buffer when the write request D is valid, for receiving a read request as a read request D from the read data processing unit, receiving read data H as a read address D from the queue head pointer memory, and reading data from the data buffer as read data D according to the read address D when the read request D is valid, and sending the read data D to a data output port; and
and a data output port for outputting the read data D.
In another aspect, the present invention provides a switch provided with the above dynamic shared buffer memory.
Through the technical scheme, the embodiment of the invention has the beneficial effects that: the embodiment of the invention designs a dynamic shared buffer area capable of supporting thousands of queues, can eliminate various access conflicts generated when a write buffer area and a read buffer area occur simultaneously, and can support a continuous write buffer area and a continuous read buffer area. In addition, the embodiment of the invention also realizes that the memories of one read port and one write port support two write requests and two read requests by adopting the idle address pre-writing and pre-reading modes.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a diagram illustrating a dynamic shared cache according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a preferred dynamic shared cache memory according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of an address access management unit according to an embodiment of the present invention; and
fig. 4 is a schematic structural diagram of a preferred address access management unit according to an embodiment of the present invention.
Description of the reference numerals
100 dynamic shared buffer memory 110 data input port
120 write data processing unit 130 read data processing unit
140 address access management unit 150 queue management unit
160 data buffer 170 data output port
121 queue number W identification module 122 enqueue request and read idle address module
123 write request IH generation module 124 write request N generation module
131 read request input port 132 read request N generation module
141 free address preprocessing module 142 FIFO processing module
143 idle address management module 144 address memory read-write management module
145 address memory 151 queue head pointer memory
152 queue tail pointer memory 153 queue length memory
154 queue length write request generation module
1411 free address pre-read FIFO Module 1412 free address pre-write FIFO Module
1421R _ FIFO counter 1422R _ FIFO write request generation module
1423W _ FIFO counter 1424W _ FIFO read request generation module
1431 free address register module 1432 free address write request generation module
1433 free address queue pointer management module
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
It should be noted that the embodiments of the present invention relate to a plurality of signals with similar names, for example, a plurality of writing addresses, reading addresses, etc., and for the convenience of clearly describing the embodiments of the present invention, the following description distinguishes the embodiments of the present invention and the figures relate to signals with similar names and types, but those skilled in the art should understand that these letters are only used for distinguishing different signals, and are intended to exemplarily describe some signals, but do not have actual physical meanings. In the case where no description is given to the contrary, the letters and their representative exemplary descriptions may be: FIFO is an abbreviation of First Input First Output, and represents First-in First-out, W represents write-in, R represents read-out, W _ FIFO represents write-in First-out, R _ FIFO represents read-out First-in First-out, D represents data, I represents idle address, H represents head, T represents tail, IH represents Input write head, OH represents Output write head, IL represents Input write queue length, OL represents Output write queue length, N represents next data address, P represents previous data address, M represents middle part, and IM represents Input write middle part. Accordingly, for example, the write request T indicates a request for a tail write, the write request D indicates a request for a write of data, and the like.
In addition, in the embodiment of the present invention, when a certain signal (for example, a write request T) takes a value of 1, it indicates valid, and when the value takes a value of 0, it indicates invalid.
Fig. 1 is a schematic diagram of a dynamic shared buffer memory for providing a switch with a dynamic shared buffer supporting thousands of queues according to an embodiment of the present invention. As shown in fig. 1, the dynamic shared cache memory 100 may include:
the data input port 110 is used for writing message description information including a write request and written data.
A write data processing unit 120, connected to the data input port 110, configured to extract a queue number W from the written data, use the written data as write data D, generate a read request I, a write request T, and a write request D according to the write request, and use the read request, the queue number W, and a queue length L corresponding to the queue number W according to the write request, the queue number W, and the write request DWGenerating a write request IH, and generating a write request N when the write request is valid and the write request IH is invalid.
A read data processing unit 130, connected to the write data processing unit 120, configured to input a read request and a read queue number, use the read queue number as a queue number R, send the queue number R to the write data processing unit 120 to assist in determining validity of the write request IH, and use a queue length L corresponding to the queue number R when the read request is validRAnd if the number is greater than 1, generating a read request N.
And an address access management unit 140, connected to the data input port 110, the write data processing unit 120, and the read data processing unit 130, and configured to receive the read request I and the write request N from the write data processing unit 120, receive the read request and the read request N from the read data processing unit, use the read request as the write request I, and output the read data N, the read data D, and/or the read data I according to an address corresponding to each request.
The queue management unit 150 includes a queue head pointer memory 151, a queue tail pointer memory 152, and a queue length memory 153, and is configured to perform: 1) receiving a queue number W, a write request T, and a write request IH from the write data processing unit 120, and taking the queue number W as a read address, a write address IH, a read address T, and a write address T, and receiving a queue number R as a read address H and a read request as a write request OH from the read data processing unit 130; 2) reading data from the queue tail pointer memory 152 according to a read address T as read data T, sending the read data T to the address access management unit 140 as a write address N of next data, and when a write request T is valid, saving the read data I output by the address access management unit 140 as write data T in a position in the queue tail pointer memory 152 corresponding to the write address T; 3) according to the write request IH, writing the read data I output by the address access management unit 140 as write data IH to a position corresponding to the write address IH in the queue head pointer memory 151, reading data from a position corresponding to the read address H in the queue head pointer memory 151 as read data H, and sending the read data H to the address access management unit 140 as write data I of a released free address and a read address N of an address at which the next data is read, and receiving the read data N from the address access management unit 140 as write data OH, and when the write request OH is valid, writing the write data OH to a position corresponding to the write address OH in the queue head pointer memory 151; and 4) length L according to write request, queue number W, read request, queue number R, queue number WWQueue number R, queue length L, and queue number RRGenerating a write request IL, a write address IL and write data IL or generating a write request OL, a write address OL and write data OL and sending the write request OL, the write address OL and the write data OL to the queue length memoryThe memory 153 causes the queue length memory 153 to write the write data IL and/or the write data OL according to the validity of the write request IL and the write request OL.
A data buffer 160 for receiving the write request D and the write data D from the write data processing unit 120, receiving the read data I from the address access management unit 140, and taking the read data I as a write address D, and storing the write data D in a memory cell corresponding to the write address D in the data buffer when the write request D is valid, for receiving the read request from the read data processing unit 130 as a read request D, receiving the read data H from the queue head pointer memory 151 as a read address D, and reading the data from the data buffer 160 as the read data D according to the read address D when the read request D is valid, and sending the read data D to a data output port.
And a data output port 170 for outputting the read data D.
FIG. 2 is a schematic diagram of a preferred dynamic shared cache that is a preferred implementation of the dynamic shared cache of FIG. 1, according to an embodiment of the invention. As shown in fig. 2, the write data processing unit 120 may include a queue number W identifying module 121, an enqueue request and read free address module 122, a write request IH generating module 123, and a write request N generating module 124; the read data processing unit 130 may include a read request input port 131 and a read request N generation module 132; the queue management unit 150 may include a queue head pointer memory 151, a queue tail pointer memory 152, a queue length memory 153, and a queue length write request generation module 154.
The following takes the dynamic shared buffer memory shown in fig. 2 as an example, and details of implementation of each part of the dynamic shared buffer memory according to the embodiment of the present invention are specifically described.
One, data input port 110
The data input port 110 is connected to the queue length write request generation module 154, the queue number W identification module 121, and the enqueue request and read free address module 122. Moreover, the data input port 110 writes message description information, which includes a write request and written data, and sends the message description information to the enqueue request and read idle address module 122, the written data is also sent to the queue number W identification module 121, and the write request is also sent to the queue length write request generation module 154.
Here, the application of the write request and the written data in each module will be described below, and will not be described herein again.
Two, write data processing unit 120
1) Queue number W identification module 121
Preferably, the queue number W identifying module 121 is configured to extract the queue number W according to the written data, and send the queue number W as the read address of the queue length memory 153, the write address IH of the queue head pointer memory 151, and the read address T and the write address T of the queue tail pointer memory 152.
More preferably, the queue number W identifying module 121 extracts the queue number W from the relevant bit field of the written data, and sends the queue number W to the queue length write request generating module 154 as a judgment condition for generating the write request IL and the write request OL. In addition, the queue number W is also sent to the write request IH generation module 123 as one of the judgment conditions for generating the write request IH.
2) Enqueue request and read free address module 122
The enqueue request and read idle address module 122 is connected to the data input port 110, the address access management unit 140, the data buffer 160, the queue tail pointer memory 152, the write request IH generation module 123, and the write request N generation module 124, and is configured to generate a read request I, a write request T, and a write request D according to the write request, and use the written data as write data D.
Specifically, the enqueue request and read idle address module 122 receives written message description information from the data input port 110, generates a read request I for reading an idle address according to the write request, and sends the read request I to the address access management unit; generating a write request, and sending the write request to the write request IH generation module 123 and the write request N generation module 124; generating a write request as a write request T, sent to the queue tail pointer memory 152; a write request is generated as write request D and the written data is sent to data buffer 160 as write data D.
3) Write request IH generation module 123
The write request IH generation module 123 is connected to the queue number W identification module 121, the enqueue request and read idle address module 122, the queue length memory 153, the read request input port 131, the queue head pointer memory 151, and the write request N generation module 124, and is configured to obtain a write request from the enqueue request and read idle address module 122, obtain a queue number W from the queue number W identification module 121, and obtain a queue length L from a position corresponding to the queue number W in the queue length memory 153WAnd according to the obtained write request, queue number W and queue length LWA write request IH is generated. Further, the generated write request IH is sent to the queue head pointer storage 151 as a write request for the storage.
Wherein, according to the obtained write request, queue number W and queue length LWThe method for generating the write request IH can comprise the following steps: if the write request is valid, and the queue length LWIs zero, or queue length LW1, but the read request is valid and queue number W is equal to queue number R, then write request IH is valid; otherwise, write request IH is invalid.
4) Write request N generation module 124
The write request N generating module 124 is connected to the enqueue request and read idle address module 122, the write request IH generating module 123, and the address access management unit 140, and is configured to obtain a write request from the enqueue request and read idle address module 122, obtain a write request IH from the write request IH generating module 123, generate a write request N when the write request is valid and the write request IH is invalid, and send the write request N to the address access management unit 140.
Read data processing unit 130
1) Read request input port 131
The read request input port 131 is connected to the queue length write request generation module 154, the queue length memory 153, the read request N generation module 132, the write request IH generation module 123, the queue head pointer memory 151, the data buffer 160, and the address access management unit 140, and is configured to input a read request and a read queue number, send the read request to the queue head pointer memory 151 as a write request OH, send to the data buffer 160 as a read request D, and send to the address access management unit 140 as a write request I. In addition, the read request input port 131 is further configured to send the read queue number as a queue number R to the queue length memory 153 as a read address, to the queue head pointer memory 151 as a read address H and a write address OH, and to send the read request and the queue number R to the write request IH generation module 123 to assist in determining the validity of the write request IH, i.e., as a determination condition. In addition, the read request and the queue number R are also sent to the queue length write request generation module 154 as determination conditions.
2) Read request N generation module 132
The read request N generation module is connected to the read request input port 131, the queue length memory 153, and the address access management unit 140, and is configured to receive a read request from the read request input port 131, and receive a queue length L from the queue length memory 153RAnd when the read request is valid and the queue length LRIf the number is greater than 1, a read request N is generated and sent to the address access management unit 140.
Fourth, address access management unit
The specific implementation method of the address access unit will be described in detail below with reference to fig. 3 and 4, and will not be described herein again.
Fifthly, a queue management unit 150
1) Queue head pointer storage 151
The queue head pointer memory 151 is connected to the queue number W identifying module 121, the write request IH generating module 123, the address access managing unit 140, and the read request input port 131, and is configured to write the read data I output by the address access managing unit 140 as write data IH to a position in the queue head pointer memory corresponding to the write address IH according to the write request IH received from the write request IH generating module 123. Furthermore, the queue head pointer memory 151 is also configured to send read data from a position corresponding to a read address H (receiving the queue number R from the read request input port 131 as the read address H) in the queue head pointer memory to the data buffer 160 as a read address D, and also to send the read data H to the address access management unit 140 as write data I of a released free address and a read address N of an address at which next data is read. Further, the queue head pointer storage 151 is further configured to receive the read data N from the address access management unit 140 as write data OH, and write the write data OH into a position in the queue head pointer storage corresponding to the write address OH when the write request OH is valid.
Thus, it can be seen that the queue head pointer memory 151 needs to provide two write ports, one read port, and when the read address is valid, data needs to be read out in the same clock cycle. In light of these access characteristics, it is desirable to implement queue head pointer memory 151 of embodiments of the present invention using a register array having two write ports and two read ports.
2) Queue tail pointer memory 152
The queue tail pointer memory 152 is connected to the queue number W identification module 121, the enqueue request and read idle address module 122, and the address access management unit 140, and is configured to receive a read address T and a write address T from the queue number W identification module 121, read data from the queue tail pointer memory 152 according to the read address T as read data T, and send the read data T to the address access management unit 140 as a write address N of next data. The queue tail pointer memory 152 is further configured to store the read data I output by the address access management unit 140 as write data T at a position in the queue tail pointer memory 152 corresponding to the write address T when the write request T received from the enqueue request and read free address module 122 is valid.
3) Queue length memory 153
The queue length memory 153 is connected to the read request input port 131, the queue number W identifying module 121, the queue length write request generating module 154, the write request IH generating module 123, and the read request N generating module 124, and is configured to generate a corresponding write number according to the validity of the write request IL and the write request OL generated by the queue length write request generating module 154According to IL and write data OL, the data is written into the corresponding position in the queue length memory 153 according to the write address IL and the write address OL corresponding to each. In addition, the queue length memory 153 is further configured to read the corresponding queue length L according to the queue number W and the queue number R respectively obtained from the queue number W identification module 121 and the read request input module 131WAnd queue length LR。
The method for writing the write address IL and the write address OL may include: when the write request IL is effective, writing the write data IL into a position corresponding to the write address IL; when the write request OL is valid, the write data OL is written into the position corresponding to the write address OL.
4) Queue length write request generation module 154
A queue length write request generating module 154, connected to the data input port 110, the queue number W identifying module 121, the queue length memory 153, and the read request input port 131, for receiving a write request from the data input port 110, receiving a queue number W from the queue number W identifying module 121, and receiving a queue length L from the queue length memory 153WAnd queue length LRReceives a read request and a queue number R from the read request input port 131, and is based on a write request, a queue number W, and a queue length LWQueue length LRAnd reading the request and the queue number R, generating a write request IL, a write address IL and write data IL or generating a write request OL, a write address OL and write data OL, and sending the generated data to the queue length memory.
The method for generating the write request IL, the write address IL and the write data IL or generating the write request OL, the write address OL and the write data OL may include: if the write request is valid and the read request is invalid or the write request is valid and the read request is valid but the queue number W is different from the queue number R, generating a write request IL, taking the queue number W as a write address IL, and taking the queue length LWPlus one as write data IL; and if the read request is valid and the write request is invalid or the read request is valid and the write request is valid, and the queue number W is different from the queue number R, generating a write request OL, taking the queue number R as a write address OL, and taking the queue length L as the write address OLRMinus one as write data OL.
Sixthly, a data buffer 160
The data buffer 160 is connected to the enqueue request and read idle address module 122, the address access management unit 140, the read request input port 131, and the data output port 170. It receives write request D and write data D from enqueue request and read idle address module 122, receives read data I from address access management unit 140, uses read data I as write address D, and stores write data D in the memory cell corresponding to write address D when write request D is valid. In addition, data buffer 160 receives a read request from read request input port 131 as read request D; the read data H is received from the queue head pointer memory 151 as a read address D, and when the read request D is valid, the data H is read from the read address D and sent to the data output port 170 as read data D.
Seventh, data output port 170
The data output port 170 is connected to the data buffer 160 for outputting the read data D.
In summary, the dynamic shared buffer memory according to the embodiment of the present invention can support thousands of queues, eliminate various access conflicts generated when the write buffer and the read buffer occur simultaneously, and support a continuous write buffer and a continuous read buffer.
Fig. 3 is a schematic structural diagram of an address access management unit according to an embodiment of the present invention. As shown in fig. 3, the address access management unit 140 may include:
a free address preprocessing module 141, configured to receive a read request I from the write data processing unit 120 to read a free address at the head of the current FIFO queue as read data I and send the read data I to the queue head pointer memory 151, the queue tail pointer memory 152, and the data buffer 160, and further configured to take the read request received from the read data processing unit 130 as a write request I and write the released free address read from the queue head pointer memory 151 as write data I into the current FIFO queue, and generate W _ FIFO read data according to the W _ FIFO read request, and generate a W _ FIFO read data valid signal.
A FIFO processing module 142, connected to the free address preprocessing module 141, configured to obtain a read request I and a write request I, count an R _ FIFO count value indicating the number of times that an R _ FIFO write request is an effective value according to the read request I, count a W _ FIFO count value indicating the number of times that a W _ FIFO write request is an effective value according to the write request I, and generate an R _ FIFO write request sent to the free address preprocessing module 141 by combining the read request I, R _ FIFO count value, data read by the W _ FIFO, a data valid signal read by the W _ FIFO, a free address R, and a free address valid R, and send data read by the W _ FIFO or the free address R as R _ FIFO write data to the free address preprocessing module 141; and is further configured to generate a W _ FIFO read request sent to the idle address preprocessing module 141 according to the R _ FIFO required data, the data valid signal read by the W _ FIFO, and the write request N.
The free address management module 143 is configured to, according to the read request N, the head pointer H, the head pointer valid H signal, the data read by the W _ FIFO, the data valid signal read by the W _ FIFO, and the R _ FIFO required data, use the head pointer H as a free address R, generate a free address R valid signal, send the free address R and the free address R valid signal to the FIFO processing module, and generate a read request IM; generating a write request P according to the data read by the write request N, W _ FIFO, the data valid signal read by the W _ FIFO and the R _ FIFO required data, and taking the data read by the W _ FIFO as write data P; and the device is also used for taking the write request P as a write request IM, taking the write data P as write data IM, taking the tail pointer of the idle address queue as a write address IM, and generating head pointer H and head pointer valid H signals according to the read request IM, the write request P, the write data P and the read data IM.
The address memory read-write management module 144 is configured to send the read data I as write data N and the write request IM or the write request N as write request M to the address memory, and further configured to generate write data M according to the received write request IM, write address N, and write data N, and generate a read request M, a read address M, read data IM, and read data N according to the received read request IM, read request N, and read data M.
The address memory 145 is configured to receive the write request M, the write address M, the write data M, the read request M, and the read address M from the address memory read-write management module, write the write data M into the memory cell corresponding to the write address M in the address memory when the write request M is valid, and read data from the memory cell corresponding to the read address M as read data M when the read request M is valid, and send the read data M to the address memory read-write management module 144.
Fig. 4 is a schematic structural diagram of a preferred address access management unit according to an embodiment of the present invention, which is an implementation of the address access management unit shown in fig. 3. As shown in fig. 4, for the address access management unit 140, the free address preprocessing module 141 may include a free address pre-read FIFO module 1411 and a free address pre-write FIFO module 1412, the FIFO processing module 142 may include an R _ FIFO counter 1421, an R _ FIFO write request generation module 1422, a W _ FIFO counter 1423, and a W _ FIFO read request generation module 1424, and the free address management module 143 may include a free address register module 1431, a free address write request generation module 1432, and a free address queue pointer management module 1433.
The following takes the address access management unit shown in fig. 4 as an example, and details of implementation of each part of the address access management unit according to the embodiment of the present invention are specifically described.
First, idle address preprocessing module 141
1. Free address pre-read FIFO module 1411
A free address pre-read FIFO module for receiving a read request I from the write data processing unit 120 to read out a free address at the head of the current FIFO queue as read data I, and sending the read data I to the queue head pointer memory 151, the queue tail pointer memory 152, and the data buffer 160.
The depths of the free address pre-read FIFO module 1411 and the free address pre-write FIFO module 1412 are both 4. The free address pre-read FIFO module 1411 has the same structure as a common FIFO, and comprises 4 storage units, a write address management unit and a read address management unit. Initially, the writing address and the reading address are both 0, a writing request is received, the writing data is stored in a storage unit pointed by the current writing address, and the writing address is increased by one; and receiving a reading request, reading data from the position pointed by the current reading address to serve as read data I, and adding one to the reading address. Before the buffer normally works, the free address pre-reading FIFO module needs to be initialized, 4 addresses at the head of the free address queue, namely 0, 1, 2 and 3, are respectively written into four storage units of the free address pre-reading FIFO module 1411, and the R _ FIFO count value is set to 4.
2. Free address pre-write FIFO module 1412
The free address pre-write FIFO module 1412 is connected to the read request input port 131, the queue head pointer memory 151, the R _ FIFO write request generation module 1422, the W _ FIFO read request generation module 1424, and the free address write request generation module 1432, and is configured to use the read request input by the read data processing unit as a write request I, write the released free address read from the queue head pointer memory 151 as a write data I into the current FIFO queue, write the write data I being written into or the data read from the current read address of the current FIFO queue as the data read from the W _ FIFO according to the W _ FIFO read request, and generate a data valid signal read from the W _ FIFO.
Specifically, the free address pre-write FIFO module 1412 receives a write request I from the read request input port 131, receives write data I from the queue head pointer storage 151, and stores the write data I to the storage unit pointed by the FIFO current write address when the write request I is valid; the free address pre-write FIFO module 1412 receives the W _ FIFO read request from the W _ FIFO read request generation module 1424, and if there is data in the FIFO and the data valid signal read by the W _ FIFO is invalid, or there is data in the FIFO and the W _ FIFO read request is valid, continues to generate the W _ FIFO read request, and if the write request I is valid and the current write address of the FIFO is equal to the read address, treats the write data I being written as the data read by the W _ FIFO, and generates the data valid signal read by the W _ FIFO; otherwise, reading data from the current read address of the FIFO as the data read by the W _ FIFO, and generating a data valid signal read by the W _ FIFO; if the W _ FIFO read request is valid but there is no data in the FIFO, the W _ FIFO read data valid signal is changed to invalid.
Second, FIFO processing module 142
1. R _ FIFO counter 1421
The R _ FIFO counter 1421 is connected to the read request input port 131 and the R _ FIFO write request generation module 1422, and is configured to receive the read request I from the write data processing unit, and count, according to the read request I, an R _ FIFO count value indicating the number of times that the R _ FIFO write request is a valid value.
Specifically, initially, the R _ FIFO count value is 0. If the R _ FIFO writing request is valid, the reading request I is invalid, and the R _ FIFO counting value is increased by one; if the R _ FIFO write request is not valid, the read request I is valid, and the R _ FIFO count value is decremented by one. Otherwise, the R _ FIFO count value remains unchanged. The R _ FIFO count value is sent to the R _ FIFO write request generation module 1422.
2. R _ FIFO write request Generation Module 1422
An R _ FIFO write request generation module 1422, configured to receive the read request I from the write data processing unit 120, receive an R _ FIFO count value from the R _ FIFO counter 1421, receive the data read out by the W _ FIFO and the data valid signal read out by the W _ FIFO from the free address pre-write FIFO module 1412, combine a free address R and a free address valid R, generate an R _ FIFO write request sent to the free address pre-read FIFO module 1411, and send the data read out by the W _ FIFO or the free address R as R _ FIFO write data to the free address pre-read FIFO module 1411.
Specifically, the R _ FIFO write request generation module 1422 is connected to the read request input port 131, the free address pre-read FIFO module 1411, the R _ FIFO counter 1421, the free address pre-write FIFO module 1412, the free address register module 1431, the W _ FIFO read request generation module 1424, and the free address write request generation module 1432. The read request I is received from the read request input port 131, the R _ FIFO count value is received from the R _ FIFO counter 1421, the free address R and the free address valid R are received from the free address register module 1431, and the data read out from the W _ FIFO and the data valid signal read out from the W _ FIFO are received from the free address pre-write FIFO module 1412. If the R _ FIFO count value is less than 4 or the R _ FIFO count value is equal to 4 and the read request I is valid, the data read by the W _ FIFO is valid or the free address is valid, R _ FIFO write request is generated. If the data read by the W _ FIFO is valid, sending the data read by the W _ FIFO to the free address pre-reading FIFO module 1411 as R _ FIFO write data; otherwise, if the free address is valid, the free address is used as R _ FIFO write data and sent to the free address pre-read FIFO. If the R _ FIFO count value is less than 4 or the R _ FIFO count value is equal to 4 and the read request I is valid, the R _ FIFO required data signal is generated and sent to the W _ FIFO read request generation module 1424, the free address register module 1431, and the free address write request generation module 1432.
3) W _ FIFO counter 1423
The W _ FIFO counter 1423 is connected to the read request input port 131, the W _ FIFO read request generation module 1424, and the free address pre-write FIFO module 1412, and is configured to receive the write request I from the read data processing unit, and count a W _ FIFO count value indicating the number of times that the W _ FIFO write request is a valid value according to the write request I.
Specifically, the W _ FIFO counter 1423 receives a write request I from the read request input port, and receives a W _ FIFO read request from the W _ FIFO read request generation module. Initially, the W _ FIFO count value is 0. If the write request I is valid, the W _ FIFO read request is invalid, and the W _ FIFO count value is increased by one; if the write request I is not valid, the W _ FIFO read request is valid, and the W _ FIFO count value is decremented by one. The W _ FIFO count value is greater than zero, or equal to 0 and the write request I is valid, considering that there is data in the W _ FIFO.
4) W _ FIFO read request Generation Module 1424
The W _ FIFO read request generating module 1424 is connected to the free address pre-write FIFO module 1412, the R _ FIFO write request generating module 1422, and the write request N generating module 124, and is configured to generate a W _ FIFO read request sent to the free address pre-write FIFO module 1412 according to the R _ FIFO write request generating module 1422 receiving R _ FIFO required data, the W _ FIFO read data valid signal received from the free address pre-write FIFO module 1412, and the write request N received from the write data processing unit 120 (specifically, the write request N generating module 124).
Further, if the data read by the W _ FIFO is valid and the R _ FIFO needs data, or the data read by the W _ FIFO needs data to be invalid and the write request N is invalid, a W _ FIFO read request is generated and sent to the free address pre-write FIFO.
Third, idle address management module 143
1. Idle address register module 1431
A free address register module 1431, configured to receive the read request N from the read data processing unit, receive a head pointer H and a head pointer valid H signal from the free address queue pointer management module, receive data read by the W _ FIFO and a data valid signal read by the W _ FIFO from the free address pre-write FIFO module, receive R _ FIFO required data from the R _ FIFO write request generation module, regard the head pointer H as a free address R according to the received data, generate a free address R valid signal, send the free address R and the free address R valid signal to the R _ FIFO write request generation module, and generate a read request IM according to the received data.
Specifically, the free address register module 1431 is connected to the R _ FIFO write request generation module 1422, the free address pre-write FIFO module 1412, the free address queue pointer management module 1433, the address memory read-write management module 144, and the read request N generation module 132, and receives the read request N from the read request N generation module, the head pointer H and the head pointer valid H from the free address queue pointer management module, the data read from the W _ FIFO and the data read from the W _ FIFO are valid from the free address pre-write FIFO, and the R _ FIFO write request generation module receives the R _ FIFO required data. If the free address valid R signal is invalid or the R _ FIFO needs data and the data valid signal read by the W _ FIFO is invalid, the free address valid R signal is valid, the head pointer valid H signal is valid, and the read request N is invalid, generating a free address valid R signal and sending the free address valid R signal to the R _ FIFO write request generating module; taking a head pointer H as an idle address R, and sending the idle address R to an R _ FIFO write request generation module; if the free address effective R signal is invalid, or R _ FIFO needs data, and the data effective signal read by W _ FIFO is invalid, the free address effective R signal is valid, under the two conditions, the head pointer is required to be valid H, the read request N is invalid, and at this time, a read request IM is generated and sent to the address memory read-write management module; and sending the head pointer H as a read address IM to an address memory read-write management module.
2. Free address write request generation module 1432
The free address write request generation module 1432 is connected to the free address pre-write FIFO module 1412, the R _ FIFO write request generation module 1422, the write request N generation module 124, and the free address queue pointer management module 1433, and is configured to receive R _ FIFO required data from the R _ FIFO write request generation module 1422, receive W _ FIFO read data and a W _ FIFO read data valid signal from the free address pre-processing module 141 (from the free address pre-write FIFO module 1412 therein), receive a write request N from the write data processing unit 120 (from the write request N generation module 124 therein), generate a write request P according to the received data, send the write request P to the free address queue pointer management module, and send the W _ FIFO read data to the free address queue pointer management module as write data P.
The method for generating the write request P can comprise the following steps: and if the data read by the W _ FIFO is valid and the R _ FIFO needs data invalidation, the write request N is invalid, and a write request P is generated and sent to the free address queue pointer management module. And sending the data read out by the W _ FIFO to the free address queue pointer management module as write data P.
3) Free address queue pointer management module 1433
The idle address queue pointer management module 1433 is configured to receive the write request P and the write data P from the idle address write request generation module 1432, receive the read request IM from the idle address registration module 1431, receive the read data IM from the address memory read-write management module 144, use the write request P as the write request IM, use the write data P as the write data IM, use the tail pointer of the idle address queue as the write address IM, send the write address IM to the address memory read-write management module 144, generate a head pointer H and a head pointer valid H signal according to the read request IM, the write request P, the write data P, and the read data IM, and send the head pointer H and the head pointer valid H signal to the idle address registration module 1431.
Specifically, the idle address queue pointer management module 1433 is connected to the idle address registration module 1431, the idle address write request generation module 1432, and the address memory read-write management module 144. The write request P and the write data P are received from the free address write request generation module 1432, the read request IM is received from the free address registration module 1431, and the read data IM is received from the address memory read-write management module 144. The free address queue pointer management module 1433 initializes the free address queue stored in the address memory 145 before the buffer operates normally. The free address queue head pointer is initialized to 4 and the other free addresses are written to the address memory 145 in sequence. During initialization, a write request IM is always valid, write data IM is j, write address IM is j-1, where j is 4, 5, 6, …, N-1, N is the depth of the address memory, and a free address queue tail pointer is initialized to N-1. After the writing is finished, the writing request IM becomes invalid, the initialization is finished, and the buffer area can work normally. In normal operation, the free address queue pointer management module 1433 sends the write request P as a write request IM, the write data P as a write data IM, and the tail pointer of the free address queue as a write address IM to the address memory read-write management module 144. After initialization is completed, a head pointer valid H signal is valid, and when the free address queue head pointer is equal to the free address queue tail pointer and the read request IM is valid, the head pointer valid H signal is invalid; otherwise, when the free address queue head pointer is equal to the free address queue tail pointer and the write request P is valid, the head pointer valid H signal becomes valid. When the head pointer valid H signal is valid, if the free address queue head pointer is equal to the free address queue tail pointer, and the read request IM and the write request P are both valid, assigning the value of the write data P to the free address queue head pointer; otherwise, giving the read data IM to the free address queue head pointer. When the head pointer valid H signal is invalid, if the write request P is valid, the value of the write data P is assigned to the free address queue head pointer. And if the write request P is effective, assigning the write data P to a tail pointer of the free address queue. Sending the free address queue head pointer as a head pointer H to the free address register module 1431; the head pointer valid H is sent to the free address registration module 1431.
Four, address memory read-write management module 144
The address memory read-write management module 144 is connected to the queue head pointer memory 151, the read request N generation module 132, the free address register module 1431, the free address queue pointer management module 1433, the write request N generation module 124, the queue tail pointer memory 152, and the address memory 145. Receiving the write request IM, the write address IM, and the write data IM from the free address queue pointer management module 1433, receiving the read request IM and the read address IM from the free address register module 1431, receiving the write request N from the write request N generation module 124, receiving the write address N from the queue tail pointer memory 152, regarding the read data I as the write data N, receiving the read request N from the read request N generation module 132, receiving the read address N from the queue head pointer memory 151, and receiving the read data M from the address memory 145. The write request IM or the write request N is sent as a write request M to the address memory 145. If the write request IM is valid, the write address IM is used as a write address M, the write data IM is used as write data M, and the write data M is sent to an address memory; otherwise, the write address N is set as the write address M, and the write data N is sent to the address memory 145 as the write data M. The read request IM or the read request N is sent to the address memory 145 as a read request M, and the read data M is sent to the free address queue pointer management module 1433 as read data IM. If the read request IM is valid, the read address IM is sent to the address memory 145 as read address M, and the read data M is sent to the queue head pointer memory 151 as read data N.
Five, address memory 145
The address memory 145 is connected to the address memory read-write management module 144, and receives the write request M, the write address M, the write data M, the read request M, and the read address M from the address memory read-write management module 144. And if the write request M is valid, writing the write data M into the storage unit corresponding to the write address M. If the read request M is valid, the data is read from the memory cell corresponding to the read address M as read data M, and sent to the address memory read-write management module 144.
Here, the embodiment of the present invention implements that the memories of one read port and one write port support two write requests and two read requests by using the idle address pre-write and idle address pre-read modes through the configured address access management unit.
The embodiment of the invention also provides a switch, and the switch is provided with the dynamic shared buffer memory.
For the detailed implementation details and beneficial effects of the switch, reference may be made to the embodiment related to the dynamic shared cache, and details are not repeated herein.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
Those skilled in the art will understand that all or part of the steps in the method according to the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In addition, any combination of various different implementation manners of the embodiments of the present invention is also possible, and the embodiments of the present invention should be considered as disclosed in the embodiments of the present invention as long as the combination does not depart from the spirit of the embodiments of the present invention.

Claims (10)

1. A dynamically shared buffer memory, comprising:
the data input port is used for writing message description information containing a write request A and written data;
write data processing unitThe data input port is connected with the data input port and is used for extracting a queue number W from the written data and using the written data as write data D which is used for writing the data according to the write request A, the queue number W and a queue length L corresponding to the queue number WWGenerating a write request IH, generating a write request N when the write request A is valid and the write request IH is invalid, and generating a read request I, a write request T and a write request D according to the write request A;
a read data processing unit for inputting a read request B and a read queue number, taking the read queue number as a queue number R, sending the queue number R to the write data processing unit to assist in judging the validity of the write request IH, and for judging the queue length L corresponding to the queue number R when the read request B is validRIf the number of the read requests is larger than 1, generating a read request N;
the address access management unit is used for receiving the read request I and the write request N from the write data processing unit, receiving the read request B and the read request N from the read data processing unit, taking the read request B as the write request I, and outputting read data N, read data D and/or read data I according to addresses corresponding to the requests;
a queue management unit comprising a queue head pointer memory, a queue tail pointer memory, and a queue length memory, for:
receiving a queue number W, a write request T and a write request IH from the write data processing unit, taking the queue number W as a read address, a write address IH, a read address T and a write address T, receiving a queue number R as a read address H from the read data processing unit, and receiving a read request B as a write request OH;
reading data from the queue tail pointer memory according to a read address T as read data T, sending the read data T to the address access management unit as a write address N of next data, and storing the read data I output by the address access management unit as write data T at a position corresponding to the write address T in the queue tail pointer memory when a write request T is valid;
according to the write request IH, writing the read data I output by the address access management unit as write data IH into a position corresponding to a write address IH in the queue head pointer memory, reading data from a position corresponding to a read address H in the queue head pointer memory as read data H, sending the read data H to the address access management unit as write data I of a released free address and a read address N of an address where next data is read, receiving the read data N from the address access management unit as write data OH, and writing the write data OH into a position corresponding to a write address OH in the queue head pointer memory when the write request OH is valid; and
according to the length L of the write request A, the queue number W, the read request B, the queue number R and the queue number WWAnd queue length L of queue number RRGenerating a write request IL, a write address IL and write data IL or generating a write request OL, a write address OL and write data OL, and sending the write request OL, the write address OL and the write data OL to the queue length memory, so that the queue length memory writes the write data IL and/or the write data OL according to the effectiveness of the write request IL and the write request OL;
a data buffer for receiving a write request D and write data D from the write data processing unit, receiving read data I from the address access management unit, and regarding the read data I as a write address D, and storing the write data D in a memory cell corresponding to the write address D in the data buffer when the write request D is valid, for receiving a read request B as a read request D from the read data processing unit, receiving read data H as a read address D from the queue head pointer memory, and reading data from the data buffer as read data D according to the read address D when the read request D is valid, and sending the read data D to a data output port; and
and a data output port for outputting the read data D.
2. The dynamically shared buffer memory of claim 1, wherein the write data processing unit comprises:
a queue number W identification module, configured to extract a queue number W according to the written data, and send the queue number W as a read address of the queue length memory, a write address IH of the queue head pointer memory, and a read address T and a write address T of the queue tail pointer memory;
the enqueue request and read idle address module is used for generating a read request I, a write request T and a write request D according to the write request A and taking written data as write data D;
a write request IH generating module for obtaining a write request A from the enqueue request and read idle address module, obtaining a queue number W from the queue number W identification module, and obtaining a queue length L from a position corresponding to the queue number W in the queue length memoryWAnd according to the obtained write request A, the queue number W and the queue length LWGenerating a write request IH; and
and the write request N generation module is used for acquiring a write request A from the enqueue request and read idle address module, acquiring a write request IH from the write request IH generation module, generating a write request N when the write request A is valid and the write request IH is invalid, and sending the write request N to the address access management unit.
3. The dynamically shared buffer memory of claim 2, wherein the read data processing unit comprises:
a read request input port, configured to input a read request B and a read queue number, send the read request B to the queue head pointer memory as a write request OH, send the read request B to the data buffer as a read request D, send the read request B to the address access management unit as a write request I, send the read queue number as a queue number R to the queue length memory as a read address, send the read queue number R to the queue head pointer memory as a read address H and a write address OH, and send the read request B and the queue number R to the write request IH generation module to assist in determining validity of the write request IH; and
a read request N generation module, connected to the read request input port, for receiving a read request B from the read request input port and receiving a queue length L from the queue length memoryRAnd is valid at read request B and queue length LRIf greater than 1, a read request N is generated and willThe read request N is sent to the address access management unit.
4. The dynamic shared buffer memory according to claim 3, wherein the queue management unit comprises:
the queue tail pointer memory is used for receiving a read address T and a write address T from the queue number WID module, reading data from the queue tail pointer memory according to the read address T as read data T, sending the read data T to the address access management unit as a write address N of the next data, and storing the read data I output by the address access management unit as write data T in a position corresponding to the write address T in the queue tail pointer memory when the write requests T received from the enqueue request and read idle address modules are valid;
the queue head pointer memory is used for writing the read data I output by the address access management unit into a position corresponding to a write address IH in the queue head pointer memory as write data IH according to the write request IH received from the write request IH generation module, sending the read data H from the position corresponding to a read address H in the queue head pointer memory to a data buffer as read data H as read address D, sending the read data H to the address access management unit as write data I of a released free address and a read address N of an address where the next data is read, receiving the read data N from the address access management unit as write data OH, and writing the write data OH into the position corresponding to the write address OH in the queue head pointer memory when the write request OH is valid;
a queue length write request generation module for receiving a write request A from the data input port, a queue number W from the queue number W identification module, and a queue length L from the queue length memoryWAnd queue length LRReceiving a read request B and a queue number R from the read request input port, and according to a write request A, a queue number W and a queue length LWQueue length LRA read request B and a queue number R, generating a write requestSolving IL, a write address IL and write data IL or generating a write request OL, a write address OL and write data OL and sending the generated data to the queue length memory;
the queue length memory is used for writing corresponding write data IL and write data OL into corresponding positions in the queue length memory according to the respective write address IL and write address OL according to the validity of the write request IL and the write request OL generated by the queue length write request generation module, and is also used for reading out the corresponding queue length L according to the queue number W and the queue number R respectively acquired from the queue number W identification module and the read request input portWAnd queue length LR。
5. The dynamic shared buffer memory of claim 4, wherein generating the write request IL, the write address IL and the write data IL or generating the write request OL, the write address OL and the write data OL comprises:
if the write request A is valid and the read request B is invalid or the write request A is valid and the read request B is valid but the queue number W is different from the queue number R, generating a write request IL, taking the queue number W as a write address IL, and taking the queue length LWPlus one as write data IL; and
if the read request B is valid and the write request A is invalid, and the queue number W is different from the queue number R, generating a write request OL, taking the queue number R as a write address OL, and taking the queue length L as the write address OLRMinus one as write data OL.
6. The dynamic shared buffer memory according to any one of claims 1 to 5, wherein the address access management unit comprises:
the free address preprocessing module is used for receiving a read request I from the write data processing unit to read a free address at the head of the current FIFO queue as read data I and sending the read data I to the queue head pointer memory, the queue tail pointer memory and the data buffer area, and is also used for taking a read request B received from the read data processing unit as a write request I, writing a released free address read from the queue head pointer memory into the current FIFO queue as write data I, generating W _ FIFO read data according to a W _ FIFO read request and generating a W _ FIFO read data effective signal;
the FIFO processing module is connected with the idle address preprocessing module and used for acquiring a read request I and a write request I, counting an R _ FIFO count value showing the times that the R _ FIFO write request is an effective value according to the read request I, counting a W _ FIFO count value showing the times that the W _ FIFO write request is an effective value according to the write request I, generating an R _ FIFO write request sent to the idle address preprocessing module by combining the read request I, R _ FIFO count value, the data read by the W _ FIFO, a data effective signal read by the W _ FIFO, an idle address R and an idle address R effective signal, and sending the data read by the W _ FIFO or the idle address R as R _ FIFO write data to the idle address preprocessing module; the W _ FIFO read request is sent to the idle address preprocessing module according to the R _ FIFO required data, the effective data signal read out by the W _ FIFO and the write request N;
the free address management module is used for taking the head pointer H as a free address R according to a read request N, the head pointer H, a head pointer effective H signal, data read by the W _ FIFO, a data effective signal read by the W _ FIFO and R _ FIFO required data, generating a free address R effective signal, sending the free address R and the free address R effective signal to the FIFO processing module and generating a read request IM; generating a write request P according to the data read by the write request N, W _ FIFO, the data valid signal read by the W _ FIFO and the R _ FIFO required data, and taking the data read by the W _ FIFO as write data P; the device is also used for taking the write request P as a write request IM, taking the write data P as write data IM, taking the tail pointer of the idle address queue as a write address IM, and generating a head pointer H and a head pointer valid H signal according to the read request IM, the write request P, the write data P and the read data IM;
the address memory read-write management module is used for sending a read data I serving as write data N and a write request IM or a write request N serving as write request M to the address memory, generating write data M according to the received write request IM, write address N and write data N, and generating a read request M, a read address M, read data IM and read data N according to the received read request IM, read request N and read data M; and
and the address memory is used for receiving the write request M, the write address M, the write data M, the read request M and the read address M from the address memory read-write management module, writing the write data M into a storage unit corresponding to the write address M in the address memory when the write request M is valid, and reading data from the storage unit corresponding to the read address M as read data M when the read request M is valid and sending the read data M to the address memory read-write management module.
7. The dynamically shared buffer memory according to claim 6, wherein the free address preprocessing module comprises:
the free address pre-reading FIFO module is used for receiving a read request I from the write data processing unit to read out a free address at the head of the current FIFO queue as read data I and sending the read data I to the queue head pointer memory, the queue tail pointer memory and the data buffer area; and
and the free address pre-writing FIFO module is used for taking the read request B input by the read data processing unit as a write request I, taking the released free address read from the queue head pointer memory as write data I to be written into the current FIFO queue, taking the write data I being written or the data read from the current read address of the current FIFO queue as the data read out by the W _ FIFO according to the W _ FIFO read request, and generating a data valid signal read by the W _ FIFO.
8. The dynamically shared buffer memory according to claim 7, wherein said FIFO processing module comprises:
the R _ FIFO counter is used for receiving a read request I from the write data processing unit and counting an R _ FIFO count value showing the number of times that the R _ FIFO write request is an effective value according to the read request I;
an R _ FIFO write request generation module, configured to receive a read request I from the write data processing unit, receive an R _ FIFO count value from the R _ FIFO counter, receive data read out by the W _ FIFO and a data valid signal read out by the W _ FIFO from the free address pre-write FIFO module, combine a free address R and a free address R valid signal, generate an R _ FIFO write request sent to the free address pre-read FIFO module, and send the data read out by the W _ FIFO or the free address R as R _ FIFO write data to the free address pre-read FIFO module;
a W _ FIFO counter for receiving the read request B from the read data processing unit as a write request I and counting a W _ FIFO count value showing the number of times that the W _ FIFO write request is a valid value according to the write request I; and
and the W _ FIFO read request generation module is used for generating a W _ FIFO read request sent to the free address pre-write FIFO module according to the R _ FIFO required data received from the R _ FIFO write request generation module, the data valid signal read out from the W _ FIFO received from the free address pre-write FIFO module and the write request N received from the write data processing unit.
9. The dynamically shared cache as recited in claim 8, wherein the free address management module comprises:
an idle address register module, configured to receive a read request N from the read data processing unit, receive a head pointer H and a head pointer valid H signal from the idle address queue pointer management module, receive data read by the W _ FIFO and a data valid signal read by the W _ FIFO from the idle address pre-write FIFO module, receive R _ FIFO required data from the R _ FIFO write request generation module, regard the head pointer H as an idle address R according to the received data, generate an idle address R valid signal, send the idle address R and the idle address R valid signal to the R _ FIFO write request generation module, and generate a read request IM according to the received data;
the free address writing request generating module is used for receiving R _ FIFO required data from the R _ FIFO writing request generating module, receiving W _ FIFO read data and W _ FIFO read data valid signals from the free address preprocessing module, receiving a writing request N from a writing data processing unit, generating a writing request P according to the received data, sending the writing request P to the free address queue pointer management module, and sending the W _ FIFO read data as writing data P to the free address queue pointer management module; and
the idle address queue pointer management module is used for receiving a write request P and write data P from the idle address write request generation module, receiving a read request IM from the idle address register module, receiving read data IM from the address memory read-write management module, taking the write request P as the write request IM, taking the write data P as the write data IM, taking the tail pointer of the idle address queue as the write address IM, sending the write address IM to the address memory read-write management module, generating a head pointer H and a head pointer valid H signal according to the read request IM, the write request P, the write data P and the read data IM, and sending the head pointer H and the head pointer valid H signal to the idle address register module.
10. A switch, characterized in that it is provided with a dynamically shared buffer memory according to any of claims 1 to 9.
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