KR20160109733A - Storage apparatus and method for processing a plurality of client data - Google Patents

Abstract

The present invention relates to a storage device and method for processing data of multiple clients. The storage device according to one embodiment of the present invention comprises: a first-stage storage unit for receiving data of multiple clients generated for each burst unit from the multiple clients; a second-stage storage unit transferred with the data of the multiple clients from the first-stage storage unit to store the transferred data in multiple memory banks, which the multiple clients share, for the each burst unit; and a third-stage storage unit transferred with data of each client from the second-stage storage unit to store data of a transaction unit, which is a transfer unit for processing data. The present invention provides an efficient data processing method and device for collecting data for each client and transmitting the same.

Description

TECHNICAL FIELD [0001] The present invention relates to a storage apparatus and method for processing a plurality of client data,

The present invention is directed to a storage device and method for processing a plurality of client data.

In a data processing method requiring processing of a plurality of different types of client data such as a transmitter, a receiver, or a transceiver (or terminal) in a communication system, the amount of data to be transmitted is different for each client, Is also independent. Typically, different client data are stored in separate memories, and the size of memory per client data is also not uniform. Therefore, if the memory configuration specialized for each client is used in the existing data processing method, the memory area efficiency is degraded by some small size memory. In addition, the memory configuration specialized for each client has a problem that the memory size increases in proportion to the amount of data to be processed at one time in the processor, and even if the amount of data for each client varies depending on the operation scenario, (Reallocation) can not be performed, and it is burdensome to design and allocate a larger memory as a whole.

The present invention provides an efficient data processing method and apparatus for collecting and transmitting client-specific data.

The present invention also provides a data storage method and apparatus for efficiently processing client-specific data using memories having a multi-stage structure.

According to an embodiment of the present invention, a storage apparatus for processing a plurality of client data includes a first storage unit for receiving and storing the plurality of client data generated in units of bursts from a plurality of clients, A second stage storage unit for receiving the plurality of client data from the storage unit and storing the plurality of client data in the plurality of memory banks shared by the plurality of clients in units of bursts; And a third storage unit for storing data in a transaction unit, which is a transfer unit for data processing.

According to another aspect of the present invention, there is provided a storage method for processing a plurality of client data, the method comprising: receiving the plurality of client data generated in units of bursts from a plurality of clients and storing the received data in a memory for each client; Storing the plurality of client data received from the memory in units of bursts in a plurality of memory banks shared by the plurality of clients, receiving the client data stored in the plurality of memory banks, And storing data in a transaction unit, which is a transfer unit for data processing.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A shows an example of a configuration of a data storage device for processing a plurality of client data in a communication system,
1B illustrates another configuration of a data storage device that processes a plurality of client data in a communication system,
2 is a diagram illustrating a pattern of data generated in a specific client,
3 illustrates an exemplary configuration of a data storage device for processing a plurality of client data in a communication system according to an embodiment of the present invention;
4 is a diagram illustrating a configuration example of a burst memory operating as a second stage storage unit in the storage apparatus according to an embodiment of the present invention;
5 is a diagram illustrating an example of an access pattern of a burst memory in a storage device according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating an area of a memory required per bit according to an embodiment of the present invention,
7 is a diagram illustrating an example of an interface between a client and a data transfer unit in a storage apparatus according to an embodiment of the present invention;
FIG. 8 is a timing diagram illustrating a client data transfer operation in a storage device according to an embodiment of the present invention;
9 is a diagram illustrating an example of client data stored in a destination memory in a storage device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

A transmitter, a receiver or a transceiver (hereinafter referred to as a " terminal ") in a communication system includes one or a plurality of processors operating on a software basis, one or a plurality of hardware blocks (or functional blocks) . ≪ / RTI > Here, information is exchanged between the hardware block and the processor (or subsystem of the processor). Some of the resultant values obtained according to the data operation in the hardware block may be transmitted to the processor and processed, and data to be transmitted to the processor may have various kinds of data depending on the characteristics of the hardware block. These various kinds of data must be transmitted to the processor within a reasonable time after being generated periodically or aperiodically in the hardware block. Assuming a communication system, the various kinds of data are transmitted / received for calibration Data such as an inphase / Q (quadrature) data, a processing result of a cell searcher, a channel estimation value of a receiver, an adaptive filter weight of an equalizer, For example.

When a plurality of hardware blocks operating at the same time are referred to as a plurality of clients, and different data generated in a plurality of hardware blocks are assumed to be different client data, in order to facilitate understanding of the present invention, Existing data storage devices and data processing methods for processing different client data will be described first. Hereinafter, embodiments of the present invention will be described on the assumption of a storage device used in a terminal of a communication system. However, a storage device according to an embodiment of the present invention may be used in various systems in which data collection, The same can be applied.

1A shows an example of a configuration of a data storage device that processes a plurality of client data in a communication system, wherein the configuration of FIG. 1A shows a data storage device using a slave bus interface structure.

1A, a plurality of client data (C ₀ to C _{N -1} ) generated from a plurality of clients (clients 0 to N-1) 110 are stored in a storage unit 130 And stored in the memories 130 ₀ to 130 _N-1 . The memories (memories 0 to N-1) 130 ₀ to 130 _N-1 of the client correspond to the bit widths (W ₀ to W _{N -1} ) of the data (C ₀ to C _{N -1} ) And have different memory sizes depending on the amount of data generated per unit time. A processor not shown may be output from the client-specific memories 130 ₀ to 130 _N-1 and read data multiplexed by the multiplexer 135 through the slave bus interface 150. In FIG. 1B, reference numeral S1 denotes memory selection for reading data from the memories 130 ₀ to 130 _N-1 for each client in the slave bus interface structure.

1B is a diagram showing another configuration example of a data storage device that processes a plurality of client data in a communication system. The configuration of FIG. 1B includes data (DMA) using a DMA (Direct Memory Access) bus interface structure for performing data input / FIG.

Referring to FIG. 1B, a plurality of client data (C ₀ to C _{N -1} ) generated from a plurality of clients (clients 0 to N-1) And stored in the memories 130 ₀ to 130 _N-1 . The memories (memory 0 to N-1) 130 ₀ to 130 _N-1 for each client have different memory sizes according to the amount of different client data (C ₀ to C _{N -1} ). The data output from the client-specific memories 1300 to 130N-1 and multiplexed by the multiplexer 135 is transferred to the processor core 180 such as a DSP (Digital Signal Processor) or a CPU (Central Processing Unit) The transfer module 160, and the RAM (Random Access Memory) 170 to the processor core 180.

In the above arrangement of the storage unit 130, a plurality of client-specific-memory _{(130 0 ~ 130 N-1} ) in Fig. 1a and 1b, for example, flip-flops (flip-flop) or a SRAM (Static Random Access Memory) On-chip memory, such as a flash memory, which has the following problems. Specifically, one client memory in the client-specific memories 130 ₀ to 130 _N-1 stores the amount of data (hereinafter "one transaction") to be processed in software at one time. Since the flip-flop as the client memory has the largest memory area per bit and the SRAM also has a relatively large area per bit, the client memory has a large silicon area of the memory due to the transaction size being processed. .

The SRAM used as the client memory includes a cell matrix for storing actual information as well as a control logic for decoding an address for reading and writing data and designating a cell for accessing . The size of the cell matrix increases in proportion to the number of bits of data to be stored, but the control logic gently increases in size compared to the cell matrix, so that the smaller the memory capacity, the larger the area of silicon occupied per bit The area efficiency of the memory is lowered. In the conventional implementation of the client memory, the amount of client-specific data differs depending on the amount of data per client. When a small amount of memory is used for a part of the client memory, the overall area efficiency decreases due to an increase in silicon area per bit. In addition, since each client memory is fixedly mapped to a specific client, the client memory can not be efficiently reallocated and used according to the operation status. In the conventional implementation of the client memory, when the amount of data generated by each hardware block (i.e., client) varies in various operation scenarios, each client memory must be created based on the largest amount of data required in all operation scenarios Considering this, the overall required memory area is increased.

In an embodiment of the present invention, a storage device using a multi-stage memory capable of further reducing the area of a memory using a traffic characteristic of client data transmitted from a plurality of clients is proposed. The client-specific data may be understood as different kinds of data processed in a terminal or the like using the storage device.

Also, in the storage device according to the embodiment of the present invention, most of the data to be processed by the processor at one time is stored in a memory having a relatively low cost, and the memory having a high implementation cost is stored at a time For rapid storage of the < / RTI > In addition, the storage device is proposed to reduce the use of a small capacity memory having a low area efficiency of the memory, and to use a memory of a predetermined capacity or more, thereby improving the overall area efficiency of the memory.

In addition, the storage device according to the embodiment of the present invention can easily change an allocation amount of memory for each client through a configuration register when the memory requirement of each client is changed according to various operation scenarios.

2 is a diagram illustrating a pattern of data generated in a specific client. Referring to FIG. 2, the client generates interrupts 205 and 207 after transmitting data, and requests processing from the processor. The processor collects data corresponding to one transaction 201, 203 at a time, but the actual data is divided into several small bursts 211, 213. Therefore, in the embodiment of the present invention, one burst is stored in the intermediate memory first for each client, and the entire data of one transaction is stored in a destination memory having a relatively small implementation cost. The destination memory may use an external DRAM (Dynamic Random Access Memory) or an SRAM, and the size of the individual instance is large, thereby improving the area efficiency. In an embodiment of the present invention, the burst can be understood as a unit of production of data generated, for example, in one client, and the transaction can be a unit of data processed (e.g., delivered to software etc.) Can be understood as a transmission unit.

FIG. 3 is a block diagram illustrating an example of a data storage apparatus for processing a plurality of client data in a communication system according to an embodiment of the present invention. FIG. 3 is a block diagram of a storage apparatus implemented with a multi- FIG.

3 stores different types of client data (C ₀ to C _N-1 ) generated from a plurality of clients (clients 0 to N-1) 310 corresponding to a plurality of hardware blocks in the terminal And a data mover 330 for temporarily storing the received data and outputting the data to the destination memory 350. The data transmission unit 330 and the first end storage unit which is implemented as per-client FIF0 (First In First Out) memories (331), a plurality of client data transferred from the first-stage storage section 1 (C ₀ ~ C storing _{N -1)} as a single unit of each burst, and includes a next burst of data is stored the second stage is implemented burst data stored before being input to the burst memory 335 for outputting to a destination memory 350. The destination memory 350 can be an external memory or the like, and is used as a third-stage storage unit. Accordingly, the storage device configured by the multi-stage memories for processing a plurality of different types of client data according to the embodiment of the present invention can be implemented by including the first to third storage sections. Here, the data amounts of the different kinds of client data (C ₀ to C _{N -1} ) input to the FIFO memories 331 may be different. Meanwhile, in the above-described embodiment, a plurality of client data (C ₀ to C _{N -1} ) transmitted from the first stage storage unit is stored in the burst memory 335 in units of one burst. However, And the present invention is not limited thereto. Accordingly, it is also possible to store client data in the burst memory 335 in units of two or more bursts.

Referring to the specific operation of the data transfer unit 330 in FIG. 3, the first-stage input operation portion stored FIF0 memories 331 is N number of client data different from the N client (310) (C ₀ ~ C _{N -1} ) and stores it in an input FIFO (First Input First Output) memory allocated for each client. Client-specific data stored in the client-specific input FIFO memory is formatted 333 in a predetermined manner and input to and stored in a burst memory 335 operating as the second stage storage unit. When the data width (W ₀ to W _{N -1} ) of each client data is smaller than the memory bank width (W _B ) in the burst memory 335, the format 333 collects input data, according to the size of the memory bank width W _B is to use memory efficiently.

In the embodiment of the present invention, the burst memory 335 stores one burst for each client, so that the amount of data to be stored in the burst memory 335 is greatly reduced as compared with the case where the entire transaction is stored. Since the burst memory 335 uses a relatively expensive memory, in the embodiment of the present invention, data is stored in units of bursts, which is a unit for generating data in the client. When one burst is stored in the burst memory 335, the burst memory 335 outputs the previously stored burst to the third-stage storage unit before the next burst occurs and the existing data is overwritten. Each client data stored in the burst memory 335, which is the second-stage storage unit, is transferred to the third-stage storage unit during the processing time between adjacent bursts. In addition, since the third-stage storage unit uses a relatively low-cost memory, in the embodiment of the present invention, the third-stage storage unit is a unit for transferring data processed through the processor (for example, a unit of transmission of data transferred to the software through the processor) Data can be stored. The software can process the data of the transaction unit at a time.

According to the embodiment of the present invention, when the client data is stored in the high-cost burst memory, only the burst volume generated once can be stored without storing the entire data of the transaction volume, which is a unit of one transmission, It is possible to improve the use efficiency of the memory for cost by transmitting the burst data to the low-cost memory and storing the burst data during the processing time.

If the processing time interval between the current burst and the next burst is so short that the processing time to transfer data to the third-stage storage unit is insufficient, the corresponding client data (i.e., data with insufficient processing time) The shortage of the processing time can be solved by double buffering in which two or more burst quantities are stored.

The storage device of FIG. 3 may also include a configuration register R1 that stores settings for processing each client data. The configuration register Rl may for example be a configuration register 331 in which each client data is associated with a start address occupied in the burst memory 335 and an address of the destination memory 350 where each client data is ultimately stored, de-formatting (337) method, etc., can be stored. 3, the output FIFO 336 temporarily stores data read from the burst memory 335 and each client data output from the output FIFO 336 is transferred to the DMA controller eXDMAC ) 339 to the third stage storage unit. In addition, each client can request interrupt generation in a specific burst using the control information delivered to the data transfer unit 330, and an interrupt generation unit I1 for processing the interrupt can be included in the storage device of FIG. 3 have.

In FIG. 3, the third stage storage unit, which is the destination memory 350, is an address space accessible from the processor as a final destination to which data is transferred. For example, the third stage storage unit may use a large-capacity data memory of a DRAM outside a chip or a specific processor in a chip, and receives data through an eXDMAC 339 that is a DMA controller. The third stage storage unit stores one transaction for each data processing unit in the processor. The implementation cost per bit is relatively low as compared with the first stage storage unit or the second stage storage unit, so the overall implementation cost is reduced. If processing of the processor is delayed and the data of the next transaction is transferred before the processing of one transaction is finished, if there is a possibility that data is overwritten, it is necessary to secure space for storing two or more transactions in the third- It is also possible to perform buffering. And the operation of the storage device including the first-stage to third-stage storage may be controlled through a control unit (not shown).

4 is a diagram illustrating a configuration example of a burst memory operating from the storage device to the second stage storage unit according to an embodiment of the present invention.

4, the burst memory 335 includes an input crossbar 3351, a plurality of memory banks (banks 1 to M-1) 3353, and an output multiplexer 3355 . The N input ports are connected to the M memory banks 3353 via an input crossbar 3351, where N < M. That is, the number of memory banks is larger than the number of input ports. In this embodiment, each memory bank has a width of, for example, W _B bits. Each input port is controlled to be connected to a particular memory bank every moment. The output port selects and outputs one of the M memory banks at each moment.

In this embodiment, any area of the burst memory 335 can be allocated to the client, and the start address of each client in the memory banks 3353 can be set in the configuration register Rl. This setting can be changed during operation of the terminal and reset according to the operation scenario. Thus, the overall size of the burst memory 335 can be designed on the basis of an operational scenario in which the sum of the burst amounts of all clients is the maximum, and in other operational scenarios, The memory 335 can be redistributed. In this embodiment, the allocation method of the burst memory 335 can reduce the required area of the memory while securing the space of the memory with the maximum burst size for each client.

5 is a diagram illustrating an example of an access pattern of a burst memory in a storage apparatus according to an embodiment of the present invention.

Referring to FIG. 5, for example, when a client accesses the burst memory 335, it sequentially accesses all the memory banks 3353 in a pattern of striping in the horizontal direction. In this case, since one client accesses a specific memory bank only once every M cycles, if two or more clients in the input crossbar 3351 are scheduled to not access two memory banks in one instant, At the same time, the memory banks can be accessed. Since reading data stored in the burst memory 335 is performed in units of one client, the number N of clients that write data in the burst memory 335 must be smaller than the number M of memory banks.

Table 1 below shows an example of allocation of the input crossbar 3351 according to the client according to the present embodiment. This is an example of allocation of memory banks over time for the case where the number of clients is 8 will be.

<Table 1>

If 8 consecutive clock cycles are defined as eight time slots as shown in Table 1 and are allocated in a round-robin manner, scheduling without collision is possible simply. In this case, when a specific client attempts to start data transmission, it may take up to 7 clocks to wait until the allocated time slot. Therefore, an input buffer (i.e., input FIFO in FIG. The input FIFO for each client, which is the first stage storage unit, stores irregularly generated data from each client without loss and transmits it to the burst memory 335 in succession.

FIG. 6 is a diagram illustrating an area (unit: gate count) of a memory required per bit according to the size of a memory according to an embodiment of the present invention. Here, one gate (gate) represents the area of a NAND gate having two inputs.

Referring to FIG. 6, the memory area of the smallest memory (Width 4, Depth 32) is 3.83 gates / bit. As the memory size increases, the memory area decreases and the memory area converges to 0.20 gate / bit . In the example of FIG. 6, the memory area is different by a maximum of 19 times among memories having different sizes. Also, if the memory size is larger than a certain size, the memory area sharply decreases from 0.2 to 0.3 gate / bit. Therefore, it can be seen that it is more advantageous in terms of memory area reduction to form a memory bank so that the memory size is uniform rather than the memory banks are implemented with various memory size distributions as in the example of FIGS. 1A and 1B. Therefore, in this embodiment, the memory sizes of the memory banks are configured uniformly regardless of the amount of data generated for each client.

In the embodiment of the present invention, each client can transmit additional information in addition to the client data to be transmitted to the destination memory 350.

7 is a diagram illustrating an example of an interface between a client and a data transfer unit in a storage apparatus according to an embodiment of the present invention.

7 shows an example in which control information (ControlInfo) and an interrupt request signal (InterruptReq) are transmitted from the client i (310) to the data transfer unit (330) in addition to Wi-bit client data (ClientData) via an interface.

Table 2 below shows an example of the control information.

<Table 2>

FIG. 8 is a timing diagram for explaining an operation of transmitting a client data in a storage device according to an embodiment of the present invention. FIG. 8 is a timing diagram illustrating an example of transmitting client data using the control information in Table 2. For example, when ContorlInfo [1: 0] in Table 2 is "10", ContorlInf [1] is "1" and ContorlInf [0] is "0" in FIG.

8, reference numeral 801 denotes a clock, reference numerals 803 and 805 denote control information, reference numeral 807 denotes an interrupt request signal, and reference numeral 809 denotes client data. The client i 310 keeps the control information (ControlInfo) at "00" in the standby state. Client i 310 transmits control information ControlInfo [0] 803, for example, "1" at the start of the first transmission and transmits a head address to start storing data in destination memory 350. [ The client i 310 transmits the control information ControlInfo [1] 805 to "1" to inform the data transfer unit 330 that the client data 809 is valid when the client data 809 is transmitted. Client i 310 transmits control information "11" after one burst transmission is completed. Upon receiving the control information "11 &quot;, the data transfer unit 330 activates the eXDMAC 339, which is the DMA controller, to start data transfer to the destination memory 350 after confirming the end of the burst. When the client i 310 transmits an interrupt request signal (InterruptReq) 807 at the end of a specific burst, the data transfer unit 330 generates an interrupt and transmits the interrupt request signal And notifies the client that the data transfer is complete. Other reference numerals denote T _{end to start} means the time between one burst and the next burst.

9 is a diagram illustrating an example of client data stored in a destination memory in a storage device according to an embodiment of the present invention.

Referring to FIG. 9, two base addresses BA0 and BA1 can be designated for each client in the setting register R1 (see FIG. 3). If the two basic addresses are different, the destination memory 350 is double Buffering can be performed. Actually, each burst stores data from a base address plus a head address (HA0, HA1, ...) transmitted by each client. At this time, the data storage unit 350 stores the additional information May be stored to facilitate processing of the data by the processor. In Fig. 9, "n + 1" represents a transaction number. The transaction number is used to check whether data of a new transaction has been transferred without using an interrupt. It is assumed that the transaction number uses a value incremented by 1 each time an interrupt is generated for each client. The processor may determine whether or not the transfer of all the data is completed by checking whether the transaction number is updated instead of performing the interrupt processing, thereby shortening the processing time.

The storage device using multi-stage memories (i.e., hierarchical memories) according to the embodiment of the present invention is implemented by including sequentially connected first to third storage units. The first stage storage unit may be implemented as FIFO memories using a small flip-flop or memory for storing data of each client operating independently. By using the first stage storage unit, it is possible to store the data without losing the waiting time until the recording can be started in the second stage storage unit.

The second stage storage unit may be implemented as a burst memory including a plurality of memory banks that can be shared by a plurality of clients in order to reduce one or more bursts generated intensively for each client, . The plurality of memory banks may have a uniform memory size to reduce a memory area, simultaneously read client data transmitted from the first storage unit and simultaneously record the same on the plurality of memory banks, The collision can be prevented when transmitting the stored data. In addition, the second stage storage unit may dynamically change the memory allocation for each client by changing the location and data amount of client-specific data in the burst memory to a software setting (for example, through a setting register). By using the configuration of the second stage storage unit, the area of the memory can be reduced. It is also possible to use the traffic characteristics of data generated by each client to increase the area efficiency of the storage device.

The third-stage storage unit stores data of a transaction unit, which is a processing unit of the processor, and may store data of one or two or more transactions for each client. The third-stage storage unit may use an external memory or an on-chip memory having a relatively low implementation cost (for example, a memory built in the processor), and may store data of each client in a specific location of the destination memory It is possible to perform double buffering using two or more base addresses. The additional information may be automatically transmitted to a specific location of the third storage unit to facilitate data processing by the processor. The additional information may be various information that aids in processing other data such as the transaction number.

According to the embodiment of the present invention described above, in a communication system in which data generated by a plurality of hardware blocks must be transmitted to a specific memory, a storage device using shared multi-stage memories capable of efficiently processing data of all clients And methods.

In addition, according to the embodiments of the present invention described above, a memory access method can be provided in a storage device using multi-stage memories. By using such a structure, the use of a small memory can be reduced, The area efficiency of the memory can be improved. It is also possible to efficiently reallocate the amount of memory allocated to each client when the amount of data generated per client is changed according to the operation scenario.

Claims (15)

1. A storage device for processing a plurality of client data,
A first stage storage unit for receiving and storing the plurality of client data generated in units of bursts from a plurality of clients;
A second stage storage unit for receiving the plurality of client data from the first stage storage unit and storing the plurality of client data in the plurality of memory banks shared by the plurality of clients in units of the bursts; And
And a third storage unit for receiving each client data from the second stage storage unit and storing data in a transaction unit which is a transmission unit for data processing.
The method according to claim 1,
Wherein the plurality of clients correspond to a plurality of processors operating independently, and the plurality of client data includes different kinds of data.
The method according to claim 1,
Wherein the first stage storage unit includes a plurality of client-specific memories each storing the plurality of client data.
The method according to claim 1,
Wherein the first stage storage unit stores the plurality of client data until the second stage storage unit can start recording.
The method according to claim 1,
Wherein the plurality of memory banks have a uniform memory size.
The method according to claim 1,
Wherein the plurality of client data is simultaneously written to the plurality of memory banks in burst units.
The method according to claim 1,
Wherein the number of the plurality of memory banks is greater than the number of the plurality of clients.
The method according to claim 1,
Wherein the plurality of client data is stored in the plurality of memory banks and the amount of data can be changed to a software setting.
9. The method of claim 8,
Wherein the second stage storage unit includes a setting register,
Wherein the software setting can be changed using the setting register.
The method according to claim 1,
Wherein client-specific memory allocation for the plurality of memory banks is dynamically variable.
The method according to claim 1,
Wherein the third stage storage unit uses an on-chip memory included in an external memory or a processor.
The method according to claim 1,
Wherein the third stage storage unit performs double buffering using a plurality of base addresses when storing each client data.
The method according to claim 1,
And the additional information transferred to the specific address of the third stage storage unit is used for data processing of the processor.
The method according to claim 1,
Wherein each of the client data stored in the second stage storage unit is transferred to the third stage storage unit during a processing time between adjacent bursts.
CLAIMS 1. A storage method for processing a plurality of client data,
Receiving the plurality of client data generated in units of bursts from a plurality of clients and storing the received data in a client-specific memory;
Receiving the plurality of client data from the client-specific memory and storing the plurality of client data in the plurality of memory banks shared by the plurality of clients in units of the burst; And
And storing data of a transaction unit, which is a transfer unit for data processing, in the destination memory, receiving the client data stored in the plurality of memory banks.

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