CN104407992A - Four-port memory based on dual-port RA (register array) - Google Patents
Four-port memory based on dual-port RA (register array) Download PDFInfo
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- CN104407992A CN104407992A CN201410782798.XA CN201410782798A CN104407992A CN 104407992 A CN104407992 A CN 104407992A CN 201410782798 A CN201410782798 A CN 201410782798A CN 104407992 A CN104407992 A CN 104407992A
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Abstract
The invention discloses a four-port memory based on a dual-port RA (register array), and aims to solve the problem that a large chip area is occupied when an address buffer is realized through a register bank or a four-port RA at present. The technical scheme is that a free address counter, a free address write control module, a free address read control module, a memory read request generating module, a memory write request generating module, a first AND gate, a second AND gate, a free address exchange register read-write control module, a free address exchange register, a free address selection module, a memory write control module, a memory read control module and a memory output data selection module are added to the dual-port RA. With adoption of the scheme, the four-port memory is realized by the dual-port RA, the occupied area of the memory can be saved when the four-port memory is taken as the address buffer in a multi-VC (virtual channel) dynamic share buffer, so that the area of a chip is reduced, and wiring congestion is avoided.
Description
Technical field
The present invention relates to the address buffer in supercomputer interconnection network switch, especially based on four port stores of dual ported register Array Construction.
Background technology
Supercomputer interconnection network switch generally adopts input buffer structure, and along with the increase of switch ports themselves number, switch adopts multilevel interchange frame, the input port that each input port and every one-level exchange needs buffer cache message, causes the number of buffer zone in switch sharply to increase.In order to reduce the chip area that buffer zone takies, the power dissipation overhead that the storer that reduction realizes buffer zone brings, adopts dynamic assignment shared buffer management method in switch, improve buffer utilization, reduces buffer depth.
Need in dynamic assignment shared buffer to safeguard multiple data queue, can according to virtual channel (Virtual Channel, or the number of output port setting data queue VC), therefore, the management method of dynamic assignment shared buffer is divided into the buffer management method of queuing up according to output port and the buffer management method of queuing up according to VC, and two kinds of methods do not have essential distinction in realization.In describing below, suppose that data in buffer zone are according to No. VC queuing, namely the data of same VC are kept in same virtual data queue, and this buffer zone is called the dynamic shared buffer of many VC.In order to improve link utilization, the physical link in interconnection network is divided into multiple virtual channel.In the input block of switch, arrange and the same number of virtual data queue of VC, the data of identical VC are organized as virtual linked list, and access mode is first in first out (First In First Out, FIFO).In some switch, in order to eliminate head obstructing problem, arrange the virtual queue identical with switch output port number, the data outputting to same output port are stored in a queue, are organized as chained list mode, and access mode is also FIFO.
The data of preserving in buffer zone are the packet slice of regular length, are called flit.Message is split as flit at end node, then transmits in a network.The flit number that the message of different length comprises is different.The storage unit width of buffer zone is identical with flit width, and each storage unit preserves a flit.The degree of depth of buffer zone is determined jointly by the link transmission delay between upper level transmitting terminal and buffer zone and link bandwidth.
Note VC number is N (N is positive integer), and the typical dynamic shared buffer of many VC as described in Figure 1, has 1 data-in port, N number of read request input port (i.e. VC
1to VC
nread request input port), N number of data-out port (i.e. VC
1to VC
ndata-out port), by VC identification module, N number of read/write address administration module (i.e. VC
1to VC
nread/write address administration module), the first write request and write address select module, the first read request and read that address selection module, the second write request and write address select module, the second read request selects module, the 3rd write request and write data selecting module, third reading request selecting module, data buffer, address buffer, third reading write address administration module form.
Data-in port is connected with VC identification module, data buffer, and the data serial of N number of VC is input to VC identification module and data buffer.VC
i(1≤i≤N) read request input port and VC
iread/write address administration module is connected, by VC
iread request is sent to VC
iread/write address administration module.
VC
idata-out port is connected with data buffer, by the VC read from data buffer
idata be sent to other processing logic of switch.
VC identification module and data-in port, VC
1to VC
nread/write address administration module is connected, and from the VC i of these data of extracting data of data-in port input, generates VC
iwrite request, is sent to VC
iread/write address administration module.
VC
iread/write address administration module and VC identification module, VC
iread request input port, the first write request and write address select module, the first read request and read that address selection module, the second write request select module with write address, the second read request selects module, the 3rd write request with write data selecting module, third reading request selecting module is connected with address buffer, receives VC from VC identification module
iwrite request, generates the VC reading idle address
ithird reading request, is sent to third reading request selecting module; VC
iread/write address administration module receives the current idle address read from third reading write address administration module, and this address is saved as VC
iwrite address, generates VC
ifirst write request, by VC
ifirst write request and write address are sent to the first write request and write address selects module; If VC
idata have been had to be kept in data buffer, VC
iread/write address administration module generates the second write request to address buffer, and by VC
ithe address of previous data, as write address, is sent to the second write request and write address selects module, then, previous data address is updated to the current idle address of reading.VC
iread/write address administration module is from VC
iread request input port receives VC
iread request as the first read request, by VC
iaddress is read as first in the address at first data place, the first read request and first is read address and is sent to the first read request and reads address selection module; If VC
ithe data number be kept in data buffer is greater than 1, generates the second read request, is sent to the second read request and selects module; Generate VC
i3rd write request, by VC
ifirst read address as writing data, send to the 3rd write request and write data selecting module.VC
iread/write address administration module receives the next data address read from address buffer, by VC
ithe address at first data place is updated to this address.
First write request and write address select module and VC
1to VC
nread/write address administration module is connected with data buffer, serial received VC
ithe VC that read/write address administration module sends
ifirst write request and write address, select effective write request and write address thereof to generate the first write request and the first write address respectively, send to data buffer.
First read request with read address selection module and VC
1to VC
nread/write address administration module, data buffer are connected with address buffer, serial received VC
ithe VC that read/write address administration module sends
ifirst read request with read address, select effective read request and read address to generate the first read request and first respectively and read address, the two is sent to data buffer, only reads address by first and send to address buffer.
Data buffer is generally the dual-port static random access storage device SRAM (StaticRandom Access Memory) with independently reading-writing port, selects module, the first read request and read address selection module, VC with data-in port, the first write request and write address
1to VC
ndata-out port is connected, and receives the first write request and the first write address that the first write request and write address select module to send, receives data and be written into the storage space that the first write address points to from data-in port; Data buffer receives the first read request and reads the first read request and first that address selection module sends and read address, from the first storage space output data reading to point to address to VC
1to VC
ndata-out port.
Second write request and write address select module and VC
1to VC
nread/write address administration module, address buffer are connected, serial received VC
ithe second write request that read/write address administration module sends and write address, select effective write request and write address, generate the second write request and the second write address, be sent to address buffer.
Second read request selects module and VC
1to VC
nread/write address administration module, address buffer are connected, serial received VC
ithe second read request that read/write address administration module sends, selects effective read request to be sent to address buffer as the second read request.3rd write request with write data selecting module and VC
1to VC
nread/write address administration module, third reading write address administration module, address buffer are connected, serial received VC
ithe 3rd write request that read/write address administration module sends with write data, select effective write request and write data, generate the idle address of the 3rd write request and write, be sent to third reading write address administration module and address buffer.
Third reading request selecting module and VC
1to VC
nread/write address administration module, third reading write address administration module, address buffer are connected, serial received VC
ithe third reading request that read/write address administration module sends, selects effective read request to be sent to third reading write address administration module and address buffer as third reading request.
Third reading write address administration module and the 3rd write request with write data selecting module, third reading request selecting module, address buffer, VC
1to VC
nread/write address administration module is connected, and receives the 3rd write request and writes the 3rd write request that data selecting module sends, using the idle address rear of queue pointer of maintenance as the 3rd write address, being sent to address buffer.Then, the tail pointer of idle address queue is updated to the idle address of write; Third reading write address administration module receives the third reading request that third reading request selecting module sends, and the head pointer of idle address queue is sent to VC as current idle address
1to VC
nread/write address administration module, and address buffer; Meanwhile, using the head pointer of idle address queue as third reading address, be sent to address buffer, read next idle address, upgrade the head pointer of idle address queue with this idle address.
Address buffer is generally have independently two Parasites Fauna or the four port RA (RegisterArray reading two write ports, register array), with the first read request with read that address selection module, the second write request and write address select module, the second read request selects module, VC
1to VC
nread/write address administration module, the second write request with write data selecting module, the second read request selects module, the 3rd write request and write data selecting module, third reading request selecting module, third reading write address administration module, VC
1to VC
nread/write address administration module is connected, receive the second write request and the second write address that the second write request and write address select module to send, by the 3rd write request with write current idle address that data selecting module sends and be written to the space, address buffer that the second write address points to; Receive the second read request that the second read request selects module to send, receive the first read request and read address with read that address selection module sends first, read next data address from the first space, address buffer of reading address sensing; Receive the 3rd write request and the idle address writing the 3rd write request that data selecting module sends and write, receive the 3rd write address that third reading write address administration module sends, the idle address of write is written to the space, address buffer of the 3rd write address sensing; Receive the third reading request that third reading request selecting module sends, receive the third reading address that third reading write address administration module sends, the space, address buffer pointed to from third reading address reads next idle address.
Logically see, the address buffer of the above-mentioned dynamic shared buffer of many VC needs to provide four access ports, and (these four access ports are not physical port, but logic port), comprise two write ports and two read ports, be denoted as the first write port, the second write port, the first read port and the second read port respectively.Composition graphs 1, corresponds in physics realization, and the input signal of the first write port comprises: the second write request, the second write address, current idle address, when the second write request is effective, current idle address is write the space, address buffer that the second write address points to.The input signal of the first read port comprises: the second read request, and first reads address, and output signal comprises: next data address, if the second read request is effective, reads next data address from the first space, address buffer of reading to point to address.The input signal of the second write port comprises: the idle address of the 3rd write request, the 3rd write address, write, if the 3rd write request is effective, the idle address of write is write the space, address buffer that the 3rd write address points to.The input signal of the second read port comprises: third reading request, third reading address, and output signal comprises: next idle address, if third reading request is effective, the space, address buffer pointed to from third reading address reads next idle address.
Four access ports of address buffer may be simultaneously accessed, therefore, address buffer needs employing four port store to realize, if realize four port stores with Parasites Fauna, four access ports can be supported easily, but Parasites Fauna will occupy larger chip area, causes routing congestion.If realize four port stores with four port RA, can facilitating chip realize in rear end wiring, but to be the twice of dual-port RA many for the area that four port RA of identical capacity take, area occupied is larger.If but realized address buffer with dual-port RA, would receive two read requests and two write requests, by the access conflict of the access conflict and write port that there will be read port simultaneously.Therefore, the address buffer that dual-port RA realizes in the dynamic shared buffer of many VC cannot directly be adopted.
Summary of the invention
The technical problem to be solved in the present invention is that to use Parasites Fauna or four port RA to realize address buffer four port store chip occupying area in prior art large, dual-port RA receives two read requests simultaneously and access conflict appears in the access of two write requests, directly cannot adopt the address buffer that dual-port RA realizes in the dynamic shared buffer of many VC.In order to the area reducing the dynamic shared buffer of many VC takies, the present invention proposes a kind of four port stores realized based on dual-port RA, for realizing the address buffer of the dynamic shared buffer of many VC.
For solving above-mentioned concrete technical problems, technical scheme of the present invention is:
The present invention is based on four port stores that adopt producer to provide in the dynamic shared buffer of many VC in four port stores and background technology that dual-port RA realizes as the difference of address buffer is, four port stores of background technology adopt Parasites Fauna or four port RA directly to realize, without the need to designing added logic; The present invention adopts dual-port RA, increases the function that following steering logic realizes four port access simultaneously: idle address counter, idle address write control module, idle address read control module, read request generation module, memory write request generation module, first and door, second and control module write by door, idle address exchange register Read-write Catrol module, idle address exchange register, idle address selection module, storer, storer read control module, storer export data selecting module.First with door, second and door be two inputs and door.Identical with the address buffer of background technology, the address buffer adopting the present invention to realize equally provides 4 access ports: the first write port, the second write port, the first read port and the second read port.The input signal of the first write port comprises: the second write request, the second write address, current idle address, when the second write request is effective, current idle address is write the space, address buffer that the second write address points to.The input signal of the first read port comprises: the second read request, and first reads address, and output signal comprises: next data address, if the second read request is effective, reads next data address from the first space, address buffer of reading to point to address.The input signal of the second write port comprises: the idle address of the 3rd write request, the 3rd write address, write, if the 3rd write request is effective, the idle address of write is write the space, address buffer that the 3rd write address points to.The input signal of the second read port comprises: third reading request, third reading address, and output signal comprises: next idle address, if third reading request is effective, the space, address buffer pointed to from third reading address reads next idle address.
Idle address counter is write control module be connected with the 3rd written request signal line, third reading request signal line, idle address read control module, idle address; Receive the 3rd write request and third reading request, if the 3rd write request is effective, third reading request is invalid, and idle address counter value is added one by idle address counter; If the 3rd write request is invalid, third reading request is effective, and idle address counter value is subtracted one by idle address counter; Otherwise idle address counter value remains unchanged; Idle address read control module and idle address is sent to by idle address counter value to write control module.
Idle address read control module is connected with door with the 3rd written request signal line, idle address counter, read request generation module, second; Receive the 3rd write request and idle address counter value, if the 3rd write request is effective or idle address counter value is 1, generates the 5th and read enablely to be sent to read request generation module and second and door; Otherwise, do not generate the 5th read enable.
Idle address is write control module and is connected with door with third reading request signal line, idle address counter, memory write request generation module, first; Receive third reading request and idle address counter value, if idle address counter value be 0 or third reading request effective, generate the 5th and write and be enablely sent to memory write request generation module and first and door; Otherwise, do not generate the 5th write enable.
First write control module with Men Yu tri-written request signal line, idle address, idle address exchange register Read-write Catrol module, idle address exchange register be connected; Writing control module reception the 5th from idle address writes enable, do logical and with the 3rd write request to operate, namely the 5th write enable and the 3rd write request simultaneously effectively time, generate the 5th write request, the 5th write request is sent to idle address exchange register Read-write Catrol module and idle address exchange register.
Second is connected with third reading request, idle address read control module, idle address exchange register Read-write Catrol module, idle address exchange register, idle address selection module with door; Read enable from idle address read control module reception the 5th, read the 5th enablely to do logical and with third reading request and operate, namely the 5th read enable and third reading request simultaneously effectively time, generate the 5th read request, the 5th read request is sent to idle address exchange register Read-write Catrol module, idle address exchange register and idle address selection module.
Idle address exchange register Read-write Catrol module is connected with door, idle address exchange register with door, second with first; Receive the 5th write request from first with door, receive the 5th read request from second with door, if the 5th write request is effective, the 5th write address is added one; If the 5th read request is effective, read cyclic address change by the 5th; The 5th write address and the 5th generated is read address and is sent to idle address exchange register.
Idle address exchange register is made up of two registers, is connected with door, second with the idle address signal line, first of write with door, idle address exchange register Read-write Catrol module, idle address selection module; The 5th write request is received with door from first, the 5th write address is received from idle address exchange register Read-write Catrol module, if the 5th write request is effective, the idle address of the write obtained by the idle address signal line from write is saved in the idle address exchange register of the 5th write address sensing; The 5th read request is received with door from second, receive the 5th from idle address exchange register Read-write Catrol module and read address, if the 5th read request is effective, read idle address as the first idle address from the 5th idle address exchange register reading to point to address, the first idle address is sent to idle address selection module.
Read request generation module is with third reading request signal line, idle address read control module, storer read control module, storer exports data selecting module, idle address selection module is connected, read enable from idle address read control module reception the 5th, if third reading request is effective, 5th read enable invalid, generate the 4th read request, the 4th read request is sent to storer read control module, storer exports data selecting module and idle address selection module; Otherwise, do not generate the 4th read request.
Memory write request generation module writes control module with the 3rd written request signal line, idle address, storer is write control module and is connected, writing control module reception the 5th from idle address writes enable, if the 3rd write request is effective, 5th write enable invalid, generate the 4th write request, the 4th write request is sent to storer and writes control module; Otherwise, do not generate the 4th write request.
Storer is write control module and is connected with the second written request signal line, the second writing address signal line, current idle address signal line, the 3rd writing address signal line, the idle address signal line of write, memory write request generation module, dual-port RA, receives the 4th write request from memory write request generation module; If the second write request is effective, 4th write request is invalid, generates memory write request, the second write address is assigned to storer write address, current idle address is assigned to storer and writes data, memory write request, storer write address, storer are write data and be sent to dual-port RA; If the second write request is invalid, 4th write request is effective, generates memory write request, the 3rd write address is assigned to storer write address, the idle address of write is assigned to storer and writes data, memory write request, storer write address, storer are write data and be sent to dual-port RA; Otherwise, do not generate memory write request.
Address signal line read by storer read control module and the second reading request signal line, first, third reading address signal line, read request generation module, dual-port RA are connected, the 4th read request is received from read request generation module, if the second read request is effective, 4th read request is invalid, generate read request, read address to be assigned to storer to read address by first, read request, storer are read address and be sent to dual-port RA; If the second read request is invalid, the 4th read request is effective, generates read request, third reading address is assigned to storer and reads address, read request, storer are read address and be sent to dual-port RA; Otherwise, do not generate read request.
Dual-port RA has a read port and a write port, writes control module, storer read control module, storer export data selecting module and be connected with storer; Dual-port RA writes control module reception memorizer write request from storer, data write by storer write address, storer, if memory write request is effective, storer is write data and is written to the dual-port RA storage space that storer write address points to; Address is read from storer read control module reception memorizer read request, storer, if read request is effective, the dual-port RA storage space sense data reading to point to address from storer exports data as storer, is sent to storer and exports data selecting module.
Storer exports data selecting module and is connected with the second reading request signal line, read request generation module, dual-port RA, idle address selection module, next data address signal line; Receive the 4th read request from read request generation module, export data from dual-port RA reception memorizer, if the second read request is effective, the 4th read request is invalid, storer is exported data and is assigned to next data address; If the second read request is invalid, the 4th read request is effective, storer is exported data and is assigned to the second idle address, the second idle address is sent to idle address selection module.
It is idle that address selection module exports data selecting module with read request generation module, storer, idle address exchange register, second is connected with door, next idle address signal line; Receive the 4th read request from read request generation module, export data selecting module from storer and receive the second idle address, receive the 5th read request from second with door, receive the first idle address from idle address exchange register; If the 4th read request is effective, the 5th read request is invalid, and the second idle address is assigned to next idle address; If the 4th read request is invalid, the 5th read request is effective, and the first idle address is assigned to next idle address.
Adopt the present invention can reach following technique effect:
In outside annexation of the present invention and connection signal and Fig. 1 the outside annexation of address buffer and connection signal just the same, idle address counter is increased by means of only the periphery at dual-port RA, control module is write in idle address, idle address read control module, read request generation module, memory write request generation module, first and door, second and door, idle address exchange register Read-write Catrol module, idle address exchange register, idle address selection module, control module write by storer, storer read control module, storer exports these 13 functional modules of data selecting module, and (these functional modules are simple combinational logic, area occupied is very little), dual-port RA is just made to have the port access characteristic of four port stores, eliminate the access conflict that dual-port RA can only provide two access ports to bring.Adopt four port RA with direct or directly adopt Parasites Fauna to realize compared with the port store of address buffer four, memory chip area occupied can be saved in the address buffer adopting the present invention to realize, thus reduces chip area, avoids routing congestion.
Accompanying drawing explanation
Fig. 1 is the many VC dynamic shared buffer overall construction drawing described in background technology.
Fig. 2 is the address buffer four port store structural drawing realized based on dual-port RA.
Embodiment:
Fig. 2 is the address buffer four port store structural drawing realized based on dual-port RA.The present invention increases the function that following steering logic realizes four port access on the basis of dual-port RA: idle address counter, control module is write in idle address, idle address read control module, read request generation module, memory write request generation module, first and door, second and door, idle address exchange register Read-write Catrol module, idle address exchange register, idle address selection module, control module write by storer, storer read control module, dual-port RA, storer exports data selecting module.Identical with the address buffer of background technology, the address buffer adopting the present invention to realize equally provides 4 access ports: the first write port, the second write port, the first read port and the second read port.The input signal of the first write port comprises: the second write request, the second write address, current idle address, when the second write request is effective, current idle address is write the space, address buffer that the second write address points to.The input signal of the first read port comprises: the second read request, and first reads address, and output signal comprises: next data address, if the second read request is effective, reads next data address from the first space, address buffer of reading to point to address.The input signal of the second write port comprises: the idle address of the 3rd write request, the 3rd write address, write, if the 3rd write request is effective, the idle address of write is write the space, address buffer that the 3rd write address points to.The input signal of the second read port comprises: third reading request, third reading address, and output signal comprises: next idle address, if third reading request is effective, the space, address buffer pointed to from third reading address reads next idle address.The signal of four access ports is just the same with background technology.
Idle address counter is write control module be connected with the 3rd written request signal line, third reading request signal line, idle address read control module, idle address; Receive the 3rd write request and third reading request, if the 3rd write request is effective, third reading request is invalid, and idle address counter value is added one by idle address counter; If the 3rd write request is invalid, third reading request is effective, and idle address counter value is subtracted one by idle address counter; Otherwise idle address counter value remains unchanged; Idle address read control module and idle address is sent to by idle address counter value to write control module.
Idle address read control module is connected with door with the 3rd written request signal line, idle address counter, read request generation module, second; Receive the 3rd write request and idle address counter value, if the 3rd write request is effective or idle address counter value is 1, generates the 5th and read enablely to be sent to read request generation module and second and door; Otherwise, do not generate the 5th read enable.
Idle address is write control module and is connected with door with third reading request signal line, idle address counter, memory write request generation module, first; Receive third reading request and idle address counter value, if idle address counter value be 0 or third reading request effective, generate the 5th and write and be enablely sent to memory write request generation module and first and door; Otherwise, do not generate the 5th write enable.
First write control module with Men Yu tri-written request signal line, idle address, idle address exchange register Read-write Catrol module, idle address exchange register be connected; Writing control module reception the 5th from idle address writes enable, do logical and with the 3rd write request to operate, namely the 5th write enable and the 3rd write request simultaneously effectively time, generate the 5th write request, the 5th write request is sent to idle address exchange register Read-write Catrol module and idle address exchange register.
Second is connected with third reading request, idle address read control module, idle address exchange register Read-write Catrol module, idle address exchange register, idle address selection module with door; Read enable from idle address read control module reception the 5th, read the 5th enablely to do logical and with third reading request and operate, namely the 5th read enable and third reading request simultaneously effectively time, generate the 5th read request, the 5th read request is sent to idle address exchange register Read-write Catrol module, idle address exchange register and idle address selection module.
Idle address exchange register Read-write Catrol module is connected with door, idle address exchange register with door, second with first; Receive the 5th write request from first with door, receive the 5th read request from second with door, if the 5th write request is effective, the 5th write address is added one; If the 5th read request is effective, read cyclic address change by the 5th; The 5th write address and the 5th generated is read address and is sent to idle address exchange register.
Idle address exchange register is made up of two registers, is connected with door, second with the idle address signal line, first of write with door, idle address exchange register Read-write Catrol module, idle address selection module; The 5th write request is received with door from first, the 5th write address is received from idle address exchange register Read-write Catrol module, if the 5th write request is effective, the idle address of the write obtained by the idle address signal line from write is saved in the idle address exchange register of the 5th write address sensing; The 5th read request is received with door from second, receive the 5th from idle address exchange register Read-write Catrol module and read address, if the 5th read request is effective, read idle address as the first idle address from the 5th idle address exchange register reading to point to address, the first idle address is sent to idle address selection module.
Read request generation module is with third reading request signal line, idle address read control module, storer read control module, storer exports data selecting module, idle address selection module is connected, read enable from idle address read control module reception the 5th, if third reading request is effective, 5th read enable invalid, generate the 4th read request, the 4th read request is sent to storer read control module, storer exports data selecting module and idle address selection module; Otherwise, do not generate the 4th read request.
Memory write request generation module writes control module with the 3rd written request signal line, idle address, storer is write control module and is connected, writing control module reception the 5th from idle address writes enable, if the 3rd write request is effective, 5th write enable invalid, generate the 4th write request, the 4th write request is sent to storer and writes control module; Otherwise, do not generate the 4th write request.
Storer is write control module and is connected with the second written request signal line, the second writing address signal line, current idle address signal line, the 3rd writing address signal line, the idle address signal line of write, memory write request generation module, dual-port RA, receives the 4th write request from memory write request generation module; If the second write request is effective, 4th write request is invalid, generates memory write request, the second write address is assigned to storer write address, current idle address is assigned to storer and writes data, memory write request, storer write address, storer are write data and be sent to dual-port RA; If the second write request is invalid, 4th write request is effective, generates memory write request, the 3rd write address is assigned to storer write address, the idle address of write is assigned to storer and writes data, memory write request, storer write address, storer are write data and be sent to dual-port RA; Otherwise, do not generate memory write request.
Address signal line read by storer read control module and the second reading request signal line, first, third reading address signal line, read request generation module, dual-port RA are connected, the 4th read request is received from read request generation module, if the second read request is effective, 4th read request is invalid, generate read request, read address to be assigned to storer to read address by first, read request, storer are read address and be sent to dual-port RA; If the second read request is invalid, the 4th read request is effective, generates read request, third reading address is assigned to storer and reads address, read request, storer are read address and be sent to dual-port RA; Otherwise, do not generate read request.
Dual-port RA has a read port and a write port, writes control module, storer read control module, storer export data selecting module and be connected with storer; Dual-port RA writes control module reception memorizer write request from storer, data write by storer write address, storer, if memory write request is effective, storer is write data and is written to the dual-port RA storage space that storer write address points to; Address is read from storer read control module reception memorizer read request, storer, if read request is effective, the dual-port RA storage space sense data reading to point to address from storer exports data as storer, is sent to storer and exports data selecting module.
Storer exports data selecting module and is connected with the second reading request signal line, read request generation module, dual-port RA, idle address selection module, next data address signal line; Receive the 4th read request from read request generation module, export data from dual-port RA reception memorizer, if the second read request is effective, the 4th read request is invalid, storer is exported data and is assigned to next data address; If the second read request is invalid, the 4th read request is effective, storer is exported data and is assigned to the second idle address, the second idle address is sent to idle address selection module.
It is idle that address selection module exports data selecting module with read request generation module, storer, idle address exchange register, second is connected with door, next idle address signal line; Receive the 4th read request from read request generation module, export data selecting module from storer and receive the second idle address, receive the 5th read request from second with door, receive the first idle address from idle address exchange register; If the 4th read request is effective, the 5th read request is invalid, and the second idle address is assigned to next idle address; If the 4th read request is invalid, the 5th read request is effective, and the first idle address is assigned to next idle address.
Claims (2)
1., based on four port stores of dual ported register array, the address buffer adopting four port stores based on dual ported register array to realize provides 4 access ports: the first write port, the second write port, the first read port and the second read port, the input signal of the first write port comprises: the second write request, the second write address, current idle address, when the second write request is effective, current idle address is write the space, address buffer that the second write address points to, the input signal of the first read port comprises: the second read request, and first reads address, and output signal comprises: next data address, if the second read request is effective, reads next data address from the first space, address buffer of reading to point to address, the input signal of the second write port comprises: the idle address of the 3rd write request, the 3rd write address, write, if the 3rd write request is effective, the idle address of write is write the space, address buffer that the 3rd write address points to, the input signal of the second read port comprises: third reading request, third reading address, and output signal comprises: next idle address, if third reading request is effective, the space, address buffer pointed to from third reading address reads next idle address, it is characterized in that based on four port stores of dual ported register array it being increase idle address counter on dual ported register array and dual-port RA, control module is write in idle address, idle address read control module, read request generation module, memory write request generation module, first and door, second and door, idle address exchange register Read-write Catrol module, idle address exchange register, idle address selection module, control module write by storer, storer read control module, storer exports data selecting module and is formed:
Idle address counter is write control module be connected with the 3rd written request signal line, third reading request signal line, idle address read control module, idle address; Receive the 3rd write request and third reading request, if the 3rd write request is effective, third reading request is invalid, and idle address counter value is added one by idle address counter; If the 3rd write request is invalid, third reading request is effective, and idle address counter value is subtracted one by idle address counter; Otherwise idle address counter value remains unchanged; Idle address read control module and idle address is sent to by idle address counter value to write control module;
Idle address read control module is connected with door with the 3rd written request signal line, idle address counter, read request generation module, second; Receive the 3rd write request and idle address counter value, if the 3rd write request is effective or idle address counter value is 1, generates the 5th and read enablely to be sent to read request generation module and second and door; Otherwise, do not generate the 5th read enable;
Idle address is write control module and is connected with door with third reading request signal line, idle address counter, memory write request generation module, first; Receive third reading request and idle address counter value, if idle address counter value be 0 or third reading request effective, generate the 5th and write and be enablely sent to memory write request generation module and first and door; Otherwise, do not generate the 5th write enable;
First write control module with Men Yu tri-written request signal line, idle address, idle address exchange register Read-write Catrol module, idle address exchange register be connected; Writing control module reception the 5th from idle address writes enable, do logical and with the 3rd write request to operate, namely the 5th write enable and the 3rd write request simultaneously effectively time, generate the 5th write request, the 5th write request is sent to idle address exchange register Read-write Catrol module and idle address exchange register;
Second is connected with third reading request, idle address read control module, idle address exchange register Read-write Catrol module, idle address exchange register, idle address selection module with door; Read enable from idle address read control module reception the 5th, read the 5th enablely to do logical and with third reading request and operate, namely the 5th read enable and third reading request simultaneously effectively time, generate the 5th read request, the 5th read request is sent to idle address exchange register Read-write Catrol module, idle address exchange register and idle address selection module;
Idle address exchange register Read-write Catrol module is connected with door, idle address exchange register with door, second with first; Receive the 5th write request from first with door, receive the 5th read request from second with door, if the 5th write request is effective, the 5th write address is added one; If the 5th read request is effective, read cyclic address change by the 5th; The 5th write address and the 5th generated is read address and is sent to idle address exchange register;
Idle address exchange register is made up of two registers, is connected with door, second with the idle address signal line, first of write with door, idle address exchange register Read-write Catrol module, idle address selection module; The 5th write request is received with door from first, the 5th write address is received from idle address exchange register Read-write Catrol module, if the 5th write request is effective, the idle address of the write obtained by the idle address signal line from write is saved in the idle address exchange register of the 5th write address sensing; The 5th read request is received with door from second, receive the 5th from idle address exchange register Read-write Catrol module and read address, if the 5th read request is effective, read idle address as the first idle address from the 5th idle address exchange register reading to point to address, the first idle address is sent to idle address selection module;
Read request generation module is with third reading request signal line, idle address read control module, storer read control module, storer exports data selecting module, idle address selection module is connected, read enable from idle address read control module reception the 5th, if third reading request is effective, 5th read enable invalid, generate the 4th read request, the 4th read request is sent to storer read control module, storer exports data selecting module and idle address selection module; Otherwise, do not generate the 4th read request;
Memory write request generation module writes control module with the 3rd written request signal line, idle address, storer is write control module and is connected, writing control module reception the 5th from idle address writes enable, if the 3rd write request is effective, 5th write enable invalid, generate the 4th write request, the 4th write request is sent to storer and writes control module; Otherwise, do not generate the 4th write request;
Storer is write control module and is connected with the second written request signal line, the second writing address signal line, current idle address signal line, the 3rd writing address signal line, the idle address signal line of write, memory write request generation module, dual-port RA, receives the 4th write request from memory write request generation module; If the second write request is effective, 4th write request is invalid, generates memory write request, the second write address is assigned to storer write address, current idle address is assigned to storer and writes data, memory write request, storer write address, storer are write data and be sent to dual-port RA; If the second write request is invalid, 4th write request is effective, generates memory write request, the 3rd write address is assigned to storer write address, the idle address of write is assigned to storer and writes data, memory write request, storer write address, storer are write data and be sent to dual-port RA; Otherwise, do not generate memory write request;
Address signal line read by storer read control module and the second reading request signal line, first, third reading address signal line, read request generation module, dual-port RA are connected, the 4th read request is received from read request generation module, if the second read request is effective, 4th read request is invalid, generate read request, read address to be assigned to storer to read address by first, read request, storer are read address and be sent to dual-port RA; If the second read request is invalid, the 4th read request is effective, generates read request, third reading address is assigned to storer and reads address, read request, storer are read address and be sent to dual-port RA; Otherwise, do not generate read request;
Dual-port RA has a read port and a write port, writes control module, storer read control module, storer export data selecting module and be connected with storer; Dual-port RA writes control module reception memorizer write request from storer, data write by storer write address, storer, if memory write request is effective, storer is write data and is written to the dual-port RA storage space that storer write address points to; Address is read from storer read control module reception memorizer read request, storer, if read request is effective, the dual-port RA storage space sense data reading to point to address from storer exports data as storer, is sent to storer and exports data selecting module;
Storer exports data selecting module and is connected with the second reading request signal line, read request generation module, dual-port RA, idle address selection module, next data address signal line; Receive the 4th read request from read request generation module, export data from dual-port RA reception memorizer, if the second read request is effective, the 4th read request is invalid, storer is exported data and is assigned to next data address; If the second read request is invalid, the 4th read request is effective, storer is exported data and is assigned to the second idle address, the second idle address is sent to idle address selection module;
It is idle that address selection module exports data selecting module with read request generation module, storer, idle address exchange register, second is connected with door, next idle address signal line; Receive the 4th read request from read request generation module, export data selecting module from storer and receive the second idle address, receive the 5th read request from second with door, receive the first idle address from idle address exchange register; If the 4th read request is effective, the 5th read request is invalid, and the second idle address is assigned to next idle address; If the 4th read request is invalid, the 5th read request is effective, and the first idle address is assigned to next idle address.
2. as claimed in claim 1 based on four port stores of dual ported register array, it is characterized in that described first with door, second and door be two inputs and door.
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