CN105138467B - Data access device, method and magnetic resonance equipment - Google Patents
Data access device, method and magnetic resonance equipment Download PDFInfo
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- CN105138467B CN105138467B CN201510474615.2A CN201510474615A CN105138467B CN 105138467 B CN105138467 B CN 105138467B CN 201510474615 A CN201510474615 A CN 201510474615A CN 105138467 B CN105138467 B CN 105138467B
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Abstract
The invention provides a data access device, a method and a magnetic resonance device, wherein the device comprises: the storage module is suitable for storing data, responding to a received read command for reading target data, and outputting row data and a feedback signal according to a row address of the target data; the cache module is used for responding to the received read command, caching the column address information of the target data and responding to the feedback signal to output the cached column address information; and the analysis module is suitable for receiving the row of data and the column address information output by the cache module and analyzing the target data from the row of data according to the column address information. The invention can solve the problem that the column address cannot be expressed due to uncertain operation delay of the memory, occupies less resources and is easy to realize.
Description
Technical Field
The present invention relates to memory read operations, and more particularly, to a data access apparatus, a method and a magnetic resonance device.
Background
With the improvement of the performance requirements of electronic products, DDR memories (Double Data Rate ) have been widely used in more and more products due to their advantages of fast transmission speed and large storage capacity. In order to prevent data loss, the DDR memory needs to be refreshed at regular intervals, which may cause the time period of data read/write operation of the DDR memory to be unfixed, that is, the delay of data transmission is random and uncertain.
In applications with complex control, the uncertain data transfer delay of the DDR memory can cause serious problems. For example, when a DDR memory is used for data buffering, some data may be stored in the addresses of row 3 and column 2, however, when the data needs to be read out, because the address line of the DDR memory addresses only the row, after a read request is issued, the DDR memory returns the data of the row 3 address over several working cycles, and the returned data includes the data of all the column addresses in the row 3. Because the delay of the read operation of the DDR memory is not fixed, the column address of the read data cannot be identified by delaying the read address, so that the column address cannot be identified, and the data of the column address expected to be read cannot be resolved from the read data.
The prior art mainly includes the following methods for solving the above problems:
1. only addressing is carried out on row addresses, namely data are written in sequence and read out in sequence, so that the problem caused by uncertain time delay is avoided, but the mode strictly limits the reading and writing of the data to sequential writing and sequential reading, and is not suitable for complex control occasions;
2. the column address is written into a DDR memory together with data, and when the data is read, the data and the column address are simultaneously analyzed, but the method occupies extra DDR memory space, so that resource waste is caused, moreover, a data interface of the DDR is generally fixed, such as 64bit or 32bit, and if a plurality of bits are used for column address identification, the control of peripheral data becomes more complex;
3. the address lines of each column of data are separated to be controlled independently, but the control mode of the DDR memory is complicated due to the mode, the width of a data interface is narrowed, and the DDR memory cannot be flexibly applied to various application occasions, particularly when the DDR memory is controlled by adopting an FPGA.
Disclosure of Invention
The invention aims to provide a data access device, a data access method and magnetic resonance equipment, which can solve the problem that a column address cannot be identified due to uncertain operation delay of a memory.
To solve the above technical problem, the present invention provides a data access apparatus, comprising:
the storage module is suitable for storing data, responding to a received read command for reading target data, and outputting row data and a feedback signal according to a row address of the target data;
the cache module is used for responding to the received read command, caching the column address information of the target data and responding to the feedback signal to output the cached column address information;
and the analysis module is suitable for receiving the row of data and the column address information output by the cache module and analyzing the target data from the row of data according to the column address information.
According to one embodiment of the present invention, the line data includes all data in a line indicated by a line address of the target data.
According to one embodiment of the invention, the storage module is a storage module with uncertain data transmission delay.
According to one embodiment of the invention, the memory module is a DDR memory.
According to one embodiment of the invention, the storage module is a storage module with uncertain data transmission delay.
According to one embodiment of the invention, the buffer module comprises a FIFO memory.
According to an embodiment of the present invention, the data written in the storage module is functional data of a multichannel nmr spectrometer, the row address is used to distinguish different channels, and the column address information is used to distinguish different functional data in each channel.
According to an embodiment of the invention, the apparatus further comprises: and the functional data of each channel of the multichannel nuclear magnetic resonance spectrometer is written into the storage module through the selector.
In order to solve the above problem, the present invention further provides a magnetic resonance apparatus including the data access device according to any one of the above aspects.
In order to solve the above problem, the present invention further provides a data access method, including:
storing data, and writing the data into a preset address of a storage module;
responding to a received read command for reading target data, and outputting row data and a feedback signal according to a row address of the target data;
caching column address information in response to the read command;
outputting the buffered column address information in response to the feedback signal;
and analyzing the target data from the row of data according to the column address information.
According to one embodiment of the present invention, the line data includes all data in a line indicated by a line address of the target data.
According to one embodiment of the invention, the storage module is a storage module with uncertain data transmission delay.
According to one embodiment of the present invention, the column address information is buffered using a FIFO memory in response to the read command; and responding to the feedback signal, and outputting the column address information buffered in the FIFO memory.
According to one embodiment of the invention, the data written into the preset address of the storage module is functional data of the multichannel nuclear magnetic resonance spectrometer, the row address is used for distinguishing different channels, and the column address information is used for distinguishing different functional data in each channel.
According to one embodiment of the invention, functional data of each channel of the multichannel nuclear magnetic resonance spectrometer is written into the storage module through a selector.
Compared with the prior art, the invention has the following advantages:
in the reading operation of the storage module, the data access device of the embodiment of the invention synchronously stores the column address information into the cache module based on the reading command, and synchronously outputs the cached column address based on the feedback signal which shows the effective row data, thereby being capable of analyzing the data of the corresponding column address in the row data read by the storage module by utilizing the read column address information. The scheme of the invention can solve the problem that the column address can not be identified in the reading operation due to unfixed time delay of the storage module (for example, the storage module can comprise a DDR memory), does not need to occupy the internal resources of the storage module and the complex external control logic, is simple to realize, occupies less resources, has lower cost and can be flexibly applied to various complex application scenes.
Drawings
FIG. 1 is a schematic block diagram of a data access device according to a first embodiment of the present invention;
FIG. 2 is a schematic block diagram of a data access device according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a data access method according to a third embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
First embodiment
Referring to fig. 1, the data access apparatus according to the first embodiment includes a data transmission network 11 and a cache module 12. The data transmission network 11 includes a storage module, and the read operation delay of the storage module is not fixed, for example, a DDR storage module or another storage module with a read operation delay not fixed. In addition, the data transmission network 11 may also include various suitable peripheral circuits, such as read and write circuits, for use with the memory modules.
Further, the storage module may store a plurality of data by way of a write operation. For example, the write data, the write address, and the write valid signal may be transmitted to the memory module to cause the memory module to write the write data to the corresponding address. The width of the written data can be consistent with the width of the column data interface of the storage module, that is, the width of the column data interface of the storage module is entirely used for storing data, and other additional data occupying the width of the interface is not used.
In a read operation, the data transfer network 11 receives at least a read command and a row address of target data. For example, a read command may be transmitted to a read enable port of the memory module and a row address may be transmitted to a read address port of the memory module.
The read command is simultaneously transmitted to the buffer module 12. In addition, the cache module 12 also receives column address information. In response to the read command, the cache module 12 caches the column address information. For example, the read command may be transmitted to a write enable port of the cache module 12, and the column address information may be transmitted to a write data port of the cache module 12, such that the column address information is written to the cache module 12. Specifically, the column address information may be a mark representing a column address, or may be the column address itself.
It should be noted that the read command, the row address and the column address information transmitted to the data transmission network 11 and the cache module 12 belong to the same read operation. In other words, when a read operation is performed, a read command and a corresponding row address are transmitted to the data transmission network 11, and the same read command and corresponding column address information are transmitted to the buffer module 12.
In response to the read command, the memory module reads out and outputs the corresponding row data according to the row address after a suitable delay (e.g., several working cycles), and also outputs a feedback signal indicating that the row data is valid. For example, the row data may be output via a read data port of the memory module and the feedback signal may be output via a feedback signal port of the memory module. Generally, the row data output by the memory module includes all the data in the row indicated by the row address.
The feedback signal output by the data transmission network 11 is transmitted to the buffer module 12, for example, may be transmitted to a read enable port of the buffer module 12. In response to the received feedback signal, the buffer module 12 outputs the buffered column address information. Furthermore, the buffer module 12 outputs the buffered column address information in a first-in first-out manner, that is, the first buffered column address information is output first.
The analyzing module 13 receives the row data of the data transmission network 11 and the column address information output by the buffer module 12, and analyzes the target data from the row data according to the column address information.
In short, the buffer module 12 buffers the column address information based on the read command, and outputs the buffered column address information in a first-in first-out manner based on the feedback signal for the parsing module 13 to parse the row data output by the storage module. In this way, no matter how many work cycles the read operation delay of the storage module is, when the storage module outputs the row data, the cache module 12 can synchronously output the column address information corresponding to the current row data. Using the column address information output by the buffer module 12, the parsing module 13 can parse the row data to obtain the corresponding column data, i.e. the data stored in the row address and the column address defined in the read operation.
The buffer module 12 may be implemented by using various suitable circuits and components, and as a preferred example, the buffer module 12 may be implemented by using a FIFO memory. Alternatively, as an alternative example, the buffer module 12 may be implemented by using a Random Access Memory (RAM), and only needs to be configured in a first-in first-out read/write manner through a peripheral circuit of the RAM.
The cache module 12 may be implemented by using existing resources in the FPGA, such as an existing FIFO memory, an RAM, and the like in the FPGA; alternatively, the cache module 12 may be implemented by a dedicated hardware circuit or a hardware chip.
Second embodiment
Referring to fig. 2, the data access device according to the second embodiment includes a memory module 21, a FIFO memory 22, and a selector 23. The data access device can be used for a multichannel nuclear magnetic resonance spectrometer, such as a multichannel nuclear magnetic resonance spectrometer used in a magnetic resonance device, so as to realize the read-write operation of functional data of a plurality of channels. The storage module 21 may be a DDR memory or another storage module with unfixed data transmission delay.
And functional data of each channel of the multichannel nuclear magnetic resonance spectrometer is written into the corresponding address of the storage module through the selector.
Further, in a write operation, a row address may be used to distinguish between different channels and a column address may be used to distinguish between different functional data within each channel. For example, one channel may correspond to a row, and functional data of the same channel is stored in the same row. Thus, the channel number may be used directly or indirectly as a row address and the identification of functions within a channel may be used directly or indirectly as a column address.
In a read operation, a read command and a row address for reading target data are transmitted to the memory module 21. For example, the read command may be transmitted to a read enable port of the memory module 21, and the row address may be transmitted to a read address port of the memory module 21.
In a read operation, a read command is simultaneously transmitted to the FIFO memory 22, for example to a write enable port of the FIFO memory 22, so that the FIFO memory 22 buffers a column address (which corresponds to the functional identification).
In response to the received read command, the memory module 21 reads out the corresponding row data according to the row address after an appropriate delay (e.g., several duty cycles). For example, a row of data is the entire row of functional data 20 indicated by the row address. While outputting the row data, the memory module 21 outputs a feedback signal indicating that the row data is valid, for example, a feedback signal port of the memory module 21 transitions from a logic low level to a logic high level.
The feedback signal output by the memory module 21 is transmitted to the FIFO memory 22, for example, to a read enable port of the FIFO memory 22. In response to the received feedback signal, the FIFO memory 22 outputs the previously stored column address information in a first-in first-out manner.
Based on the column address information output by the FIFO memory 22, a parsing module (not shown in fig. 2) can parse out the functional data 201 desired to be read from the entire row of functional data 20. The functional data 201 is functional data indicated by a row address and a column address of a read operation.
Third embodiment
Referring to fig. 3, the data access method according to the third embodiment includes the steps of:
step S31, storing data, and writing the data into the preset address of the storage module;
step S32, responding to the received read command for reading the target data, and outputting line data and feedback signals according to the line address of the target data;
step S33, in response to the read command, caching column address information;
step S34, outputting the buffered column address information in response to the feedback signal;
and step S35, analyzing the target data from the row data according to the column address information.
As a non-limiting example, the column addresses may be buffered and output in a first-in-first-out manner using various suitable buffer modules, such as, but not limited to, FIFO memories.
For more details of the method, please refer to the related description of the first embodiment and the second embodiment, which is not repeated herein.
In summary, in the technical solution of the present invention, a read command of a storage module is used as a write indication signal of a cache module to perform synchronous cache on a column address corresponding to the read command, a feedback signal of the storage module is used as a read indication signal of the cache module to read the cached column address in a first-in first-out manner, so as to overcome the problem that the delay of the storage module is not fixed, and the method has at least the following advantages:
(1) only a cache module is configured on the basis of a storage module, so that the method is easy to realize, small in occupied resource, easy to control time sequence and low in cost;
(2) the problem that the delay is required to be fixed in a complex occasion is solved, so that the application occasion of the storage module with unfixed read operation delay is wider;
(3) compared with the mode of writing the column addresses into the storage module together in the prior art, the method does not need to occupy the internal resources of the storage module additionally, and improves the utilization rate of the storage module;
(4) compared with the mode of singly controlling the column address line of the memory module in the prior art, the width of a data interface does not need to be changed, so that the application of the memory module is more flexible;
(5) the implementation method is flexible and various, and the cache module can be implemented in an FPGA chip or a special hardware chip;
(6) the column address and the row data are synchronously output, so that the problem caused by unfixed delay length can be solved;
(7) in the reading operation, the delay of the column address in the cache module is the same as the transmission delay of the data in the storage module, and the control is accurate.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (14)
1. A data access device, comprising:
the storage module is suitable for storing data, responding to a received read command for reading target data, and outputting row data and a feedback signal indicating that the row data are effective according to a row address of the target data;
the cache module is used for responding to the received read command, caching the column address information of the target data and responding to the feedback signal to output the cached column address information;
and the analysis module is suitable for receiving the row data and the column address information and analyzing the target data from the row data according to the column address information.
2. The apparatus of claim 1, wherein the row of data comprises all data in a row indicated by a row address of the target data.
3. The apparatus of claim 1, wherein the storage module is a storage module with uncertain data transmission delay.
4. The apparatus of claim 1, wherein the memory module is a DDR memory.
5. The apparatus of claim 1, wherein the buffer module comprises a FIFO memory.
6. The apparatus of claim 1, wherein the data stored in the storage module is functional data of a multichannel nmr spectrometer, the row address is used to distinguish different channels, and the column address information is used to distinguish different functional data in each channel.
7. The apparatus of claim 6, further comprising:
and the functional data of each channel of the multichannel nuclear magnetic resonance spectrometer is written into the storage module through the selector.
8. A magnetic resonance apparatus comprising a data access arrangement as claimed in any one of claims 1 to 7.
9. A method for accessing data, comprising:
storing data, and writing the data into a preset address of a storage module;
responding to a received read command for reading target data, and outputting row data and a feedback signal indicating that the row data is effective according to a row address of the target data;
caching column address information in response to the read command;
outputting the buffered column address information in response to the feedback signal;
and analyzing the target data from the row data according to the column address information.
10. The method of claim 9, wherein the row of data includes all data in a row indicated by a row address of the target data.
11. The method of claim 9, wherein the storage module is a storage module with uncertain data transmission delay.
12. The method of claim 9, wherein in response to the read command, the column address information is buffered using a FIFO memory; and responding to the feedback signal, and outputting the column address information buffered in the FIFO memory.
13. The method of claim 9, wherein the data written into the preset address of the memory module is functional data of a multichannel nmr spectrometer, the row address is used for distinguishing different channels, and the column address information is used for distinguishing different functional data in each channel.
14. The method of claim 13, wherein the functional data of each channel of the multichannel nmr spectrometer is written to the memory module via a selector.
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| CN112035383B (en) * | 2019-06-04 | 2023-01-03 | 北京邮电大学 | Data scheduling method, device and system |
| CN110688083B (en) * | 2019-09-27 | 2023-03-14 | 电子科技大学 | DDR 3-based high-speed data stream long-delay frequency storage forwarding method |
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| CN101162441A (en) * | 2007-11-09 | 2008-04-16 | 华为技术有限公司 | Access apparatus and method for data |
| CN102812518A (en) * | 2010-01-28 | 2012-12-05 | 惠普发展公司，有限责任合伙企业 | Memory access methods and apparatus |
| CN104281545A (en) * | 2013-07-11 | 2015-01-14 | 华为技术有限公司 | Data reading method and data reading equipment |
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| CN101162441A (en) * | 2007-11-09 | 2008-04-16 | 华为技术有限公司 | Access apparatus and method for data |
| CN102812518A (en) * | 2010-01-28 | 2012-12-05 | 惠普发展公司，有限责任合伙企业 | Memory access methods and apparatus |
| CN104281545A (en) * | 2013-07-11 | 2015-01-14 | 华为技术有限公司 | Data reading method and data reading equipment |
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