CN105138467A - Data access apparatus and method and magnetic resonance device - Google Patents
Data access apparatus and method and magnetic resonance device Download PDFInfo
- Publication number
- CN105138467A CN105138467A CN201510474615.2A CN201510474615A CN105138467A CN 105138467 A CN105138467 A CN 105138467A CN 201510474615 A CN201510474615 A CN 201510474615A CN 105138467 A CN105138467 A CN 105138467A
- Authority
- CN
- China
- Prior art keywords
- data
- column address
- row
- address information
- memory module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The present invention provides a data access apparatus and method and a magnetic resonance device. The apparatus comprises: a storage module, adapted to store data, and in response to to a received read command for reading target data, output row data and a feedback signal according to a row address of the target data; a caching module, adapted to in response to the received read command, cache column address information of the target data, and in response to the feedback signal, output the cached column address information;and a parsing module, adapted to receive the row data and the column address information outputted by the cashing module, and parse the target data from the row data according to the column address information. According to the data access apparatus and method and the magnetic resonance device provided by the present invention, the problem of incapability in indicating the column address caused by uncertainty in the operation delay is solved, less resources are occupied, and implementation is easy.
Description
Technical field
The present invention relates to memory read operations, particularly relate to a kind of data access arrangement, method and magnetic resonance equipment.
Background technology
Along with the raising that electronic product performance requires, the advantage that DDR storer (DoubleDataRate, Double Data Rate synchronous DRAM) is fast with its transmission speed and memory capacity is large, is widely used in increasing product.In order to prevent loss of data, DDR storer often needs to refresh at regular intervals, and the time cycle of the data read-write operation of DDR storer can be caused like this not fix, and the time delay of also i.e. data transmission is random, uncertain.
Controlling in complicated application scenario, DDR storer uncertain data transmission delay can cause serious problem.Such as, when using DDR storer to carry out data buffer storage, in the address that a certain data can be arranged stored in the 3rd row the 2nd, but, when needs read these data, because the address wire of DDR storer only carries out addressing, after read request sends to row, the data of the 3rd row address returned through several work periods by DDR storer, and the data returned comprise the data of all column addresss in the 3rd row.Time delay due to the read operation of DDR storer is unfixed, and the method not reading address by time delay, to identify the column address of sense data, causes column address to identify, and just cannot parse the data expecting the column address read from sense data.
In prior art, solution to the problems described above mainly contains following several:
1, only addressing is carried out to row address, also by data sequence write, sequentially read, therefore evaded the problem that uncertain time delay brings, but the read-write of data is strictly restricted to and is sequentially written in, sequentially reads by this mode, merges inapplicable at the controlling filed of complexity;
2, column address is write in DDR storer with data, when reading data, data and column address are parsed simultaneously, but the DDR storage space outside this method meeting occupying volume, cause the waste of resource, and the data-interface of DDR is generally fixing, such as 64bit or 32bit, if some positions to be wherein used for column address mark, the control of peripheral data can be made to become comparatively complicated;
3, the address wire of each column data is separated to control separately, but this mode makes the control mode of DDR storer become comparatively complicated, and data-interface narrowed width can be caused, various application scenario cannot be applicable to flexibly, especially when adopting FPGA to realize the control of DDR storer.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of data access arrangement, method and magnetic resonance equipment, the problem that the uncertain column address caused of operation delay that can solve storer cannot identify.
For solving the problems of the technologies described above, the invention provides a kind of data access arrangement, comprising:
Memory module, is suitable for storing data, in response to the read command of the reading target data received, according to the defeated trip data of the row address of described target data and feedback signal;
Cache module, in response to the described read command received, carries out buffer memory to the column address information of described target data, and in response to described feedback signal, is exported by the described column address information of buffer memory;
Parsing module, is suitable for the column address information receiving the row data and the output of described cache module, and described target data is parsed from the row data according to described column address information.
According to one embodiment of present invention, described row data comprise the total data in the row of the row address instruction of described target data.
According to one embodiment of present invention, described memory module is the uncertain memory module of data transmission delay.
According to one embodiment of present invention, described memory module is DDR storer.
According to one embodiment of present invention, described memory module is the uncertain memory module of data transmission delay.
According to one embodiment of present invention, described cache module comprises FIFO memory.
According to one embodiment of present invention, the data write in described memory module are the performance data of hyperchannel nuclear magnetic resonance spectrometer, and described row address is for distinguishing different passages, and described column address information is for distinguishing performance datas different in each passage.
According to one embodiment of present invention, described device also comprises: selector switch, and the performance data of each passage of described hyperchannel nuclear magnetic resonance spectrometer writes described memory module by described selector switch.
In order to solve the problem, present invention also offers a kind of magnetic resonance equipment, comprise the data access arrangement described in above-mentioned any one.
In order to solve the problem, present invention also offers a kind of data access method, comprising:
Store data, in the address of preset described data write memory module;
In response to the read command of the reading target data received, according to the defeated trip data of the row address of described target data and feedback signal;
In response to described read command, buffer memory is carried out to column address information;
In response to described feedback signal, the described column address information of buffer memory is exported;
According to described column address information, described target data is parsed from the row data.
According to one embodiment of present invention, described row data comprise the total data in the row of the row address instruction of described target data.
According to one embodiment of present invention, described memory module is the uncertain memory module of data transmission delay.
According to one embodiment of present invention, in response to described read command, FIFO memory is used to carry out buffer memory to described column address information; In response to described feedback signal, the column address information of buffer memory in described FIFO memory is exported.
According to one embodiment of present invention, the data in write memory module preset address are the performance data of hyperchannel nuclear magnetic resonance spectrometer, and described row address is for distinguishing different passages, and described column address information is for distinguishing performance datas different in each passage.
According to one embodiment of present invention, the performance data of each passage of described hyperchannel nuclear magnetic resonance spectrometer writes described memory module by selector switch.
Compared with prior art, the present invention has the following advantages:
The data access arrangement of the embodiment of the present invention is in the read operation of memory module, based on read command by column address information stores synchronized in cache module, and based on the effective feedback signal of expression row data, by the column address synchronism output of buffer memory, thus in the row data that the column address information of reading can be utilized memory module to be read the Data Analysis of respective column address is out.Adopt the solution of the present invention, the problem that in the read operation that memory module (such as can comprise DDR storer) fixedly do not cause due to time delay, column address cannot identify can be solved, and the solution of the present invention is without the need to taking the internal resource of memory module, also without the need to the External control logic of complexity, realize simple, take resource few, cost is lower, can flexible Application in the application scenarios of various complexity.
Accompanying drawing explanation
Fig. 1 is the schematic structured flowchart of data access arrangement according to a first embodiment of the present invention;
Fig. 2 is the schematic structured flowchart of data access arrangement according to a second embodiment of the present invention;
Fig. 3 is the schematic flow sheet of data access method according to a third embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
First embodiment
With reference to figure 1, comprise data transmission network 11, cache module 12 according to the data access arrangement of the first embodiment.Wherein, data transmission network 11 comprises memory module, and the time delay of the read operation of this memory module is not fixed, such as, be DDR memory module or read operation time delay other memory modules unfixed.In addition, data transmission network 11 can also comprise with memory module with the use of various suitable peripheral circuit, such as reading and writing circuit.
Furthermore, memory module can store multiple data by the mode of write operation.Such as, by write data, writing address and the effective Signal transmissions of write to memory module, to make memory module, write data can be write corresponding address.Wherein, the width of write data can be consistent with the column data interface width of memory module, and, the column data interface width of memory module, all for storing data, does not take other additional datas of interface width yet.
When carrying out read operation, data transmission network 11 at least receives the row address of read command and target data.Such as, what read command can transfer to memory module reads enable port, and what row address can transfer to memory module reads address port.
This read command transfers to cache module 12 simultaneously.In addition, cache module 12 also receives column address information.In response to this read command, cache module 12 pairs of column address informations carry out buffer memory.Such as, what this read command can transfer to cache module 12 writes enable port, and what column address information can transfer to cache module 12 writes FPDP, makes column address information be written into cache module 12.Particularly, above-mentioned column address information is the mark characterizing column address, also can be column address itself.
It should be noted that, transfer to the read command of data transmission network 11 and cache module 12, row address and column address information and belong to same read operation.In other words, when carrying out a read operation, read command and corresponding row address transfer to data transmission network 11, and same read command and corresponding column address information transfer to cache module 12.
In response to this read command, memory module, after suitable delay (such as several work periods), reads corresponding row data according to row address and exports, and also exports in addition and represents the effective feedback signal of row data.Such as, row data can export via the data reading port of memory module, and feedback signal can export via the feedback signal port of memory module.Typically, the row data that memory module exports contain the total data in the row of row address instruction.
The feedback signal transmission that data transmission network 11 exports is to cache module 12, and what such as can transfer to cache module 12 reads enable port.In response to the feedback signal received, the column address information of buffer memory exports by cache module 12.Further, cache module 12 adopts the mode of first in first out to be exported by the column address information of buffer memory, and namely the column address information of first buffer memory first exports.
Parsing module 13 receives the row data of data transmission network 11 and the column address information of cache module 12 output, and target data is parsed from row data according to column address information.
In brief, cache module 12 carries out buffer memory based on read command to column address information, is exported by the column address information of buffer memory in the mode of first in first out based on feedback signal, for the parsing of the row data that parsing module 13 pairs of memory modules export.Adopt in such a way, no matter the read operation time delay of memory module is how many work periods, and when the defeated trip data of memory module, cache module 12 can the synchronism output column address information corresponding with current row data.Use the column address information that cache module 12 exports, parsing module 13 can be expert in data and be parsed corresponding column data, the data stored in the row address namely limited in read operation, column address.
Cache module 12 can adopt various suitable circuit, element realizes, and as a preferred example, cache module 12 can adopt FIFO memory to realize.Or as the interchangeable example of one, cache module 12 can adopt random access storage device (RAM) to realize, the read-write mode of first in first out only need be configured to by the peripheral circuit of RAM.
Cache module 12 can utilize existing resource in FPGA to realize, such as, in FPGA existing FIFO memory, RAM etc.; Or cache module 12 also can utilize special hardware circuit or hardware chip to realize.
Second embodiment
With reference to figure 2, comprise memory module 21, FIFO memory 22 and selector switch 23 according to the data access arrangement of the second embodiment.This data access arrangement may be used for hyperchannel nuclear magnetic resonance spectrometer, such as, for the hyperchannel nuclear magnetic resonance spectrometer in magnetic resonance equipment, to realize the read-write operation of the performance data of multiple passage.Wherein, memory module 21 can be DDR storer, or data transmission delay other memory modules unfixed.
The performance data of each passage of hyperchannel nuclear magnetic resonance spectrometer is write in address corresponding to described memory module by described selector switch.
Furthermore, in write operation, row address can be used to distinguish different passages, use column address to distinguish performance datas different in each passage.Such as, passage can corresponding a line, and the performance data of same passage is stored in same a line.So, channel number can directly or indirectly as row address, and the Function Identification in passage can directly or indirectly as column address.
In read operation, the read command and the row address that read target data transfer to memory module 21.Such as, what read command can transfer to memory module 21 reads enable port, and what row address transferred to memory module 21 reads address port.
In read operation, read command transfers to FIFO memory 22 simultaneously, and what such as transfer to FIFO memory 22 writes enable port, carries out buffer memory to make FIFO memory 22 pairs of column addresss (this column address corresponds to Function Identification).
In response to the read command received, memory module 21, after suitable time delay (such as several work periods), reads corresponding row data according to row address.Such as, row data are the full line performance data 20 of this row address instruction.While defeated trip data, memory module 21 exports in the lump and represents the effective feedback signal of row data, and the feedback signal port of such as memory module 21 is logic high by logic low saltus step.
The feedback signal transmission that memory module 21 exports is to FIFO memory 22, and what such as transfer to FIFO memory 22 reads enable port.In response to the feedback signal received, the mode of previously stored column address information according to first in first out exports by FIFO memory 22.
According to the column address information that FIFO memory 22 exports, parsing module (not shown in Fig. 2) can expecting that the performance data 201 read parses in full line performance data 20.Performance data 201 is exactly the row address of read operation, the performance data of column address instruction.
3rd embodiment
With reference to figure 3, the data access method according to the 3rd embodiment comprises the steps:
Step S31, stores data, in the address of preset described data write memory module;
Step S32, in response to the read command of the reading target data received, according to the defeated trip data of the row address of described target data and feedback signal;
Step S33, in response to described read command, carries out buffer memory to column address information;
Step S34, in response to described feedback signal, exports the described column address information of buffer memory;
Step S35, parses described target data according to described column address information from described row data.
As a nonrestrictive example, various suitable cache module can be used to carry out buffer memory and output in the mode of first in first out to column address, such as FIFO memory, but be not limited to this.
About more details of the method, refer to the associated description of aforementioned first embodiment and the second embodiment, repeat no more here.
To sum up, the read command of memory module is write indicator signal as cache module by technical scheme of the present invention, synchronization caching is carried out with the column address corresponding to read command, the feedback signal of memory module is read indicator signal as cache module, with the column address adopting the mode of first in first out to read buffer memory, thus overcome the unfixed problem of memory module time delay, the method at least tool has the following advantages:
(1) only need allocating cache module on the basis of memory module, be easy to realize, take resource few, sequential easily controls, and cost is lower;
(2) solve the problem that complicated application requirements time delay is fixing, make the application scenario of the unfixed memory module of read operation time delay more extensive;
(3) compared with column address together being write in prior art the mode of memory module, do not need the extra internal resource taking memory module, improve the utilization factor of memory module;
(4), compared with the mode of the column address conductor of control store module independent with prior art, without the need to changing data-interface width, make the application of memory module more flexible;
(5) implementation method is versatile and flexible, and this cache module both can realize in fpga chip, also can realize with special hardware chip;
(6) column address and row data synchronism output, can solve the unfixing problem caused of delay length;
(7) in read operation, the time delay of column address in cache module is identical with data transmission delay in a storage module, controls precisely.
Although the present invention describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiment is only used to the present invention is described, change or the replacement of various equivalence also can be made when not departing from spirit of the present invention, therefore, as long as all will drop in the scope of claims of the application the change of above-described embodiment, modification in spirit of the present invention.
Claims (14)
1. a data access arrangement, is characterized in that, comprising:
Memory module, is suitable for storing data, in response to the read command of the reading target data received, according to the defeated trip data of the row address of described target data and feedback signal;
Cache module, in response to the described read command received, carries out buffer memory to the column address information of described target data, and in response to described feedback signal, is exported by the described column address information of buffer memory;
Parsing module, is suitable for receiving described row data and described column address information, and described target data is parsed from described row data according to described column address information.
2. device according to claim 1, is characterized in that, described row data comprise the total data in the row of the row address instruction of described target data.
3. device according to claim 1, is characterized in that, described memory module is the uncertain memory module of data transmission delay.
4. device according to claim 1, is characterized in that, described memory module is DDR storer.
5. device according to claim 1, is characterized in that, described cache module comprises FIFO memory.
6. device according to claim 1, it is characterized in that, the data stored in described memory module are the performance data of hyperchannel nuclear magnetic resonance spectrometer, and described row address is for distinguishing different passages, and described column address information is for distinguishing performance datas different in each passage.
7. device according to claim 6, is characterized in that, also comprises:
Selector switch, the performance data of each passage of described hyperchannel nuclear magnetic resonance spectrometer writes described memory module by described selector switch.
8. a magnetic resonance equipment, comprises the data access arrangement as described in any one of claim 1-7.
9. a data access method, is characterized in that, comprising:
Store data, in the address of preset described data write memory module;
In response to the read command of the reading target data received, according to the defeated trip data of the row address of described target data and feedback signal;
In response to described read command, buffer memory is carried out to column address information;
In response to described feedback signal, the described column address information of buffer memory is exported;
According to described column address information, described target data is parsed from described row data.
10. method according to claim 9, is characterized in that, described row data comprise the total data in the row of the row address instruction of described target data.
11. methods according to claim 9, is characterized in that, described memory module is the uncertain memory module of data transmission delay.
12. methods according to claim 9, is characterized in that, in response to described read command, use FIFO memory to carry out buffer memory to described column address information; In response to described feedback signal, the column address information of buffer memory in described FIFO memory is exported.
13. methods according to claim 9, it is characterized in that, data in write memory module preset address are the performance data of hyperchannel nuclear magnetic resonance spectrometer, and described row address is for distinguishing different passages, and described column address information is for distinguishing performance datas different in each passage.
14. methods according to claim 13, is characterized in that, the performance data of each passage of described hyperchannel nuclear magnetic resonance spectrometer writes described memory module by selector switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510474615.2A CN105138467B (en) | 2015-08-05 | 2015-08-05 | Data access device, method and magnetic resonance equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510474615.2A CN105138467B (en) | 2015-08-05 | 2015-08-05 | Data access device, method and magnetic resonance equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105138467A true CN105138467A (en) | 2015-12-09 |
| CN105138467B CN105138467B (en) | 2020-06-02 |
Family
ID=54723821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510474615.2A Active CN105138467B (en) | 2015-08-05 | 2015-08-05 | Data access device, method and magnetic resonance equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105138467B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110688083A (en) * | 2019-09-27 | 2020-01-14 | 电子科技大学 | DDR 3-based high-speed data stream long-delay frequency storage forwarding method |
| CN111324288A (en) * | 2018-12-14 | 2020-06-23 | 北京兆易创新科技股份有限公司 | Memory device |
| CN112035383A (en) * | 2019-06-04 | 2020-12-04 | 北京邮电大学 | Data scheduling method, device and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162441A (en) * | 2007-11-09 | 2008-04-16 | 华为技术有限公司 | Access apparatus and method for data |
| CN102812518A (en) * | 2010-01-28 | 2012-12-05 | 惠普发展公司，有限责任合伙企业 | Memory access methods and apparatus |
| US20140334238A1 (en) * | 2005-08-01 | 2014-11-13 | Rambus Inc. | Low Power Memory Device |
| CN104281545A (en) * | 2013-07-11 | 2015-01-14 | 华为技术有限公司 | Data reading method and data reading equipment |
-
2015
- 2015-08-05 CN CN201510474615.2A patent/CN105138467B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140334238A1 (en) * | 2005-08-01 | 2014-11-13 | Rambus Inc. | Low Power Memory Device |
| CN101162441A (en) * | 2007-11-09 | 2008-04-16 | 华为技术有限公司 | Access apparatus and method for data |
| CN102812518A (en) * | 2010-01-28 | 2012-12-05 | 惠普发展公司，有限责任合伙企业 | Memory access methods and apparatus |
| CN104281545A (en) * | 2013-07-11 | 2015-01-14 | 华为技术有限公司 | Data reading method and data reading equipment |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111324288A (en) * | 2018-12-14 | 2020-06-23 | 北京兆易创新科技股份有限公司 | Memory device |
| CN111324288B (en) * | 2018-12-14 | 2024-02-23 | 兆易创新科技集团股份有限公司 | Memory device |
| CN112035383A (en) * | 2019-06-04 | 2020-12-04 | 北京邮电大学 | Data scheduling method, device and system |
| CN112035383B (en) * | 2019-06-04 | 2023-01-03 | 北京邮电大学 | Data scheduling method, device and system |
| CN110688083A (en) * | 2019-09-27 | 2020-01-14 | 电子科技大学 | DDR 3-based high-speed data stream long-delay frequency storage forwarding method |
| CN110688083B (en) * | 2019-09-27 | 2023-03-14 | 电子科技大学 | DDR 3-based high-speed data stream long-delay frequency storage forwarding method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105138467B (en) | 2020-06-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102684976B (en) | Method, device and system for carrying out data reading and writing on basis of DDR SDRAN (Double Data Rate Synchronous Dynamic Random Access Memory) | |
| CN103714038B (en) | A kind of data processing method and device | |
| CN100426793C (en) | Storage controller and control method | |
| CN101162441B (en) | Access apparatus and method for data | |
| CN108831512A (en) | Load reduced memory module | |
| US20170132166A1 (en) | Chip interconnection method, chip and device | |
| CN106647928A (en) | Abnormal time sequence locating method and apparatus, and mainboard | |
| CN104407983B (en) | Modbus address remapping method used for electric quantity module | |
| CN105138467A (en) | Data access apparatus and method and magnetic resonance device | |
| CN103714036A (en) | I2C multiplexer supporting batch reading verification and control method | |
| US8988951B2 (en) | Method and device for writing block data to an embedded DRAM free of address conflicts | |
| CN103778120A (en) | Global file identification generation method, generation device and corresponding distributed file system | |
| CN206946471U (en) | A kind of shared read-write SDRAM of multichannel circuit arrangement | |
| CN102236622A (en) | Dynamic memory controller and method for increasing bandwidth utilization rate of dynamic memory | |
| CN101599049B (en) | Method for controlling discontinuous physical addresses of DMA access and DMA controller | |
| CN102932265B (en) | Data caching management device and method | |
| CN105550089B (en) | A kind of FC network frame head error in data method for implanting based on digital circuit | |
| CN102789424A (en) | External extended DDR2 (Double Data Rate 2) read-write method on basis of FPGA (Field Programmable Gate Array) and external extended DDR2 particle storage on basis of FPGA | |
| CN105335296B (en) | A kind of data processing method, apparatus and system | |
| CN104407992A (en) | Four-port memory based on dual-port RA (register array) | |
| CN116457751A (en) | Write data access structure and chip | |
| CN107145414B (en) | Method and system for testing distributed object storage | |
| CN109710547A (en) | It is a kind of industry Internet of Things in buffer memory management design and implementation method | |
| CN112685358B (en) | DDR3 grouping read-write method based on FPGA | |
| CN107465569A (en) | A kind of SAS Switch whole machine cabinets crawl node phy error count method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 201807 2258 Chengbei Road, Jiading District, Shanghai Patentee after: Shanghai Lianying Medical Technology Co., Ltd Address before: No. 802258 Jiading Road, Shanghai Patentee before: SHANGHAI UNITED IMAGING HEALTHCARE Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 201807 2258 Chengbei Road, Jiading District, Shanghai Patentee after: Shanghai Lianying Medical Technology Co., Ltd Address before: 201807 2258 Chengbei Road, Jiading District, Shanghai Patentee before: SHANGHAI UNITED IMAGING HEALTHCARE Co.,Ltd. |