CN110164487A - A kind of framework of dynamic RAM - Google Patents
A kind of framework of dynamic RAM Download PDFInfo
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- CN110164487A CN110164487A CN201910275295.6A CN201910275295A CN110164487A CN 110164487 A CN110164487 A CN 110164487A CN 201910275295 A CN201910275295 A CN 201910275295A CN 110164487 A CN110164487 A CN 110164487A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
Abstract
The invention discloses a kind of framework of memory, specifically a kind of low-power consumption double data rate dynamic random access memory (LPDDR).Belong to reservoir designs technical field.Purpose is to provide a kind of framework of low-power consumption double data rate dynamic random access memory (LPDDR).The framework has 8 or more memory block, command block, input/output block, data paths etc..The first sub-block and the second sub-block of each memory block are located in NxN array, and wherein N is an even number, wherein the first sub-block is located at the first half of NxN array, wherein the second sub-block is located at the latter half of NxN array.The first sub-block and the second sub-block of each memory block are located at the symmetrical position of array center position, so that the distance of each memory block of input and output block access is essentially identical, the power consumption of the reading and writing data order of final difference memory block lower, more preferable can be predicted, is more symmetrical.
Description
Technical field
The invention discloses a kind of framework of memory, specifically a kind of low-power consumption double data rate dynamic random is deposited
Access to memory (LPDDR).Belong to reservoir designs technical field.
Background technique
Synchronous Dynamic Random Access Memory (SDRAM) is the dynamic random access memory synchronous with computer system bus
Device (DRAM).The especially sync cap of SDRAM, can waiting system clock signal before responding input control.Clock signal
For driving internal finite state machine to carry out pipeline to incoming order.Data storage areas is divided into several pieces,
Allow the multiple storage access commands of memory single treatment.This allows higher data access speed than asynchronous DRAM memory chip
Rate.
Low-power consumption double data rate (DDR) SDRAM is one kind of DDR SDRAM, also known as mDDR (also referred to as low-power consumption
DDR or LPDDR), it is the communication mark that the American Association EEE electronic equipment engineering committee (JEDEC) formulates towards low-power consumption RAM
Standard, it is famous with low-power consumption and small size, dedicated for intelligent movable mobile phone, tablet computer and other mobile computing devices.
One typical LPDDR includes multiple memory blocks, input/output block, command block.Input/output block can be from specific
Memory block in read data, can also input data into specific memory block.With the increase of memory capacity, each memory block
Distance to input/output block increases, and the power consumption of reading and writing data can be increasing.
Summary of the invention
The object of the present invention is to provide a kind of framves of low-power consumption double data rate dynamic random access memory (LPDDR)
Structure.With 8 or more memory blocks, command block, input/output block, data path etc..First sub-block of each memory block and
Second sub-block is located in NxN array, and wherein N is an even number, wherein the first sub-block is located at the first half of NxN array, wherein
Second sub-block is located at the latter half of NxN array.The first sub-block and the second sub-block of each memory block are located at array center position
Symmetrical position so that the distance of each memory block of input and output block access is essentially identical, final difference memory blocks
The power consumption of reading and writing data order lower, more preferable can be predicted, is more symmetrical.
Low-power consumption dynamic RAM of the invention, feature include a command block, the memory with memory block
Core, at least two reading and writing data channels, one outputs and inputs block:
Each memory block at least has the first sub-block and the second sub-block;Wherein the first sub-block memory block is connected to reading and writing data channel
In first data read/write channel, it is logical that the second sub-block memory block is connected to second reading and writing data in reading and writing data channel
Road；
Reading and writing data channel is in memory core and outputs and inputs and transmits data between block, wherein command block drive command signal
It operates memory core, reading and writing data channel and outputs and inputs block；
First the second sub-block of sub-block is located in NxN array, and wherein N is an even number, wherein the first sub-block is located at the first half of array
Part, wherein the second sub-block is located at the latter half of array；
Command block is arranged along the 1st side of array, is output and input block and is arranged along the 2nd side of array, wherein the 1st side and the 2nd side position
In the relative position of array；
First reading and writing data channel is routed between the first half of array, latter half of the second reading and writing data channel in array
Between be routed；
The first sub-block and the second sub-block of each memory block are located in array, positioned at the symmetrical position of array center position
It sets；
For the data that memory is read, data word has the first range byte, the second range byte, third range byte,
4th range byte, wherein first outputs and inputs block the first range byte of processing, second, which outputs and inputs block, handles the second model
Byte is enclosed, third outputs and inputs block processing third range byte, and the 4th, which outputs and inputs block, handles the 4th range byte.Wherein
First reading and writing data channel, which is connected to first and outputs and inputs block and second, outputs and inputs block, the connection of the second reading and writing data channel
Block and the 4th, which is output and input, to third outputs and inputs block.
For the data for being written to memory, the data of memory are read from block input is output and input by data
Write access is to some memory block.Data can be divided into first group and second group of data, wherein first group of data is stored in some
First sub-block of particular memory block, second group of data are stored in the second sub-block of some particular memory block.
Specific structure of the invention is disclosed in detail below.
A kind of framework of dynamic RAM, including a command block, the memory with memory block, it is characterized in that often
A memory block at least has the first sub-block and the second sub-block；
It further include the channel at least two reading and writing datas (DRW), wherein the first sub-block memory block is connected at least two reading and writing datas
First data read/write channel in channel, and the second sub-block memory block therein are connected at least two reading and writing data channels
Second data read/write channel；
And one output and input (DQ) block, wherein at least two reading and writing data channel passes between memory core and DQ block
Transmission of data, wherein command block drive command signal operation memory core, reading and writing data channel and DQ block.
In the memory block of the memory, first the second sub-block of sub-block is located in NxN array, and wherein N is an idol
Number, wherein the first sub-block is located at the first half of array, wherein the second sub-block is located at the latter half of array.
The command block arranges that wherein DQ block is arranged along the 2nd side of array along the 1st side of array, wherein the 1st side and the
2 sides are located at the opposite of array.
The first reading and writing data channel is routed between the first half of array, and the second reading and writing data channel is in array
Latter half between be routed.
The first sub-block and the second sub-block of the memory block are located in array, the bilateral symmetry positioned at array center position
Position.
The DQ block is arranged along the 2nd side of array.
The wherein data word has the first range byte, the second range byte, third range byte, the 4th range word
Section, wherein the first DQ block handles the first range byte, the 2nd DQ block handles the second range byte, and the 3rd DQ block handles third range
Byte, the 4th DQ block handle the 4th range byte.Wherein the first reading and writing data channel is connected to the first DQ block and the 2nd DQ block, the
Two reading and writing data channels are connected to the 3rd DQ block and the 4th DQ block.
Data are inputted from DQ block, pass through reading and writing data channel to some memory block.Data can be divided into first group and
Two groups of data, wherein first group of data is stored in the first sub-block of some particular memory block, second group of data is stored in some spy
Determine the second sub-block of memory block.
The first sub-block and the second sub-block of each memory block of the invention are located at the symmetrical position of array center position
It sets, so that the distance of each memory block of input and output block access is essentially identical, the reading and writing data order of final difference memory block
Power consumption lower, more preferable can be predicted, is more symmetrical.
Detailed description of the invention
Attached drawing 1 is the memory block diagram that the present invention has storage sub-block.
Attached drawing 2 is the block diagram of the one embodiment for the memory that the present invention has more memory blocks.
Attached drawing 3 is memory one embodiment block diagram with more storage sub-blocks of the invention.
Attached drawing 4 is the additional embodiment block diagram of the memory with more memory blocks of the invention.
Attached drawing 5 is another embodiment of the memory with storage sub-block of the invention.
Attached drawing 6 is the data path of memory of the invention.
Specific embodiment
Embodiment one
In the detailed description of following embodiment, the attached drawing in this document is referred to, these attached drawings can specifically be practiced
Embodiment.
A kind of framework of dynamic RAM, such as DRAM, including the region with multiple memory blocks.These memory blocks
Region is properly termed as storage core.Usual data read/write bus can be individual data reading (DR) line and data write (DW) line,
Or multiplexed data reads and writes (DRW) line.
A kind of framework of dynamic RAM, including a command block, the memory with memory block, it is characterized in that often
A memory block at least has the first sub-block and the second sub-block；
It further include the channel at least two reading and writing datas (DRW), wherein the first sub-block memory block is connected at least two reading and writing datas
First data read/write channel in channel, and the second sub-block memory block therein are connected at least two reading and writing data channels
Second data read/write channel；
And one output and input (DQ) block, wherein at least two reading and writing data channel passes between memory core and DQ block
Transmission of data, wherein command block drive command signal operation memory core, reading and writing data channel and DQ block.
In the memory block of the memory, first the second sub-block of sub-block is located in NxN array, and wherein N is an idol
Number, wherein the first sub-block is located at the first half of array, wherein the second sub-block is located at the latter half of array.
The command block arranges that wherein DQ block is arranged along the 2nd side of array along the 1st side of array, wherein the 1st side and the
2 sides are located at the opposite of array.
The first reading and writing data channel is routed between the first half of array, and the second reading and writing data channel is in array
Latter half between be routed.
The first sub-block and the second sub-block of the memory block are located in array, the bilateral symmetry positioned at array center position
Position.
The DQ block is arranged along the 2nd side of array.
The wherein data word has the first range byte, the second range byte, third range byte, the 4th range word
Section, wherein the first DQ block handles the first range byte, the 2nd DQ block handles the second range byte, and the 3rd DQ block handles third range
Byte, the 4th DQ block handle the 4th range byte.Wherein the first reading and writing data channel is connected to the first DQ block and the 2nd DQ block, the
Two reading and writing data channels are connected to the 3rd DQ block and the 4th DQ block.
Data are inputted from DQ block, pass through reading and writing data channel to some memory block.Data can be divided into first group and
Two groups of data, wherein first group of data is stored in the first sub-block of some particular memory block, second group of data is stored in some spy
Determine the second sub-block of memory block.
One typical DRAM may include eight or more memory block, such as block 0, block 1 etc..Memory core is by 8
A or 8 or more memory blocks form.Each piece may include bit line, wordline, storage unit, bit line detection amplifier, part
With global row decoder, column decoder etc..Each memory block can respond the data read/write order to the memory block.
Fig. 1 is the memory block diagram that the present invention has storage sub-block.Memory of the invention includes a command block 10, interior
Deposit core 12, reading and writing data channel 22 and 24 and input/output (DQ) 14.Reading and writing data channel 22 and 24 is multiplexing
Reading and writing data bus.
Order and address block 10 can also include test logic 16 and 20, order and address logic 18.Test 16 He of logic
20 include the internal test mode control circuit for testing respective memory.Order and address logic 18 are included as respective deposit
The circuit of reservoir processing order and address.
Storing core 12 includes eight block storages: memory block 0,1,2,3,4,5 67.Each memory block of 0-7 can wrap
Include first sub-block and second sub-block.The first sub-block and the second sub-block of 0-7 memory block are logical by reading and writing data respectively
Road 22 and 24 is connected with DQ block 14.Half of sub-block of 0-7 memory block is arranged by 4x4 array.First sub-block cloth of 0-7 memory block
Set the top half in 4x4 array, i.e. the 1st row and the 2nd row of array.Second sub-block of 0-7 memory block is arranged in 4x4 array
Lower half portion, i.e. the 3rd row and the 4th row of array.Reading and writing data channel 22 is routed between the 1st row of 4x4 array and the 2nd row,
The first sub-block of memory block 0-7 is connected to DQ block 14.The cloth between the 3rd row of 4x4 array and the 4th row of reading and writing data channel 24
Line is connected to the second sub-block of memory block 0-7 to DQ block 14.
If Subset block array is extended to NxN Subset block array, every two rows sub-block may be coupled to different data and read
Write access.Each reading and writing data channel can be located between every two row of NxN array, therefore upper sub-block and lower sub-block are to respective
The distance in reading and writing data channel is essentially identical.By keeping the distance for accessing each memory block essentially identical, in different memory blocks
The power consumption of reading and writing data order can be predicted more preferably and more symmetrical.
The preceding half block and rear half block of 0-7 memory block are arranged separately in the array relative to DQ block 14, deposit access each
Store up difference of the relative distance between different memory blocks of block and little.For the Subset block array of a 4x4, if some is stored
One sub-block of block is located at the first row of array, then second sub-block of the memory block will be located at the 4th column.If some is deposited
The sub-block of storage block is located at the secondary series of array, arranges then other sub-blocks of the memory block will be located at third.2 of each memory block
Sub-block is located at the central symmetry position of array.
Such as the first sub-block of memory block 0 is located at the first row of array, the second sub-block of memory block 0 is located at the 4th of array the
In column (or last column).When data are read in memory block 0, while two sub-blocks of access block 0.Data can be passed through
Read/write channel 22 reads the partial data of the first sub-block, and the partial data of the second sub-block is read by data read/write channel 24.
Since there are sub-block, each sub-block to respective reading and writing data channel 22 and 24 in the two sides of the physical location of reading and writing data channel 22 and 24
Distance it is all identical.To realize, whichsoever memory block is accessed, and power consumption is all similar.Because storing in core 12
The total distance of each memory block to DQ block 14 is similar.
Under the extreme case of not above scheme, if the first sub-block and the second sub-block of memory block 0 all in column 1,
Compared with other memory blocks not in first row, data must could be incited somebody to action by distance farthest on reading and writing data channel 22 and 24
Data are passed to/taking-up memory block 0.If the first sub-block and the second sub-block of memory block 0 are all in column 4, relative to other not
Data must be passed to/taking-up memory block 0 by shortest distance on reading and writing data channel by the memory block 7 of four column, these sub-blocks.
Due to these different distances, so that memory block 0 is with memory block 7 because data are passed to/take out the transmission power consumption generated and have very
Big difference causes power consumption asymmetric.
Storing core 12 can further comprise simulated block 40, read with providing various reference voltages to block storage 0-7 and data/
Write access 22 and 24.Analog circuit block 40 may include the typical element of memory, including voltage generator, detector, other electricity
Source generating circuit, clamp circuit etc..According to the design and specification of memory, simulated block 40 can provide other power consumptions of memory
It is required that.
The people with common skill is appreciated that the sub-block of any amount of memory block and/or any scale is equal in this respect
It is applicable to the present invention.In order to help to understand that this is invented, eight memory blocks are each there are two half block, are described to convey this
The concept of invention.However, the memory block of other quantity and/or any amount of sub-block are used equally for the present invention.Such as it can make
With 16 memory blocks, each memory block has 4 sub-blocks (i.e. 1/4 sub-block).Other variations of memory block and/or sub-block quantity
It is included in the present invention.In addition, the array size of sub-block equally can extend to NxN array, wherein N can be even number.Number
It can be routed between every two rows sub-block according to read/write channel and be connected to DQ.
Data are transmitted between DQ block 14 and memory block 0-7 in reading and writing data channel 22 and 24.DQ block 14 includes DQ control block
32 and DQ block 28,30,34 and 36.The data that DQ block 28,30,34 and 36 separately includes specified byte unit output and input electricity
Road.When DQ control block 32 can control 28 to DQ block, 30,34 and 36 global write (data write-in) and reading (data output)
Sequence.Therefore, DQ block 28,30,34 and 36 can follow the control signal from command block 18.Each DQ block 28,30,34 and 36
Including data input/output buffer, these buffers are controlled by the control signal of DQ control block 32.28,30,34 and of DQ block
36 are assigned to different byte numbers.
For example, memory supports the interface of 32 I/O read-write data, i.e. the data of 4 bytes, each byte has accordingly
DQ block is supported.DQ block 28 provides circuit relevant to the position 24-31 in 4 character data bytes and pad.DQ block 30 provides and 4 words
Save the relevant circuit in the position 8-15 and pad in data word.DQ block 34 provides circuit relevant to the position 0-7 in 4 byte datas
And pad.DQ block 36 provides circuit relevant to the position the 16-23 of 4 character data bytes and pad.Particularly, DQ block 28,30,34
It include the I/O interlock circuits of each byte with 36, including output driver, pad, power supply and output control logic, other
With the respective syllable dependent circuit of DQ block.
Therefore, each DQ block 28,30,34 and 36 is responsible for a byte of 4 byte words.The physics of DQ block 28,30,34 and 36
Position is extremely important, so that power consumption minimizes.First sub-block of 0-7 memory block is connected with DQ block 28 and 30, so that any number
It is only stored in the first sub-block of 0-7 memory block according to the position 24-31 and 8-15 of word.Further, since the first son of memory block 0-7
The position of block is in the top half for storing core 12, therefore DQ block 28 and 30 can also be located at the top half of DQ block 14, thus
More signal wires are allowed to be directly connected to reading and writing data channel 22.Likewise, the second sub-block of 0-7 memory block is connected to DQ block 34
With 36, so that 16-23 and 0-7 of any data word are only stored in the second sub-block of 0-7 memory block.Further, since storage
All in the lower half portion of storage core 12, DQ block 34 and 36 also is located at the lower half portion of DQ block 14 for the position of the second sub-block of block 0-7,
To allow more signal wires to be directly connected to reading and writing data channel 24.
DQ block 14 is made of DQ block 28,30,34,36, positioned at the side of memory core 12.By the way that DQ block 14 is put
On one side, symmetric design can be applied to sub-block, so that the read-write power consumption across different memory blocks is symmetrical.Usually life
Enable block 10 that can be located at the opposite of DQ block 14.But it can also be seen that different configurations from the present invention.For example, DQ block 14 can be with
Positioned at the upright position of current DQ block 14.Or DQ block 14 can be divided into two opposite segments, so that DQ block 28 and 30
In the side of storage core 12, and DQ block 34 and 36 is located at the other side of storage core 12.
Fig. 2 is the block diagram of another embodiment of the memory that the present invention has more memory blocks.According to the present invention, order and
Address (CA) block 10 and DQ block 14 can be located relative to the different location of storage core 12.For example, can be by DQ block 14 and life
The function of block 10 is enabled to merge into order and DQ block 14c, they are located at the side of storage core 12.Sub-block can be divided into two groups, and one
Group is located at storage core 12a, and another group is located at storage core 12b.Since order and DQ block 14c are disposed in reading and writing data channel
22 and 24 one end, by arrangement sub-block on the column direction of storage core 12a and 12b position (or the position on line direction,
Depending on reading and writing data channel 22 and 24 and the direction of DQ block 14c), memory block to order and DQ block 14c substantially has identical
Distance.
Fig. 3 is of the invention with another embodiment block diagram of the memory of more storage sub-blocks.In other realities of the invention
It applies in example, command block 10 and DQ block 14 can be located at the centre for storing core 12, and reading and writing data channel 22 and 24 is in command block 10
With the two sides of DQ block 14.Because DQ block 14 is placed on the center of storage core, pass through the position of arrangement sub-block in a column direction
(or position on line direction, depending on reading and writing data channel 22 and 24 and the direction of the opposite storage core of DQ block 14),
Memory block substantially has identical distance to DQ block 14.Sub-block can be divided into two groups, and one group is located at storage core 12a, another group of position
In storage core 12b.
Fig. 4 is the additional embodiment block diagram of the memory with more memory blocks of the invention.According to the present invention, command block 10
There can be different location with DQ block 14 with facing memory core 12.For example, relative to storage core 12, DQ block 14 and command block 10
The same side can be located at.DQ block 14 can be divided into two different block DQ block 14a and DQ block 14b, and wherein DQ block 14a reception comes from
The data in reading and writing data channel 22 output data to reading and writing data channel 22, and DQ block 14b receives logical from reading and writing data
The data in road output data to reading and writing data channel 24.Command block 10 can with DQ block and be placed on the same side, in DQ block
Between 14a and 14b.Since DQ block 14a and 14b are disposed in the one end in reading and writing data channel 22 and 24, son can be arranged
Position (or the position on line direction, depending on reading and writing data channel and the side of DQ block 14a and 14b of block in a column direction
To), set roughly the same for the distance of memory block to DQ block 14a and 14b.Sub-block can be divided into two groups, and one group is located at storage
Core 12a, another group is located at storage core 12b.
What the people for possessing common skill in this direction as one was understood, the physics based on memory of the invention
Layout Embodiment has very much.Above-described embodiment is not configured to limit in any way, is only used for prominent in present invention displaying
Those of embodiment.
Fig. 5 is another embodiment of the memory with storage sub-block of the invention.In LPDDR4 storage core, deposit
Storing up core, there are four different region 41a-41d.Storage core 41a-41d can be divided into two groups, one group of storage core 41a and
41b, another group of storage core 41c and 41d.For every group of storage core, there is DQ block and an order and address block, for
Every group of storage core write-in data read data from every group of storage core.Especially DQ block 44a passes through reading and writing data channel 43a
Reading writes data to memory core 41a;DQ block 44b writes data to storage core 41b by reading and writing data channel 43b reading;Order
With address block 46a for controling and operating DQ block 44a and 44b and storage core 41a and 41b.In addition, DQ block 44c passes through number
Storage core 41c is write data to according to read/write channel 43c reading;DQ block 44d writes data to memory by reading and writing data channel 43d reading
Core 41d;Order and address block 46b control and operate DQ block 44c and 44d, store core 41c and 41d.As shown, this hair
It is bright to can extend to any number of storage core, DQ block and order and address block.The present embodiment is only based on the present invention
Memory various configurations example.
Fig. 6 is the data path of memory of the invention.Command block 10 includes that order and address block 160, row address select
Device 162, block control logic 164, column address counter and latch blocks 166.Order and address about data can be input to life
It enables and address block 160.The address of data is transferred to storage core 12, passes through row address selector 162, block control logic 164
Data are read or are written from storage core 12 with column address counter/latch 166.Row address selector 162, block control are patrolled
Volumes 164 and column address counter/latch 166 can be by activating one of memory block 0-7 read come storing data or therefrom
Access evidence, to be operated to storage core 12.
Although the present invention is described some embodiments, it is to be appreciated that the invention is not limited to
These embodiments.On the contrary, the present invention is understood that and explains in its broadest sense, as claim is reflected.Cause
This, these claims are construed as not only including equipment described here, method and system, every other and into one
The change and modification of step will be apparent from for having the people of common skill in this respect.
Claims (7)
1. a kind of framework of dynamic RAM, including a command block, the memory of multiple memory blocks, it is characterized in that each
Memory block at least has the first sub-block and the second sub-block；
It further include the channel at least two reading and writing datas (DRW), wherein the first sub-block memory block is connected at least two reading and writing datas
First data read/write channel in channel, and the second sub-block memory block therein are connected at least two reading and writing data channels
Second data read/write channel；
And one output and input (DQ) block, wherein at least two reading and writing data channel passes between memory core and DQ block
Transmission of data, wherein command block drive command signal operation memory core, reading and writing data channel and DQ block.
2. low-power consumption dynamic RAM according to claim 1, it is characterized in that in the memory block of the memory,
First the second sub-block of sub-block is located in NxN array, and wherein N is an even number, wherein the first sub-block is located at the first half of array
Point, wherein the second sub-block is located at the latter half of array.
3. low-power consumption dynamic RAM according to claim 1, it is characterized in that the command block is along the 1st of array
Side arrangement, wherein DQ block is arranged along the 2nd side of array, wherein the 1st side and the 2nd side are located at the opposite of array.
4. low-power consumption dynamic RAM according to claim 1, it is characterized in that the first reading and writing data channel
It is routed between the first half of array, the second reading and writing data channel is routed between the latter half of array.
5. low-power consumption dynamic RAM according to claims 1 and 2, it is characterized in that the first son of the memory block
Block and the second sub-block are located in array, positioned at the symmetrical position of array center position.
6. low-power consumption dynamic RAM according to claim 5, it is characterized in that the wherein data word has first
Range byte, the second range byte, third range byte, the 4th range byte, wherein the first DQ block handles the first range byte,
2nd DQ block handles the second range byte, and the 3rd DQ block handles third range byte, and the 4th DQ block handles the 4th range byte,
In the first reading and writing data channel be connected to the first DQ block and the 2nd DQ block, the second reading and writing data channel is connected to the 3rd DQ block and
Four DQ blocks.
7. low-power consumption dynamic RAM according to claim 6 leads to it is characterized in that the data are inputted from DQ block
Reading and writing data channel is crossed to some memory block, data can be divided into first group and second group of data, wherein first group of data is deposited
The first sub-block in some particular memory block is stored up, second group of data is stored in the second sub-block of some particular memory block.
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| CN201910275295.6A CN110164487A (en) | 2019-04-08 | 2019-04-08 | A kind of framework of dynamic RAM |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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