CN107408404A - Apparatuses and methods for memory device as a store for program instructions - Google Patents

Apparatuses and methods for memory device as a store for program instructions Download PDF

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CN107408404A
CN107408404A CN201680012413.9A CN201680012413A CN107408404A CN 107408404 A CN107408404 A CN 107408404A CN 201680012413 A CN201680012413 A CN 201680012413A CN 107408404 A CN107408404 A CN 107408404A
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China
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memory
plurality
array
library
program instructions
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CN201680012413.9A
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Chinese (zh)
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J·T·扎沃德恩
K·B·惠勒
R·C·墨菲
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美光科技公司
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Priority to US62/112,914 priority
Application filed by 美光科技公司 filed Critical 美光科技公司
Priority to PCT/US2016/015059 priority patent/WO2016126478A1/en
Publication of CN107408404A publication Critical patent/CN107408404A/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408Address circuits
    • G11C11/4087Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065Differential amplifiers of latching type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1036Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20Employing a main memory using a specific memory technology
    • G06F2212/202Non-volatile memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/603Details of cache memory of operating mode, e.g. cache mode or local memory mode
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/12Group selection circuits, e.g. for memory block selections, chip selection, array selection

Abstract

The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller, coupled to the array and the sensing circuitry is configured to receive a block of instructions including a plurality of program instructions. The memory controller is configured to store the block of instructions in the array and retrieve program instructions to perform logical operations on the compute component.

Description

用于存储器装置的设备及方法以作为程序指令的存储 Storage device and method for a memory device as program instructions

技术领域 FIELD

[0001] 本发明大体上涉及半导体存储器及方法,且更特定来说涉及用于存储器装置的设备及方法以作为程序指令的存储。 [0001] The present invention generally relates to a semiconductor memory and methods, and more particularly, storage device and method for a memory device according to a program instruction.

背景技术 Background technique

[0002] 存储器装置通常提供为计算系统中的内部半导体集成电路。 [0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in a computing system. 存在许多不同类型的存储器,包含易失性存储器及非易失性存储器。 There are many different types of memory including volatile memory and non-volatile memory. 易失性存储器可需要电力来维持其数据(例如,主机数据、错误数据等),且包含随机存取存储器(RAM)、动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、同步动态随机存取存储器(SDRAM)及晶闸管随机存取存储器(TRAM)等。 Volatile memory can require power to maintain its data (e.g., host data, error data, etc.), and includes a random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM) and a random access memory thyristors (the TRAM) and the like. 非易失性存储器可在未供电时通过保持存储数据而提供永久性数据,且可包含NAND闪存、N0R闪存及电阻可变存储器(例如相变随机存取存储器(PCRAM)、电阻式随机存取存储器(RRAM)及磁阻式随机存取存储器(MRAM),例如自旋力矩转移随机存取存储器(STT RAM))等。 The nonvolatile memory may be provided by the power supply when not holding data permanently stored data, and may include NAND flash memory, and a resistance variable N0R flash memory (e.g., a phase change random access memory (the PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), for example, a spin-torque transfer random access memory (STT RAM)) and the like.

[0003] 计算系统通常包含若千处理资源(例如,一或多个处理器),其可检索并执行指令且将所执行指令的结果存储到适合位置。 [0003] The computing system typically comprises a processing resource, if one thousand (e.g., one or more processors), which may retrieve and execute the instruction and the execution result is stored into the appropriate position instruction. 处理器可包括若干功能单元,例如算术逻辑单元(ALU)电路、浮点单元(FPU)电路及/或组合逻辑块,例如,所述功能单元可用以通过对数据(例如,一或多个操作执行例如AND、OR、NOT、NAND、N0R及X0R以及反相(例如,反转)逻辑运算的逻辑运算而执行指令。举例来说,功能单元电路可用以经由若干逻辑运算而对操作数执行例如加法、减法、乘法及/或除法的算术运算。 The processor may include several functional units such as an arithmetic logic unit (ALU) circuit, a floating point unit (FPU) circuit and / or a combinational logic block, e.g., the functional unit may be used to pass data (e.g., one or more operations performs, for example aND, OR, NOT, NAND, N0R and X0R and an inverter (e.g., reverse) and logic operation execution logic operation instructions. for example, the functional unit circuit may be used to perform a plurality of logical operation operand via e.g. addition, subtraction, multiplication and / or division arithmetic.

[0004] 在提供指令到功能单元电路以供执行时可涉及计算系统中的若干组件。 [0004] in providing instructions to the functional units for the circuit it may involve several components, when executed in a computing system. 可例如通过处理资源(例如控制器及/或主机处理器)执行所述指令。 For example, the instructions may be executed by a processing resource (e.g. the controller and / or host processor). 可将数据(例如,将对其执行指令的操作数)存储在可由功能单元电路存取的存储器阵列中。 The data may be memory array (e.g., the execution of its instruction operand) is stored in the functional unit can be accessed in the circuit. 可从所述存储器阵列检索指令及/或数据,且可在功能单元电路开始对数据执行指令之前串行化及/或缓冲指令及/或数据。 Retrieving from said memory array instructions and / or data, and may begin execution serialized instruction prior to the data and / or buffering instructions and / or data to the functional unit circuit. 此外,因为可通过功能单元电路以一或多个时钟周期执行不同类型的运算,所以还可串行化及/或缓冲所述指令及/或数据的中间结果。 Further, since the different types of operators may be performed in one or more clock cycles by the circuit function units, it may be serialized and / or intermediate results and said instruction buffer / or data.

[0005] 在许多例子中,处理资源(例如,处理器及/或相关联功能单元电路)可在存储器阵列外部,且可经由处理资源与存储器阵列之间的总线存取数据以执行指令集。 [0005] In many cases, processing resources (e.g., processor and / or associated functional unit circuit) may be external to the memory array, and may be accessed via a data bus between the processing resources and memory array to execute a set of instructions. 处理性能在存储器中处理器(processor-in-memory)装置中可得以改进,其中可在存储器内部及/或附近(例如,直接在与存储器阵列相同的芯片上)实施处理资源。 Processing performance of a processor (processor-in-memory) devices can be improved in a memory, which may be (e.g., directly in the same memory array chips) processing resources embodiment / or near the internal memory and. 存储器中处理(processing-in-memory) 装置可通过减少及/ 或消除外部通信而节省时间,且还可节约电力。 Device memory processing (processing-in-memory) may be reduced and / or eliminated to save time and external communication, and may also conserve power through.

附图说明 BRIEF DESCRIPTION

[0006] 图1A是根据本发明的若干实施例的呈包含存储器装置的计算系统的形式的设备的框图。 [0006] FIG 1A is a block diagram of apparatus in the form of a computing system including a memory device according to several embodiments of the present invention.

[0007] 图1B是根据本发明的若干实施例的呈包含存储器装置的计算系统的形式的设备的另一框图。 [0007] FIG. 1B is a block diagram of another form of a computing system containing the memory device of the embodiment of the device according to several embodiments of the present invention.

[0008] 图1C是根据本发明的若干实施例的存储器装置的库的框图。 [0008] FIG 1C is a block diagram of a database according to the present invention several embodiments of a memory device embodiment.

[0009] 图1D是根据本发明的若干实施例的存储器装置的库的另一框图。 [0009] FIG. 1D is a block diagram of another embodiment of a memory device repository in accordance with several embodiments of the present invention.

[0010] 图2是说明根据本发明的若干实施例的存储器装置的感测电路的示意图。 [0010] FIG. 2 is a diagram illustrating a sensing circuit of a memory device according to several embodiments of the present invention.

[0011] 图3是说明根据本发明的若干实施例的存储器装置的感测电路的示意图。 [0011] FIG. 3 is a schematic diagram of a sensing circuit of a memory device according to several embodiments of the present invention.

[0012] 图4是说明根据本发明的若干实施例的由图3中所示的感测电路实施的可选择逻辑运算结果的逻辑表。 [0012] FIG. 4 is a logic table of the operation result select logic implemented by the sensing circuit shown in FIG 3 in accordance with several embodiments of the present invention.

具体实施方式 Detailed ways

[0013] 本发明包含关于具有存储器装置的设备及方法以作为程序指令(例如,具备存储器中处理(PM)能力的装置的P頂命令)的存储。 [0013] The present invention comprises apparatus and methods having a memory on a memory device to a program instruction (e.g., comprising means (PM) in the memory capacity P of the top of the processing command). 在一个实施例中,设备包括存储器装置。 In one embodiment, the apparatus comprises a memory device. 设备可经由数据总线及控制总线耦合到主机。 Devices may be coupled to the host via a data bus and a control bus. 存储器装置包含存储器单元阵列及经由多个感测线耦合到所述阵列的感测电路。 The memory device includes a memory cell array and a sense circuit coupled to the array via a plurality of sense lines. 所述感测电路包含感测放大器及经配置以实施逻辑运算的计算组件。 The sensing circuit comprises a sense amplifier and configured to implement the logic operation of the computing components.

[0014] 存储器控制器耦合到所述阵列及感测电路。 [0014] The memory controller coupled to the array and sense circuitry. 存储器控制器经配置以接收具有多个程序指令的指令块。 Instruction block memory controller is configured to receive a plurality of program instructions. 举例来说,可从主机接收所述指令块。 For example, the instruction block may be received from the host. 在各种实施例中,程序指令通过主机预解析。 In various embodiments, the program instructions by the host preresolved. 如本文中所使用,术语“预解析”希望意味着通过程序设计师针对特定装置(例如,具备PIM能力的装置)以软件及/或固件(例如,机器指令)池称为“微代码”)设计(例如, 写入)程序指令。 As used herein, the term "pre-analysis" means desired by the designer in software programs and / or firmware (e.g., machine instructions) Pool referred to as "microcode" for (e.g., the ability of the device includes PIM) device specific) design (e.g., write) the program instructions. 另外,如本文中所使用,术语“预解析”希望指示己例如通过主机处理资源确定用于存储指令的地址翻译。 Further, as used herein, the term "pre-analysis" indicates hexyl desired host processing resources, for example, by determining the address for storing instructions translation.

[0015] 在各种实施例中,指令块包含与存储器中处理(PIM)命令(在本文中也称为“程序指令”)相关联的多个指令。 [0015] In various embodiments, the instruction block comprising a plurality of instructions and a memory command processing (the PIM) (also referred to herein as "program instructions") is associated. 如本文中所使用,PIM命令经执行以引起具备PIM能力的装置在存储器上或在存储器附近执行逻辑运算。 As used herein, PIM command executed to cause the apparatus includes a PIM capacity in performing a logic operation on the memory or in the vicinity of the memory. 逻辑运算的实例包含逻辑布尔运算(Boolean operation),例如AND、N0R、X0R等。 Examples of logic operations comprising a logical Boolean operations (Boolean operation), e.g. AND, N0R, X0R like. 存储器控制器经配置以将指令块存储在阵列中,且检索程序指令以在计算组件上执行逻辑运算。 The memory controller is configured to store instruction blocks in the array, and the retrieval program instructions to perform logical operations on the computing component.

[0016]如下文将更详细解释,存储器装置的库可为一万六千列或更多(16K+)列宽。 [0016] As will be explained in detail below, the library may be a memory device or more sixteen thousand (16K +) column width. 阵列内可存在库的多个库区段。 There may be multiple libraries Reservoir segments within the array. 每一库区段可具有特定数目个行,例如,512个行。 Reservoir each segment may have a certain number of rows, for example, 512 rows. 跨16K+列宽库区段可定义多个块。 16K + cross section may define a plurality of column width Reservoir blocks. 库区段中的块可具有1K+列宽。 The blocks may have segments Reservoir 1K + column width. 因此,如本文中所使用,指令块希望意味着如适于存储在具备PIM能力的装置中的具有大约1K个位的位长度的指令块。 Thus, as used herein, means that the desired instruction block suitable for storing such instructions having approximately 1K blocks of bits in the bit length of the apparatus is provided with the capability PIM. 在各种实施例中,块可包含进一步定义成多个块(chunk),例如,四⑷个256位块。 In various embodiments, the block may be further defined as comprising a plurality of blocks (the chunk), for example, four 256-bit blocks ⑷. 然而,实施例不限于位的此实例数目。 However, the embodiment is not limited to this example, the number of bits.

[0017] 如在本发明中的下文将进一步显而易见,此精细(granular)定义可用于其中需要对准向量以执行逻辑运算的具备存储器中处理(P頂)能力的存储器装置。 [0017] The present invention hereinafter will be further apparent, this fine (Granular) can be used to define a vector which needs to be aligned to perform the logical operation includes a memory process (P top) of the memory device capability. 举例来说,可将256位块视为四(4)个64位值(例如,数值)的向量。 For example, block 256 may be considered as four (4) 64-bit values ​​(e.g., values) vector. 每一M位值可为逻辑运算中的向量的元素。 M-bit value of each element of the vector can be in the logical operation. 另外,具有与P顶命令相关联的多个指令的指令块可包含64位P顶命令。 Furthermore, P has a top plurality of instructions associated with the command instruction block 64 may comprise a top P command. 举例来说,用以执行逻辑运算的个别P頂命令(例如,“程序指令”)的长度可为64个位。 For example, for the individual top P command logical operations (e.g., "program instructions") may have a length of 64 bits. 因此,PIM命令可呈长度为64个位的微码指令的形式。 Thus, PIM command length may be in the form of 64-bit microcode instructions.

[0018] 进一步应注意,具备P頂能力的装置运算可使用基于位向量的运算来执行逻辑运算。 [0018] It should further be noted that the ability to have a top P means logic operations may be performed based on the arithmetic operation using the bit vector. 如本文中所使用,术语“位向量”希望意味着位向量存储器装置(例如,P頂装置)上的物理邻接(在存储器单元阵列中的行(例如,水平定向)或列(例如,垂直定向)中物理邻接)数目个位。 As used herein, the term "bit vector" desired physical abutment (rows (e.g., horizontal orientation) in the memory cell array on the mean vector memory bit means (e.g., P top devices) or columns (e.g., vertical orientation ) contiguous physical) number of bits. 因此,如本文中所使用,“位向量运算”希望意味着对位向重执行的运算,所述位向量是例如由PIM装置使用的虚拟地址空间的邻接部分(也称为“±央”)。 Thus, as used herein, "bit vector operation" to the desired position calculation means for re-executed, for example, the bit vector is contiguous portion of virtual address space used by the PIM means (also referred to as "± center") . 举例来说,虚拟地址空间的块可具有256个位的位长度。 For example, the virtual block address space may have a bit length of 256 bits. 块可或可不与所述虚拟地址空间中的其它块物理邻接。 May or may not block with the physical block adjacent to the other virtual address space. [0019]任何处理资源的重要特征是存取足够程序指令以保持忙碌而具有最小延迟或中断的能力。 [0019] The important feature of any processing resources are sufficient to access program instructions to keep busy with minimal delay or interruption capability. 在本发明以前,存储器中处理(PIM)装置期望扩充动态随机存取存储器(DRAM)地址/控制总线以针对DRAM装置上的每一库而将PIM命令传递到存储器控制器。 Prior to the present invention, the processing memory (PIM) desired expansion device dynamic random access memory (DRAM) address / control bus for each bank in the DRAM device and transmitting the command to the memory controller PIM. 针对那个方案,接着DRAM中的每一库将提供专用于指令的小存储器。 For that program, and then each of the DRAM library dedicated to memory instruction small. 来自此方法的设计复杂性是双重的。 From design complexity of this approach is twofold.

[0020]首先,需要将地址/控制(A/C)总线制成更大且以较高速度操作增加对DRAM零件的输入/输出(I/O)设计的显著风险。 [0020] First, the need to address / control (A / C) and increasing the input bus made more significant part of the risk DRAM / output (I / O) designed to operate at a higher speed. 增加I/O的质量及速度显著影响芯片面积且涉及谨慎设计工作以避免干扰实际DRAM操作。 Increase in I / O speed and quality significantly affect the chip area and to a careful design to avoid interference with the actual DRAM operation.

[0021]其次,芯片上可用指令带宽将显著受限于每一库中所包含的指令存储器的小的大小。 [0021] Next, an on-chip instruction available bandwidth significantly limited by the small size of each library included in the instruction memory. 无“后备存储”(例如,在库本地的存储)的所述指令存储器的有限大小意味着一旦指令串流运行超出所述小存储器的大小,DRAM便将等待主机系统提供下一指令集。 It means no finite size "backing store" (e.g., stored in the library locally) Once the instruction memory operating instruction stream exceeds the size of the small memory, waiting for the host system to provide a DRAM put the next set of instructions. 增加专用指令存储器(例如,在库本地的“高速缓存”)的大小将改进PIM系统提供足够指令以使DRAM保持忙于PM运算的能力。 Adding a dedicated instruction memory (e.g., a local library "cache") size would improve PIM instructions to cause the system to provide sufficient retention busy PM DRAM operation. 然而,增加存储器的量影响整体芯片面积且还增加干扰实际DRAM操作的可能性。 However, increasing the amount of memory and also affects the overall chip area actually increase the likelihood of interference DRAM operation.

[0022]本发明的实施例提供一种将具有自变量的大量程序指令提供到DRAM且接着以低延时将所述指令投送到DRAM的嵌入式处理引擎(例如,存储器控制器)同时保留DRAM的协议、逻辑及电接口的有效方法。 [0022] Embodiments of the present invention provide a number of program instructions having an argument and then provided to the DRAM to the low-latency instructions delivered to the DRAM embedded processing engines (e.g., memory controller) while retaining the method of the DRAM effective protocol, logical, and electrical interfaces. 因此,本文中描述的实施例可有利于使A/C总线保持在标准宽度及数据速率,从而减少PIM DRAM的任何“特殊”设计量,且还使PIM DRAM与多种计算装置中的现有存储器接口更兼容。 Thus, the embodiments described herein may be beneficial that the A / C bus standard width and held in the data rate, thereby reducing the "special" PIM DRAM design of any amount, and also to enable PIM DRAM with a variety of computing devices in the conventional more compatible with the memory interface.

[0023]另外,本文中描述的实施例可允许主机系统在操作开始时提供大指令块到DRAM, 从而显著减少或完全消除指令执行的中断,以将更多指令传送到具备PIM能力的DRAM装置。 [0023] Further, the embodiments described herein may allow a host system to provide a large instruction at the operation start block to a DRAM, thereby significantly reducing or completely eliminating interrupt instruction execution, a DRAM device to transmit more instructions to have PIM Ability . 具备PIM能力的装置设计及嵌入式处理引擎(例如,存储器控制器)的控制流与DRAM的先前折衷包含DRAM上所使用的I/O的显著增加,这将增加零件上的非生产性空间的分率,且增加平面规划(floor planning)及噪声抑制(noise containment)复杂性,且增加零件上的电力消耗而未增加额外计算性能。 Increased significantly compromise comprising previously used on the DRAM I / O devices and embedded processing engine design (e.g., memory controller) includes the ability to PIM and the DRAM control flow, which will increase the space on the part unproductive fraction, and increases the complexity of the planning plane (floor planning) and noise suppression (noise containment), and increases the power consumption on the part without additional computational performance. 还如上文所述,其它先前折衷包含在DRAM中使用相对较大、 专用存储器区域来存储程序指令而仍未足够大以保持大量程序指令,因此增加对整体芯片上的I/O资源的竞争且减小存储器控制器的有效速度。 Also as described above, other previously contained in the trade-off is relatively large in a DRAM, the memory area dedicated to store program instructions and yet large enough to hold a large number of program instructions, thereby increasing competition for I / O resources and the overall chip reducing the effective speed of the memory controller.

[0024] 如下文更详细描述,实施例可允许主机系统分配多个DRAM库中的若干位置(例如, 子阵列或子阵列的部分)以保持指令块。 [0024] as described in greater detail below, embodiments may allow a host system to allocate a number of locations (e.g., part of a sub-array or sub-array) in the plurality of DRAM banks to maintain instruction block. 主机系统将对整个指令块执行地址解析且将其写入到目标库中的所分配位置(例如,子阵列)中。 The host system will perform the entire instruction block address resolution and write it to the dispensing position (e.g., sub-array) in the target library. 根据各种实施例,指令块可包含与存储器中处理(PIM)命令(在本文中还称为“程序指令”)相关联的一或多个相异指令。 According to various embodiments, as in instruction block may include processing memory (PIM) command (also referred to herein as "program instructions") or a plurality of distinct instructions associated. 如本文中所使用,PIM命令经执行以引起具备PIM能力的装置在存储器上或在存储器附近执行逻辑运算。 As used herein, PIM command executed to cause the apparatus includes a PIM capacity in performing a logic operation on the memory or in the vicinity of the memory. 举例来说,在各种实施例中,可在与具备PIM能力的装置的存储器阵列的间距上执行逻辑运算。 For example, in various embodiments, logical operations may be performed on the spacing means includes a PIM capacity memory array.

[0025] 将指令块写入到所分配位置利用DRAM装置的正常DRAM写入路径。 [0025] The instruction block is written to the DRAM device using a normal position assigned to DRAM write path. 在将指令块写入到所分配位置(例如,子阵列)中之后,主机系统可引导存储器控制器(例如,DRAM库控制器) 开始执行所述指令块。 When the instruction block is written to the dispensing position (e.g., child arrays) after the host system may direct a memory controller (eg, DRAM controller database) begin executing the instruction block. 存储器控制器根据需要将从所分配位置拉取(pull)指令块以处置所述指令块所含有的分支、循环、逻辑及数据运算,根据需要高速缓存程序指令且再填充指令高速缓存。 The memory controller will need to pull the dispensing position (pull) the branch instruction block, circulation, and logic to handle operation data contained in the instruction block, according to the instruction cache program and required instruction cache refill.

[0026]此外,在存储器控制器执行指令块时,主机系统可将后续指令块写入(例如,预写入)到所分配指令子阵列中,以有利于具备PIM能力的装置中的未来计算的开始。 [0026] Further, when the memory controller executes the instruction block, the host system may be a subsequent block write command (e.g., pre-write) command to the sub-array allocated to facilitate future includes means capable of calculating PIM s begin. 如读者将了解,虽然本文中用实例论述DRAM式具备P頂能力的装置,但实施例不限于DRAM存储器中处理器(P頂)实施方案(P頂RAM)。 As the reader will appreciate, although the examples discussed herein with DRAM device includes a P-type top capacity, but the embodiment is not limited to a DRAM memory, a processor (P top) embodiment (P top RAM).

[0027]为了解经改进程序指令技术,用于实施此类技术的设备、具有PIM能力的存储器装置及相关联主机的论述如下。 [0027] In order to understand instructions TECHNICAL improved, apparatus for implementing such techniques discussed PIM has the ability to host memory devices and associated follows. 根据各种实施例,涉及具有PIM能力的存储器装置的程序指令(例如,PIM命令)可将PIM命令的实施分布在多个感测电路上方,所述感测电路可实施逻辑运算且可将PIM命令存储在存储器阵列内,例如不必用主机经由存储器装置的A/C总线来回传送所述PIM命令。 According to various embodiments, it relates to a memory device having a capability PIM program instructions (e.g., PIM command) command may be implemented PIM distributed over the plurality of sense circuits sensing, the sensing circuit may implement logical operations and may PIM command stored in the memory array, for example, do not have a memory device via the a / C bus back and forth with the host commands the PIM. 因此,涉及具有PIM能力的存储器装置的PIM命令可以较少时间且使用较少电力完成。 Thus, to a memory device having a capability of PIM PIM command using less power and less time to complete. 通过减少在计算系统周围移动以处理所请求的存储器阵列操作(例如,读取、 写入等)的数据量,可实现某一时间及电力优点。 By reducing the amount of data moving processing requested memory array operations (e.g., read, write, etc.) can be achieved and power advantages of a time around the computing system.

[0028]与先前系统(例如先前PM系统)及具有外部处理器的系统(例如,定位在存储器阵列外部(例如在单独集成电路芯片上)的处理资源)相比,本发明的若干实施例可提供与执行计算功能相关联的经改进平行性及/或降低的电力消耗。 [0028] with previous systems (such as previously PM system) and a system having an external processor (e.g., positioned outside the memory array (e.g., processing resources on a single integrated circuit chip)) compared several embodiments of the present invention may be provide improved parallelism and performs functions associated with computing and / or reduced power consumption. 举例来说,若干实施例可提供执行完整的计算功能,例如整数加法、减法、乘法、除法及CAM (内容可寻址存储器)功能,而例如不经由总线(例如,数据总线、地址总线、控制总线)将数据传送出存储器阵列及感测电路。 For example, several embodiments may be provided to perform a complete calculation function, e.g. integer addition, subtraction, multiplication, division, and CAM (content addressable memory) functions, for example but not via a bus (e.g., a data bus, an address bus, a control bus) to transfer data out of the memory array and the sense circuit. 此类计算功能可涉及执行若千逻辑运算(例如,例如AND、OR、NOT、NOR、NAND、XOR等的逻辑函数)。 Such calculation function may involve performing a logical operation if one thousand (e.g., such as AND, OR, NOT, NOR, NAND, XOR logic function, etc.). 然而,实施例不限于这些实例。 However, embodiments are not limited to these examples. 举例来说,执行逻辑运算可包含执行若干非布尔逻辑运算,例如复制、比较、破坏等。 For example, performing a logical operation may include performing a number of non-Boolean logic operations, such as copying, comparing, and other damage.

[0029] 在先前方法中,可(例如,经由包括输入/输出(I/O)线的总线)将数据从阵列及感测电路传送到例如处理器、微处理器及/或计算引擎的处理资源,所述处理资源可包括经配置以执行适当逻辑运算的ALU电路及/或其它功能单元电路。 [0029] In previous methods, it may be (e.g., including via an input / output (I / O) bus lines), for example, to process the data from the array and sensing circuit transmits a processor, a microprocessor and / or calculated engine resources, the processing resources may include ALU circuitry and / or other functional units suitable circuitry configured to perform logical operations. 然而,将数据从存储器阵列及感测电路传送到此处理资源可涉及大量电力消耗。 However, data transfer and sensing circuit array from the memory resources available to this process involves a large power consumption. 即使处理资源定位在与存储器阵列相同的芯片上,在将数据移出阵列而到计算电路(此可涉及执行感测线(在本文中可称为数字线或数据线)地址存取(例如,列解码信号的触发(firing))以将数据从感测线传送到I/O线(例如,本地I/O线)上;将数据移动到阵列外围;及将数据提供到计算功能)时仍可消耗大量电力。 Even a processing resource located on the same chip with the memory array, the array and the data out to the calculation circuit (this may involve performing sensing line (may be referred to herein as a data line or digit line) address to access (e.g., column and when the data is still supplied to the calculation function); trigger decoded signal (firing)) to transfer data from the sensing line to the I / O lines (e.g., local I / O line); moving the data to the peripheral array consume large amounts of electricity.

[0030] 此外,处理资源(例如,计算引擎)的电路可不符合与存储器阵列相关联的间距规贝1J。 [0030] Furthermore, the circuit processing resources (e.g., compute engine) may not comply with regulations pitch shell 1J associated with the memory array. 举例来说,存储器阵列的单元可具有处2或册2单元大小,其中“F”是对应于单元的特征大小。 For example, the memory cell array may have at the 2 or 2 copies unit size, where "F" corresponding to the feature size of the unit. 因而,与先前P頂系统的ALU电路相关联的装置(例如,逻辑门)可无法形成在与存储器单元的间距上,这可影响例如芯片大小及/或存储器密度。 Thus, the previous ALU circuit P lifting system associated with means (e.g., logic gates) may be formed not on the pitch of the memory cells, which may affect, for example, the chip size and / or density memory. 本发明的若干实施例包含形成在与存储器单元阵列的间距上且能够在存储器单元阵列本地执行例如集中及分散操作的计算功能的感测电路。 Some embodiments of the present invention comprises a sensing circuit and capable of forming on the pitch of the array of memory cells, for example, the memory cell array is performed locally and centralized calculation functions of the dispersing operation.

[0031] 在本发明的以下详细描述中,参考形成本发明的部分的附图,且在附图中通过说明展示可如何实践本发明的一或多个实施例。 [0031] In the following detailed description of the present invention, with reference to the accompanying drawings which form part of the present invention, and to show by way of illustration can be how to practice the present invention, one or more embodiments in the accompanying drawings. 足够详细地描述这些实施例以使所属领域的一般技术人员能够实践本发明的实施例,且应了解,在不脱离本发明的范围的情况下,可利用其匕买施例且可进行过程、电气及/或结构改变。 These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of the present invention, and it should be appreciated that without departing from the scope of the present invention may be utilized which dagger Buy embodiments and may be the process, electrical and / or structural changes. 如本文中所使用,例如“N,'、“M”等的标示符(尤其关于图式中的元件符号)指示:可包含如此指定的若干特定特征。如本文中所使用, “若干”特定事物可指代此类事物中的一或多个(例如,若干存储器阵列可指代一或多个存储器阵列)。“多个”希望指代多于一个此类事物。 As used herein, such as "N, '," M "or the like identifier (particularly with respect to the element symbols) indicate: may include a number of specific features such as specified herein," a number of "specific things may refer to one or more (e.g., can refer to a plurality of memory arrays or a plurality of memory arrays) Generation of such things. "plurality" are intended to refer to more than one such thing.

[0032]本文中的图遵循编号惯例,其中首位或前几位数字对应于图式图号且剩余数字识别图式中的元件或组件。 [0032] FIG herein follow a numbering convention in which the first or leading digits correspond to the drawing figure number and the remaining digits identify an element or component. 可通过使用类似数字识别不同图之间的类似元件或组件。 You may identify similar elements or components between different figures through the use of similar digits. 举例来说,2〇6可参考图2中的元件“〇6”,且类似元件在图3中可称为306。 For example, the second element may be 2〇6 "〇6" Referring to FIG, and a similar element in FIG. 3 may be referred to as 306. 如将了解,可添加、交换及/或消除在本文中的各种实施例中展示的元件以提供本发明的若千额外实施例。 As will be appreciated, can be added, exchanged, and / or embodiment eliminates the various elements shown in the embodiments herein to provide an embodiment of the present invention when the additional one thousand. 另外,如将了解,图中所提供的元件的比例及相对尺度希望说明本发明的某些实施例,且不应被视为限制意义。 Further, as it will be appreciated the proportion and the relative scale of the elements provided in the figures intended to illustrate certain embodiments of the present invention, and should not be regarded as limiting sense.

[0033]图1A是根据本发明的若干实施例的呈包含存储器装置丨2〇的计算系统1〇〇的形式的设备的框图。 [0033] FIG 1A is a form of apparatus comprises a memory means in the form of 1〇〇 2〇 Shu computing system block diagram of the embodiment according to several embodiments of the present invention. 如本文中所使用,设备希望意味着可经耦合以实现特定功能的一或多个组件、装置及/或系统。 As used herein, the device may be intended to mean one or more components, devices and / or systems coupled to achieve a particular functionality. 如本文中所使用,系统希望意味着以有线或无线方式耦合在一起以形成较大网络(例如,如在分布式计算网络中)的装置集合。 As used herein, systems intended to mean a wired or wireless coupled together to form a larger network (e.g., as in a distributed computing network) collection means. 因此,图1A到1D中所展示且论述的存储器装置12〇、存储器控制器140、通道控制器143、库仲裁器145、高速接口(HSI) 141、存储器阵列130、感测电路150及/或逻辑电路170还可单独视为“设备”。 Thus, in FIG. 1A-1D are shown and discussed 12〇 memory device, memory controller 140, channel controller 143, the arbiter 145 libraries, high-speed interface (HSI) 141, a memory array 130, sensing circuit 150 and / or the logic circuit 170 may also be considered as a separate "device."

[0034]系统100包含主机110,所述主机110耦合(例如,连接)到包含存储器阵列130的存储器装置120。 [0034] The system 100 includes a host 110, coupled to the host 110 (e.g., connected) to the memory array 130 includes memory means 120. 主机110可为主机系统,例如个人膝上型计算机、桌上型计算机、数码相机、智能电话或存储器卡读取器,以及各种其它类型的主机。 Host 110 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a smart phone or a memory card reader, and various other types of hosts. 主机110可包含系统主板及/或背板, 且可包含若干处理资源(例如,一或多个处理器、微处理器或某一其它类型的控制电路)。 Host 110 may include a system board and / or the backsheet, and may include a plurality of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). 系统100可包含单独集成电路,或主机110及存储器装置120两者可在相同集成电路上。 The system 100 may include separate integrated circuits, and a memory device 110 or the host 120 may be both on the same integrated circuit. 系统100可为例如服务器系统及/或高性能计算(HPC)系统及/或其部分。 100 may be, for example, the server system and / or high-performance computing (HPC) system and / or parts of the system. 尽管图1A及1B中所示的实例说明具有范纽曼(Von Neumann)架构的系统,但本发明的实施例可以非范纽曼架构实施,其可不包含通常与范纽曼架构相关联的一或多个组件(例如,CPU、ALU等)。 Although the examples shown in FIGS. 1A and 1B, a system having Fanniu Man described (Von Neumann) architecture, embodiments of the present invention may be non embodiment Fanniu Man architecture, which comprises not typically associated with one or more schema Fanniu Man component (e.g., CPU, ALU, etc.).

[0035]为明确起见,系统100己经简化以集中在与本发明特定相关的特征。 [0035] For clarity, a simplified system 100 has to focus on specific features relevant to the present invention. 存储器阵列130可为例如DRAM阵列、SRAM阵列、STT RAM阵列、PCRAM阵列、TRAM阵列、RRAM阵列、NAND快闪阵列及/或NOR快闪阵列。 The memory array 130 may be, for example, an array of DRAM, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array and / or NOR flash array. 阵列130可包括布置成由存取线(本文中可称为字线或选择线)耦合的行及由感测线(本文中可称为数据线或数字线)耦合的列的存储器单元。 Array 130 may be arranged to include the access line (may be referred to herein as a word line or select line) by a row of memory cells and sense lines (may be referred to herein as a data line or digit line) coupled to a column coupled. 尽管图1中展示单一阵列130,但实施例不限于此。 Although FIG. 1 shows in a single array 130, but the embodiment is not limited thereto. 举例来说,存储器装置120可包含若干阵列130 (例如, 若干DRAM单元库、NAND快闪单元库等)。 For example, the memory device 120 may comprise a plurality of array 130 (e.g., a plurality of DRAM cell library, the NAND flash cell library, etc.).

[0036] 存储器装置120包含用以锁存经由数据总线156 (例如,I/O总线)通过I/O电路144 提供的地址信号的地址电路142。 [0036] The memory device 120 includes a data bus 156 via a latch configured (e.g., I / O bus) address of the address signal circuit 142 is supplied through the I / O circuit 144. 状态及/或例外信息可从存储器装置120上的存储器控制器140提供到通道控制器143 (包含带外总线157),其又可从存储器装置120提供到主机110。 State and / or the exception information may be provided from the memory controller 120 on the memory device 140 to the channel controller 143 (comprising band bus 157), which in turn is supplied from the memory 120 to the host apparatus 110. 通过地址电路142接收地址信号,且通过行解码器146及列解码器152解码地址信号以存取存储器阵列130。 The address circuit 142 receives an address signal, and by the row decoder 146 and column decoder 152 decodes the address signals to access the memory array 130. 可通过使用感测电路150感测数据线上的电压及/或电流变化而从存储器阵列130读取数据。 Data may be read from the memory array 130 via voltage and / or current change sensing data lines 150 using the sensing circuit. 感测电路150可从存储器阵列130读取并锁存页(例如,行)数据。 The sensing circuit 150 may read from the memory array 130 and latch page (e.g., row) of data. I/O电路144可用于经由数据总线156与主机110进行双向数据通信。 I / O circuit 144 can be used for bidirectional data communication with the host 156 via a data bus 110. 写入电路148用以将数据写入到存储器阵列130。 The write circuit 148 to write data to the memory array 130.

[0037] 存储器控制器140 (例如,库控制逻辑及/或序列发生器)解码由控制总线154从主机110提供的信号。 Signal (e.g., bank control logic and / or sequencer) is decoded by the control bus 154 from the host 110 to provide [0037] the memory controller 140. 这些信号可包含用以控制对存储器阵列130执行的操作(包含数据读取、 数据写入及数据擦除操作)的芯片启用信号、写入启用信号及地址锁存信号。 These signals may include a chip enable signal for controlling the operation of the memory array 130 is performed (including data read, data write and data erase operation), the write enable signal and the address latch signals. 在各种实施例中,存储器控制器140负责执行来自主机110的指令。 In various embodiments, the memory controller 140 responsible for executing instructions from the host 110. 存储器控制器140可包含控制逻辑、序列发生器、状态机或某一其它类型的逻辑电路。 The memory controller 140 may comprise control logic, a sequencer, a state machine, or some other type of logic circuit. 控制器140可控制阵列(例如,存储器阵列130)中的移位数据(例如,右或左)。 The controller 140 may control the array (e.g., a memory array 130) shift data (e.g., right or left) of.

[0038] 下文进一步描述感测电路150的实例。 [0038] Examples of further sensing sensing circuit 150 described below. 举例来说,在若千实施例中,感测电路150可包括若干感测放大器及若干计算组件,其可用作且在本文中称为累加器且可用以(例如,对与互补数据线相关联的数据)执行逻辑运算。 For example, if one thousand in the embodiment, the sensing circuit 150 may include a plurality of sense amplifiers and a plurality of computing components, which can be used and is referred to herein as an accumulator and can be used to (for example, associated with complementary data lines data associated) performing a logic operation.

[0039] 在若干实施例中,感测电路150可用以使用存储在阵列130中的数据作为输入而执行逻辑运算,且将逻辑运算的结果存储回到阵列130而不经由感测线地址存取传送数据(例如,不触发列解码信号)。 [0039] In several embodiments, may be used to store data using a sensing circuit 150 in the array 130 as an input, performs a logic operation, and the result is stored back to the logical operation of the array 130 via the sense lines without access address transmitting data (e.g., does not trigger a column decode signal). 因而,各种计算功能可使用感测电路150且在感测电路150内执行, 而非(或结合)通过感测电路外部的处理资源(例如,通过与主机110相关联的处理器及/或定位在装置120上(例如,在控制器140上或别处)的其它处理电路,例如ALU电路)执行。 Accordingly, various computing functions using the sensing circuit 150 and executed within the sensing circuit 150, instead of (or in combination) through the external sensing circuit processing resources (e.g., by a processor 110 associated with the host and / or positioned on the device 120 (e.g., in the controller 140 or elsewhere) to other processing circuitry, such as circuit ALU) performs.

[0040] 在各种先前方法中,例如与操作数相关联的数据将经由感测电路从存储器读取且经由I/O线(例如,经由本地I/O线及/或全局I/O线)提供到外部ALU电路。 [0040] In various previous method, for example associated with the operands associated data read and via I / O lines (from the memory via the sensing circuitry, for example, via a local I / O lines and / or global I / O lines ) ALU supplied to an external circuit. 外部ALU电路可包含若干缓存器且将使用操作数执行计算功能,且结果将经由I/O线传送回到阵列。 ALU external circuit may comprise a plurality of buffers and the number of operations performed using the calculation function, and transmits the result via the I / O lines back to the array. 相比之下,在本发明的若干实施例中,感测电路150经配置以对存储在存储器阵列130中的数据执行逻辑运算且将结果存储回到存储器阵列130,而不启用耦合到感测电路150的I/O线(例如,本地I/O线)。 In contrast, in several embodiments of the present invention, the sensing circuit 150 is configured to perform a logic operation on the data stored in the memory array 130 and stores the result back to the memory array 130, coupled to the sensing without activating circuit I / O line 150 (e.g., a local I / O lines). 感测电路150可形成在与阵列的存储器单元的间距上。 The sensing circuit 150 may be formed on a pitch of the memory cell array. 额外外围感测放大器、缓存器、高速缓存及/或数据缓冲(例如,逻辑电路170)可耦合到感测电路150且可用以存储(例如,高速缓存及/或缓冲)本文中描述的运算的结果。 Additional peripheral sense amplifier, a buffer, a cache and / or data buffer (e.g., a logic circuit 170) may be coupled to the operation sensing circuit and is used to store (e.g., a cache and / or buffer) described herein 150 result.

[0041] 因而,在若干实施例中,阵列130及感测电路150外部的电路不必执行计算功能,这是因为感测电路150可执行适当逻辑运算以执行此类计算功能,而无需使用外部处理资源。 [0041] Accordingly, in several embodiments, the array 150 external circuit 130 and a sensing circuit having to perform a calculation function, because the sensing circuit 150 may perform the appropriate logic operation function to perform such calculation, without using an external process resources. 因此,感测电路150可用以至少在某种程度上恭维及/或取代此外部处理资源(或至少此外部处理资源的带宽消耗)。 Thus, the sensing circuit 150 may be used to compliment at least in part and / or substituted portions addition processing resources (or bandwidth consumption in addition at least part of the processing resources).

[0042] 然而,在若干实施例中,感测电路150可用以执行除由外部处理资源(例如,主机110)执行的逻辑运算外的逻辑运算(例如,以执行指令)。 [0042] However, in several embodiments, the sensing circuit 150 may be used to perform logical operations in addition to logical operations performed by an external processing resource (e.g., host 110) (e.g., to execute instructions). 举例来说,主机110及/或感测电路150可限于仅执行特定逻辑运算及/或特定数目个逻辑运算。 For example, the host 110 and / or sensing circuit 150 may be limited to performing only a specific logical operations and / or logical operations a particular number.

[0043]启用I/O线可包含启用(例如,接通)具有耦合到解码信号(例如,列解码信号)的栅极及耦合到所述I/O线的源极/漏极的晶体管。 [0043] Enable I / O line may comprise enabled (e.g., turned on) to the decoded signal having a coupled (e.g., column decode signal) and the gate of the transistor source is coupled to the I / O lines of the source / drain. 然而,实施例不限于不启用I/O线。 However, the embodiment is not limited to the embodiment does not enable I / O line. 举例来说, 在若干实施例中,感测电路(例如,15〇)可用以执行逻辑运算而不启用阵列的列解码线;然而,除传送回到阵列130之外,可启用本地I/O线以将结果传送到适合位置(例如,到外部缓存器)。 For example, in several embodiments, the sensing circuit (e.g., 15〇) may be used to perform logical operations does not enable the column decoder array lines; however, in addition to the transfer array 130 back outside, to enable the local I / O lines result to the appropriate location (e.g., outside the buffer).

[0044]图1B是根据本发明的若干实施例的呈包含经由通道控制器143耦合到主机11〇的多个存储器装置120-1、…、120-N的计算系统100的形式的另一设备架构的框图。 [0044] FIG. 1B is an embodiment according to several embodiments of the present invention comprises a form of a plurality of memory devices coupled to the host controller 143 via channel 11〇 120-1, ..., another form of a computing device 120-N of system 100 block diagram of the architecture. 在至少一个实施例中,通道控制器143可按集成方式以模块11S的形式耦合到多个存储器装置12〇-1、…、120-N,例如,形成在与多个存储器装置12〇-1、…、120-N的芯片上。 In at least one embodiment, the channel controller 143 may be integrated as a module coupled to a plurality of memory devices 11S 12〇-1, ..., 120-N, for example, formed in a plurality of memory devices 12〇-1 , ..., 120-N of the chip. 在替代实施例中, 通道控制器143可与主机110集成(如由虚线111说明),例如形成在与多个存储器装置12〇-1、…、120-N的芯片分开的芯片上。 In alternative embodiments, the channel controller 143 may be integrated with the host 110 (as illustrated by the dashed line 111), for example, is formed on 12〇-1, ..., 120-N of the plurality of separate chips chip memory devices. 如图1A中所描述,通道控制器143可经由地址及控制(A/ C)总线154耦合到多个存储器装置120-1、…、120-N中的每一个,其又可鍋合到主机110。 As described in Figure 1A, the channel controller 143 via address and control (A / C) bus 154 is coupled to a plurality of memory devices 120-1, ..., 120-N each of which in turn bonded to a host pot 110. 如图1A中所描述,通道控制器143还可经由数据总线156耦合到多个存储器装置丨加^、…、 120-N中的每一个,其又可耦合到主机110。 As described in Figure 1A, the channel controller 143 may also be coupled to a plurality of memory devices via a data bus Shu plus ^ 156, ..., 120-N each of which in turn is coupled to the host 110. 另外,通道控制器143可经由与高速接口(HSI) 目关联的约束外(〇〇B)总线157耦合到多个存储器装置120_丨、…、12〇_N中的每一个,所述高速界面(HSI) 141经配置以将状态、例外及其它数据信息报告到通道控制器143以与主机110交换。 Further, the channel controller 143 may be coupled via bus 157 mesh outer constraints associated with high-speed interface (the HSI) (〇〇B) to a plurality of memory devices 120_ Shu, ..., 12〇_N each of the high-speed interface (HSI) 141 to report the state, and exception information to the other data path 143 to the host controller 110 is configured to exchange. _5]如图1B中所示,通道控制器143可从与多个存储器装置120—丨、…、120_N中的每一个中的库仲裁器145相关联的高速接口(HSI) 141接收状态及例外信息。 [5] As shown in FIG. 1B, the channel controller 143 from the plurality of memory devices 120- Shu, ..., 145 associated 120_N in the library in each of the arbiter high speed interface (HSI) 141 receives state and Exception information. 在图1B的实例中,多个存储器装置120-1、…、120-N中的每一个可包含用以定序关于多个库(例如,Bank零(〇)、 Bank —(1)、…、Bank六⑹、Bank七⑺等)的控制及数据的库仲裁器145。 In the example of FIG. 1B, a plurality of memory devices 120-1, ..., 120-N each of which may comprise a plurality of libraries for sequencing on (e.g., zero Bank (square), Bank - (1), ... , library arbiter Bank six ⑹, Bank seven ⑺, etc.) and control data 145. 多个库Bank 〇、…、 Bank 7中的每一个可包含控制器140-1、…、140-7 (统称为140)及其它组件,包含存储器单元阵列13〇及感测电路15〇、逻辑电路170等,如结合图1A描述。 Bank square plurality of libraries, ..., Bank 7 may each include a controller 140-1, ..., 140-7 (collectively 140) and other components, including a memory cell array and sensing circuit 15〇 13〇, logic circuit 170, etc., as described in conjunction with FIG. 1A.

[0046]举例来说,多个存储器装置120-1、…、120-N中的多个库(例如,Bank 0、…、Bank7) 中的每一个可包含用以锁存经由数据总线156(例如,I/O总线)通过I/O电路144提供的地址信号的地址电路142。 [0046] For example, 120-1, ..., 120-N in a plurality of libraries (e.g., Bank 0, ..., Bank7) each of the plurality of memory devices may include a bus 156 via a data latch for ( For example, I / O bus) address of the address signal circuit 142 is supplied through the I / O circuit 144. 状态及/或例外信息可使用〇OB总线157从存储器装置12〇上的控制器140提供到通道控制器143,又可从多个存储器装置uo-i、…、U0-N提供到主机110。 State and / or the exception information bus 157 may be used 〇OB supplied from the controller 140 to the memory device 12〇 channel controller 143, in turn from a plurality of memory devices uo-i, ..., U0-N to the host 110. 对于多个库(例如,Bank 0、…、Bank 7)中的每一个,可通过地址电路142接收地址信号,且通过行解码器146及列解码器152解码地址信号以存取存储器阵列130。 For multiple libraries (e.g., Bank 0, ..., Bank 7) each of a, by the address circuit 142 receives an address signal, and by the row decoder 146 and column decoder 152 decodes the address signals to access the memory array 130. 可通过使用感测电路150感测数据线上的电压及/或电流变化而从存储器阵列130读取数据。 Data may be read from the memory array 130 via voltage and / or current change sensing data lines 150 using the sensing circuit. 感测电路150可从存储器阵列13〇读取并锁存页(例如,行)数据。 The sensing circuit 150 may read from the memory array 13〇 and latch page (e.g., row) of data. I/O电路144可用于经由数据总线156与主机110进行双向数据通信。 I / O circuit 144 can be used for bidirectional data communication with the host 156 via a data bus 110. 写入电路148用以将数据写入到存储器阵列130,且OOB总线157可用以将状态、例外及其它数据信息报告到通道控制器143。 The write circuit 148 to write data to the memory array 130, and the OOB bus 157 may be used to report the state, and exception information to the other data path controller 143.

[0047]通道控制器143可包含一或多个局部缓冲器161以接收程序指令,且可包含逻辑160以分配每一相应库的阵列中的多个位置(例如,子阵列或子阵列的部分)以存储与多个存储器装置120-1、…、120-N中的每一个的操作相关联的各个库的程序指令,例如,库命令及自变量(PIM命令)。 [0047] The channel controller 143 may include one or more local buffer 161 to receive program instructions, and may comprise logic 160 to allocate a plurality of arrays each respective positions in the library (e.g., sub-array or sub-array portion ) to store a plurality of memory devices 120-1, ..., 120-N of each of the operating instructions associated with each library program, e.g., library commands and arguments (PIM command). 通道控制器143可将程序指令(例如,PIM命令)发送到多个存储器装置120-1、…、120-N且将所述程序指令存储在存储器装置120-1、…、120-N的给定库内。 Channel controller 143 may be programmed (e.g., PIM command) to the plurality of memory devices 120-1, ..., 120-N and the 120-1, ..., 120-N to program instructions stored in said memory means given library.

[0048] 如结合图1A所描述,存储器阵列130可为例如DRAM阵列、SRAM阵列、STT RAM阵列、 PCRAM阵列、TRAM阵列、RRAM阵列、NAND快闪阵列及/或NOR快闪阵列。 [0048] As described in conjunction with FIG. 1A, the memory array 130 may be, for example, an array of DRAM, SRAM array, STT RAM array, the PCRAM array, the TRAM array, a RRAM array, the NAND flash array and / or NOR flash array. 阵列130可包括布置成由存取线(本文中可称为字线或选择线)耦合的行及由感测线(本文中可称为数据线或数字线)耦合的列的存储器单元。 Array 130 may be arranged to include the access line (may be referred to herein as a word line or select line) by a row of memory cells and sense lines (may be referred to herein as a data line or digit line) coupled to a column coupled.

[0049] 如图1A中,与给定存储器装置120-1、…、120-N中的特定库Bank 0、…、Bank 7相关联的控制器140 (例如,库控制逻辑及/或序列发生器)可解码由控制总线154从主机110提供的信号。 [0049] As shown in FIG. 1A, with a given memory device 120-1, ..., 120-N in a particular bank Bank 0, ..., Bank 7 associated with the controller 140 (e.g., bank control logic and / or sequence generation device) may decode the control signal supplied from the host bus 154 110. 这些信号可包含用以控制对存储器阵列130执行的操作(包含数据读取、数据写入及数据擦除操作)的芯片启用信号、写入启用信号及地址锁存信号。 These signals may include a chip enable signal for controlling the operation of the memory array 130 is performed (including data read, data write and data erase operation), the write enable signal and the address latch signals. 在各种实施例中,控制器140负责执行来自主机110的程序指令。 In various embodiments, the controller 140 is responsible for executing program instructions from the host 110. 且如上述,控制器140可包含控制逻辑、序列发生器、状态机等,以控制使用感测电路(在图1A中展示为150)执行逻辑运算。 And as described above, the controller may include control logic 140, a sequencer, a state machine, used to control the sensing circuit (shown as 150 in FIG. 1A) for performing logic operations. 举例来说,控制器140可控制阵列(例如,图1A中的存储器阵列130)中的移位数据(例如,右或左)。 For example, the controller 140 may control an array (e.g., a memory array 130 of FIG. 1A) shift data (e.g., right or left) of.

[0050]图1C是根据本发明的若干实施例的存储器装置的库121-1的框图。 [0050] FIG 1C is a block diagram of a memory device embodiment library 121-1 according to several embodiments of the present invention. 即,库W1-1可表示存储器装置的实例库,例如图1B中所示的Bank 0、…、Bank 7 (121-0、…、121-7)。 That is, the library may represent examples of W1-1 bank memory device, for example, Bank 0 shown in FIG. 1B, ..., Bank 7 (121-0, ..., 121-7). 如图1C中所示,库架构可包含多个主存储器列(水平展示为X),例如在实例DRAM库中16,384个歹!J。 Shown in Figure 1C, the database schema may comprise a plurality of columns of a main memory (shown as X-level), for example, in the example of the DRAM banks 16,384 bad! J. 另外,库121-1可分成由用于数据路径的放大区域分离的区段123-1、123-2、…、123-N。 Further, libraries 121-1 may be divided into regions separated by the data path for amplifying section 123-1,123-2, ..., 123-N. 库区段U3-1、…、123-N中的每一个可包含多个行(垂直展示为Y),例如,在实例DRAM库中每一区段可包含16,384个行。 Reservoir section U3-1, ..., 123-N may each comprise a plurality of rows (shown as perpendicular to the Y), for example, in the example of DRAM banks each section may contain 16,384 lines. 实例实施例不限于此处描述的列及行的实例水平及/或垂直定向或其实例数目。 Examples of horizontal rows and columns described embodiment is not limited to the example embodiments herein and / or vertical orientation, or the number of instances.

[0051]如图1C中所示,库架构可包含耦合到库区段123-1、…、123-N的感测电路及额外逻辑电路15〇/170,包含感测放大器、缓存器、高速缓存及数据缓冲。 [0051] As shown in Figure 1C, the database schema may be coupled to the reservoir area comprises a segment 123-1, ..., 123-N of the sensing circuit and additional logic circuit 15〇 / 170, comprising a sense amplifier, a buffer, a high-speed data caching and buffering. 感测电路及额外逻辑电路150/170可表示与图1A中所示的阵列130相关联的感测电路150及额外逻辑电路,且可提供^图1A中的存储器控制器140相关联的对高速缓存171的额外高速缓存。 A sensing circuit and additional logic circuitry 150/170 may represent a sense circuit 150 and additional logic circuitry and the array 130 shown in FIG. 1A associated ^ and may provide the memory controller of FIG. 1A 140 associated with the high-speed additional cache buffer 171. 此外,如图1C中所示,库架构可库控制140,其可表示图1A中所示的存储器控制器140。 Further, as shown in FIG 1C library architecture library control 140, which may represent the memory controller 140 shown in FIG. 1A. 在实例中,图1C中所示的库控制可表示由图1A中所示的存储器控制器140具体实施且包含于所述存储器控制器140中的功能性。 In an example, the library shown in FIG. 1C shows a specific embodiment may be controlled by the memory controller 140 shown in FIG. 1A and included in the functionality of the memory controller 140.

[0052]图1D是根据本发明的若干实施例的存储器装置的库121的另一框图。 [0052] FIG. 1D is a block diagram of another library 121 according to the present invention, several embodiments of a memory device embodiment. 举例来说,库121可表示存储器装置的实例库,例如图1B中所示的Bank 0、…、Bank 7(121_0、...、121-7)。 For example, the library 121 may represent examples of the library memory devices, e.g. Bank 0 shown in FIG. 1B, ..., Bank 7 (121_0, ..., 121-7). 如图1D中所示,库架构可包含耦合存储器控制器(例如,库控制/序列发生器140)的地址/控制(A/C)路径(例如,总线I53)。 As shown in FIG. 1D, the database schema may comprise a memory controller coupled (e.g., library control / sequencer 140) address / control (A / C) paths (e.g., bus I53). 再次,在实例中,图1D中所示的库控制/序列发生器140可表示由图1A及1B中所示的存储器控制器/序列发生器140具体实施且包含于所述存储器控制器/序列发生器140中的功能性的至少一部分。 Again, in the example, the library control shown in FIG. 1D / sequencer 140 may be represented by a particular embodiment of the memory controller shown in FIGS. 1A and 1B / sequencer 140 included in the memory controller and / sequences at least a part of the functionality of the generator 140. 也如图1D中所示,库架构可包含数据路径(例如,总线155),其耦合到指令(例如,程序指令(PIM命令))读取路径中的多个控制/数据缓存器且耦合到特定库121中的多个库区段(例如,库区段123)。 As also shown in FIG. 1D, the database schema may include data paths (e.g., bus 155), coupled to the plurality of control instructions (e.g., program instructions (PIM command)) in the read path / coupled to the data buffer and Reservoir plurality of segments (e.g., segment Reservoir 123) in a particular bank 121.

[0053]如图1D中所不,库区段123进一步可细分成多个子阵列125-1、…、125-N,其再次由如图1B中所示且结合图2到4进一步描述的多个感测电路及额外逻辑电路150/170分离。 [0053] FIG. 1D No Reservoir section 123 is further subdivided into a plurality of sub-arrays 125-1, ..., 125-N, which is again a shown in FIG. 1B and further described in conjunction with FIGS. 2 to 4 sensing circuits and a plurality of additional logic circuitry 150/170 separation. 在一个实例中,库区段121可分成十六(16)个子阵列。 In one example, the reservoir area 121 may be divided into segments sixteen (16) sub-arrays. 然而,实施例不限于此实例数目。 However, embodiments are not limited the number of instances.

[0054]图1D说明程序指令高速缓存171,其与库的控制器140相关联且耦合到写入路径149及库123中的子阵列125_1、…、125_N中的每一个。 [0054] FIG. 1D illustrate program instruction cache 171, the controller 140 with the library and associated write path 149 is coupled to the library 123 and sub-array 125_1, ... 125_N in each. 替代地或额外地,图1A中所示的逻辑电路17〇可用作例如用以在特定库本地(“在间距上”)高速缓存及/或重新高速缓存所检索的指令的指令高速缓存。 Alternatively or additionally, the logic circuit shown in FIG. 1A 17〇 useful in a particular bank, for example, instructions to the local ( "on pitch") cache and / or re-cache the retrieved instruction cache. 在至少一个实施例中,多个子阵列I25-1、…、125-N及/或多个子阵列的部分可称为用于将程序指令(例如,PM命令)及/或常数数据存储到存储器装置中的库123的多个位置。 In at least one embodiment, the portion of the plurality of sub-arrays I25-1, ..., 125-N and / or sub-arrays may be referred to as a program instruction (e.g., PM command) and / or the constant data stored in the memory means the library 123 is a plurality of positions.

[0055]根据本发明的实施例,图1D中所示的控制器140 (例如,存储器控制器)经配置以从主机(例如,图1A中的主机110)接收指令块及/或常数数据。 [0055] According to an embodiment of the present invention, shown in FIG. 1D controller 140 (e.g., memory controller) to the host (e.g., host 110 of FIG. 1A) receives the instruction blocks and / or constant data are configured. 或者,可在控制器140处从与主机110集成或与主机分离(例如,以模块II8的形式与多个存储器装置120-1、…、120-N集成, 如图1B中所示)的通道控制器143接收指令块及/或常数数据。 Alternatively, the passage 140 may be integrated with the host 110 or separated from the host (e.g., in the form of a plurality of modules II8 memory devices 120-1, ..., 120-N integrated, as shown in FIG. 1B) in the controller The controller 143 receives instruction blocks and / or constant data.

[0056]指令块及/或数据可包含多个程序指令(例如,PIM命令)及/或常数数据(例如,经设定用于PIM计算的数据)。 [0056] instruction blocks and / or data may comprise a plurality of program instructions (e.g., command PIM) and / or the constant data (e.g., by setting a PIM calculated data). 根据实施例,存储器控制器140经配置以将来自主机11〇及/或通道控制器143的指令块及/或常数数据存储在阵列(例如,图1A中所示的阵列130)及/或库(例如,图1B、1C及1D中所示的库121-0、…、121-7)的(图1D中所示的123)中。 According to an embodiment, the memory controller 140 is configured to 11〇 from the host and / or the channel controller instruction block 143 and / or constant data stored in the array (e.g., array shown in FIG. 1A 130) and / or libraries (e.g., the library shown in FIG. 1B, 1C and 1D 121-0, ..., 121-7) (123 shown in FIG. 1D) in. 存储器控制器140进一步经配置以例如包含呈硬件电路及/或特定应用集成电路(ASIC)的形式的逻辑,以接收程序指令且执行所述程序指令以使用感测电路(包含计算组件(例如在图1A中展示为150的感测电路及图2及3中的计算组件231及331)执行逻辑运算。 The memory controller 140 further includes, for example in the form of a logical hardware circuits and / or application specific integrated circuit (ASIC) is to receive and execute the program instructions are configured to use the program instructions sensing circuit (computing component comprises (e.g. Figure 1A shows a sensing circuit of FIG. 2 and 3, and the computing component 231 and 150 331) performing a logic operation.

[0057] 在图1D的实例实施例中,控制器140经配置以使用DRAM协议及DRAM逻辑及电接口以从主机110及/或通道控制器143接收程序指令及/或常数数据,且执行程序指令及/或使用常数数据以用感测电路15〇、250及/或350的计算组件执行逻辑运算。 [0057] embodiment, the controller 140 is configured to use protocol DRAM and DRAM-logic and the electrical connection to 110 and / or channel controller 143 receives program instructions and / or constant data from the host, and executes the program in the example embodiment of FIG. 1D instructions and / or 15〇 a sensing circuit, a computing component 250 and / or 350 performing a logic operation using a constant data. 在控制器140处接收且由控制器140执行的程序指令及/或常数数据可由程序设计师预解析(例如,预定义)及/ 或提供到主机110及/或通道控制器143。 Received and executed by the controller 140 of the controller 140 program instructions and / or data may be constant preresolved designer program (e.g., predefined) and / or to the host 110 and / or channel controller 143.

[0058] 在一些实施例中,如图1B中所见,存储器单元阵列(图1A中的130)包含存储器单元120-1、…、120-N的多个库,且存储器装置120包含耦合到所述多个库120-1、…、120-N中的每一个的库仲裁器145。 [0058], as seen in FIG. 1B, in some embodiments, the memory cell array (130 in FIG. 1A) includes memory cells 120-1, ..., 120-N of the plurality of libraries, and coupled to the memory device 120 includes the plurality of libraries 120-1, ..., each gallery arbiter 145 ... 120-N. 在此类实施例中,每一库仲裁器经配置以从库仲裁器145接收与特定库相关的指令块及/或常数数据。 In such embodiments, each bank arbiter configured to instruct arbiter 145 receives a block from a library associated with a particular database and / or constant data. 接着,控制器140可将所接收的指令块及/或常数数据存储到如由主机110及/或通道控制器143分配的特定库的多个位置。 Next, the controller 140 may command the received block and / or constant data stored in the database as a plurality of positions by a particular host 110 and / or controller 143 assigned channels. 举例来说,主机110及/或通道控制器143经配置以对库仲裁器145的多个位置进行地址翻译以指派给存储器装置120 的库。 For example, the host 110 and / or channel controller 143 is configured to perform address translation to a plurality of positions in a database arbiter 145 assigned to the memory device 120 of the library. 在至少一个实施例中,如图1D中所示,多个位置包含DRAN库121-1、…、121-7中的若干子阵列125-1、…、125-N及/或所述若干子阵列的部分。 In at least one embodiment, as shown in FIG. 1D, a plurality of locations comprising the library DRAN 121-1, ..., a plurality of sub-arrays 121-7 125-1, ..., 125-N and / or the number of sub portion of the array.

[0059] 根据实施例,每一存储器控制器140可经配置以(例如在A/C总线154上)从主机110 及/或通道控制器143接收指令,以开始执行接收到给定库121-1、…、121-7的指令块。 [0059] According to an embodiment, each memory controller 140 may be configured to (e.g. on the A / C bus 154) from and / or host 143 receives the command channel controller 110 to begin receiving the given library 121- 1, ..., 121-7 of the instruction block. 存储器控制器140经配置以(例如,在控制及数据缓存器151的读取数据路径155上)从特定库的多个位置检索指令,且执行程序指令以使用感测电路150的计算组件执行逻辑运算。 The memory controller 140 is configured to (e.g., on a read data path 155 and control the data buffer 151), and executes a plurality of program instructions from a specific location search command to calculate a component library using the sensed logic circuit 150 operations. 控制器140可在特定库本地(例如,在指令高速缓存171及/或逻辑电路170中)高速缓存所检索的程序指令,以处置指令块执行内所含有的分支、循环、逻辑及数据操作。 The controller 140 may (e.g., in the instruction cache 171 and / or logic circuitry 170) the retrieved program instruction cache in a particular library locally to the branch instruction block execution of handling contained, cycle, logic, and data manipulation. 且控制器140可重新高速缓存所检索的指令以重复使用。 And the controller 140 may re-caching instructions retrieved for reuse. 因此,DRAM装置上的专用程序指令存储器(高速缓存)的大小不必增加以将经预解析程序指令存储在具备PIM能力的DRAM装置(PIMRAM)上。 Thus, the size of the DRAM devices dedicated program instruction memory (cache) to the DRAM device without having to increase the pre-parsed program instructions stored in the PIM includes the capability (PIMRAM).

[0060] 在一些实施例中,多个存储器装置120-1、…、120-N耦合到主机110及/或通道控制器143。 [0060] In some embodiments, a plurality of memory devices 120-1, ..., 120-N coupled to a host 110 and / or channel controller 143. 此处,主机110及/或通道控制器143可例如经由数据总线156将指令块发送到多个存储器装置120-1、…、120-N的适当库仲裁器145-1、…、145-N。 Here, the host 110 and / or channel controller 143 may be, for example, instruction blocks transmitted via the data bus 156 to a plurality of memory devices 120-1, ..., 120-N of the appropriate library arbiter 145-1, ..., 145-N .

[0061]此外,根据实施例,存储器控制器140经配置使得在存储器控制器140 (例如,并行) 执行先前接收的指令块时,库121可接收与所述特定库相关的程序指令的后续指令块且将所接收的指令块中的指令存储到所述特定库的多个位置。 [0061] Further, according to an embodiment, the memory controller 140 is configured such that the memory controller 140 (e.g., parallel) execution of the instruction block previously received, program library 121 may receive associated with the particular instruction subsequent instructions library and the block store instruction received block of instructions to a plurality of positions of the specific library. 因此,本文中描述的实施例无需等待将从主机110及/或通道控制器143接收的未来或下一程序指令集(例如,PIM命令)。 Accordingly, the embodiments described herein without waiting from the host 110 and / or future program or channel controller 143 receives the next set of instructions (e.g., the PIM command). 代替性地,本文中描述的设备及方法装置有利于具备PIM能力的DRAM装置中针对程序指令(例如,PIM命令)的后备存储,且可有利于在执行先前接收的指令块时将后续指令块预写入到所分配位置中,以有利于开始具备PIM能力的DRAM装置中的未来计算。 In place of, the apparatus and methods herein described apparatus facilitates DRAM device comprising PIM-capable backing store for the program instructions (e.g., PIM command), and may facilitate the implementation of the previously received block of instructions subsequent instruction blocks pre-written to the assigned position to start facilitate future DRAM device includes a calculation ability PIM.

[0062] 如读者将了解,且如图2到4的实例中更详细描述,存储器控制器140经配置以通过控制感测电路150 (包含计算组件251及/或35 1)实施例如△勵、01?、冊1\熟即、冊1?及\01?逻辑函数的逻辑运算而控制程序指令(例如,PIM命令)的执行。 [0062] As the reader will appreciate, and as shown in Example 2-4 described in more detail, the memory controller 140 is configured to sense the control circuit 150 (comprising a computing component 251 and / or 351) Reed embodiment △ e.g., 01 ?, volume 1 \ cooked namely, books 1? and \ 01? logic arithmetic logic functions and control program instructions (eg, PIM command) is executed. 另外,存储器控制器140经配置以控制感测电路150以执行非布尔逻辑运算(包含复制、比较及擦除操作)作为执行程序指令(例如,PIM命令)的部分。 Further, the memory controller 140 configured to control the sensing circuit 150 to perform a non-Boolean logic operation (including copying, comparing, and erasing operations) as an executing program instructions (e.g., the PIM command) portion.

[0063]图2是说明根据本发明的若干实施例的感测电路250的示意图。 [0063] FIG. 2 is a diagram illustrating an example of a sensing circuit 250 according to several embodiments of a schematic diagram of the present invention. 感测电路250可对应于图1A及1B中所示的感测电路150。 The sensing circuit 250 may correspond to that shown in FIGS. 1A and 1B a sensing circuit 150. 感测电路25〇的感测放大器206可对应于图2中所示的感测放大器206,且感测电路25〇的计算组件231可对应于例如图1A中所示的感测电路(包含计算组件)150。 25〇 sensing circuit 206 may sense amplifier shown in FIG. 2 correspond to the sense amplifier 206, and the sensing circuit 25〇 computing component 231 may correspond to the sense circuit shown in FIG. 1A, for example, (comprising calculation component) 150.

[0064]存储器单元包括存储元件(例如,电容器)及存取装置(例如,晶体管)。 [0064] The memory cell includes a memory element (e.g., a capacitor) and access devices (e.g., transistors). 举例来说, 第一存储器单元包括晶体管2〇2_1及电容器203-1,且第二存储器单元包括晶体管202-2及电容器2〇3_2,等等。 For example, the first memory cell comprises a transistor and a capacitor 2〇2_1 203-1, and the second memory cell includes a transistor and a capacitor 2〇3_2 202-2, and the like. 在此实例中,存储器阵列230是1T1C (一个晶体管一个电容器)存储器单元的DRAM阵列。 In this example, the memory array is a DRAM array 230 1T1C (one transistor one capacitor) of the memory cell. 在若千实施例中,存储器单元可为破坏性读取存储器单元(例如,读取存储在单元中的数据破坏所述数据使得最初存储在单元中的数据在读取之后被刷新)。 Embodiment, the memory cell may be a destructive read memory cell (e.g., reading data stored in the data unit such that damage to data stored in the first unit is refreshed after reading) In the embodiment, if one thousand.

[0065]存储器阵列230的单元可布置成由字线2〇4-X(行X)、204-Y (行Y)等耦合的行及由互补感测线对(例如,数据线DIGIT (n-1) /DIGIT (n-1) _、DIGIT (n) /DIGIT ⑹—、DIGIT (n+1) / DIGIT (n+1) _)耦合的列。 [0065] The memory cell array 230 may be arranged by the word line 2〇4-X (line X), 204-Y (line Y) and the like coupled by a row of complementary sense lines (e.g., data lines DIGIT (n -1) / DIGIT (n-1) _, DIGIT (n) / DIGIT ⑹-, DIGIT (n + 1) / DIGIT (n + 1) _) coupled columns. 对应于每一对互补感测线的个别感测线还可分别称为数据线205-1⑼及2〇5_2(Dj。尽管图2中仅展示一对互补数据线,但本发明的实施例不限于此,且存储器单元阵列可包含存储器单元及/或数据线的额外列(例如,4,0%个、8,192个、16,384个等)。 Corresponding to each individual sense line of the sense line may also complement are referred to as data lines and 205-1⑼ 2〇5_2 (Dj. Although Figure 2 shows only one pair of complementary data lines, embodiments of the present invention do not limited thereto, and may include a memory cell array of memory cells, and / or additional data lines (e.g., a 4,0%, 8,192, 16,384, etc.).

[0066]存储器单元可耦合到不同数据线及/或字线。 [0066] The memory unit may be coupled to different data lines and / or word lines. 举例来说,晶体管202-1的第一源极/ 漏极区域可耦合到数据线2〇5_1 (D),晶体管2〇2_1的第二源极/漏极区域可耦合到电容器2〇3_1,且晶体管202-1的栅极可耦合到字线204-X。 For example, a first source / drain region of the transistor 202-1 may be coupled to a data line 2〇5_1 (D), a second transistor 2〇2_1 source / drain regions may be coupled to the capacitor 2〇3_1, and the gate of the transistor 202-1 may be coupled to a word line 204-X. 晶体管202-2的第一源极/漏极区域可耦合到数据线2〇5_2 (D_),晶体管2〇2_2的第二源极/漏极区域可耦合到电容器203-2,且晶体管202-2的栅极可耦合到字线204-Y。 A first source of the transistor 202-2 / drain regions can be coupled to a data line 2〇5_2 (D_), a second transistor 2〇2_2 source / drain region 203-2 may be coupled to the capacitor, and transistors 202- the gate electrode 2 may be coupled to a word line 204-Y. 单元板(如图2中所示)可耦合到电容器203-1及203-2 中的每一个。 Cell board (shown in FIG. 2) may be coupled to each of the capacitors 203-1 and 203-2 of. 单元板可为在各种存储器阵列配置中可施加参考电压(例如,接地)的共同节点。 Cell plate can be applied to a reference voltage (e.g., ground) of the common node in various memory array configurations.

[0067]根据本发明的若干实施例,存储器阵列23〇耦合到感测电路250。 [0067] According to several embodiments of the present invention, the memory array is coupled to the sensing circuit 250 23〇. 在此实例中,感测电路250包括对应于存储器单元的相应列(例如,耦合到相应互补数据线对)的感测放大器206及计算组件2:31。 In this example, the sensing circuit 250 includes a corresponding column of memory cells corresponding to (e.g., coupled to respective complementary pairs of data lines) of the sense amplifier 206 and computing components 2:31. 感测放大器206可耦合到互补感测线对2〇5_1及205-2。 The sense amplifier 206 can be coupled to a complementary pair of sense lines 205-2 and 2〇5_1. 计算组件231可经由传递门207-1及207-2耦合到感测放大器206。 Computing component 231 may be coupled via a transfer gate 207-2 to 207-1 and the sense amplifier 206. 传递门207-1及207-2的栅极可耦合到逻辑运算选择逻辑213。 The gate of transfer gate 207-1 and 207-2 may be coupled to the selection logic 213 logic operation.

[0068]逻辑运算选择逻辑213可经配置以包含:传递门逻辑,其用于控制传递门以将未转置的互补感测线对耦合在感测放大器206与计算组件231之间(如图2中所示);及/或交换门逻辑,其用于控制交换门以将经转置的互补感测线对耦合在感测放大器206与计算组件231 之间。 [0068] The logical operation selection logic 213 may be configured to include: transfer gate logic, for controlling the transfer gate to the non-transposed complementary sense line pair is coupled between sense amplifier 206 and computing component 231 (FIG. in Figure 2); and / or swap gate logic for controlling the switching door is transposed complementary sense line pair is coupled between sense amplifier 206 and computing component 231. 逻辑运算选择逻辑213还可耦合到互补感测线对205-1及205-2。 Logical operation selection logic 213 may also be coupled to a complementary pair of sense lines 205-1 and 205-2. 逻辑运算选择逻辑213可经配置以基于选定逻辑运算而控制传递门207-1及207-2的连续性,如下文针对逻辑运算选择逻辑413的各种配置所详细描述。 Logic operation selection logic 213 may control the continuity of the transfer gate 207-1 and 207-2 are configured based on the selected logical operation, as described in detail below for the various configurations of the logical operation logic 413.

[0069]感测放大器2〇e可经操作以确定存储在选定存储器单元中的数据值(例如,逻辑状态)。 [0069] The sense amplifier 2〇e may be operable to determine a data value stored in the selected memory cell (e.g., logic state). 感测放大器2〇6可包括交叉耦合锁存器,其在本文中可称为主要锁存器。 2〇6 may include a sense amplifier cross-coupled latch, which may be referred to herein as primary latch. 在图2中说明的实例中,对应于感测放大器2〇6的电路包括锁存器215,所述锁存器215包含耦合到一对互补数据线D 205-1及D_2〇5_2的四个晶体管。 In the example illustrated in FIG. 2, corresponding to the sense amplifier circuit includes a latch 215 2〇6, the latch 215 is coupled to a pair comprises complementary data lines D 205-1 and the four D_2〇5_2 transistors. 然而,实施例不限于此类实例。 However, the embodiment is not limited to such example. 锁存器215可为交叉耦合锁存器(例如,例如n沟道晶体管(例如,NM0S晶体管)227-1及227-2的一对晶体管的栅极与例如P沟道晶体管(例如,PM0S晶体管)229-1及229_2的另一对晶体管的栅极交叉耦合)。 The latch 215 may be a cross-coupled latch (e.g., for example, n-channel transistor (e.g., transistor NM0S) of the gate of a pair of transistors, for example, 227-1 and 227-2 and the P-channel transistor (e.g., PMOS transistors ) 229-1 and another gate 229_2 cross-coupled pair of transistors). 包括晶体管2W-1、227_2、229_1及229-2的交叉耦合锁存器215可称为主要锁存器。 2W-1,227_2,229_1 includes transistors 229-2 and a cross-coupled latch 215 may be referred to as a primary latch.

[0070]在操作中,当感测(例如,读取)存储器单元时,数据线205—i (D)或2〇5_2 (DJ中的一个上的电压将略大于数据线2〇5_1 〇))或2〇5-2(D_)中的另一个上的电压。 [0070] In operation, upon sensing (e.g., read) of memory cells, the data lines 205-i (D) or 2〇5_2 (DJ voltage on a data line will be slightly larger than 2〇5_1 square) ) or the voltage on the other (D_) in 2〇5-2. 可驱使A^T信号及RNL*信号降低以启用(例如,触发)感测放大器2〇6。 A ^ T can drive signal and the RNL * signal is lowered to enable (e.g., trigger) 2〇6 sense amplifier. 与pM〇S晶体管的一个相比,具有较低电压的数据线2〇5_1 〇)或205_2 (D_)将在更大程度上接通pM0S晶体管229_丄或229-2中的另一个,借此驱使具有较高电压的数据线2〇5-1 (D)或205-2 (D_)升高到大于另一数据线205-1⑼或205-2 (D_)经驱使而升高的程度。 PM〇S compared with a transistor, a data line having a lower voltage 2〇5_1 square) or 205_2 (D_) will turn on the other transistor 229_ pM0S 229-2 in the Shang or greater extent, by this has driven the data line high voltage 2〇5-1 (D) or 205-2 (D_) rises above the other data line driven by the degree 205-1⑼ or 205-2 and elevated (D_). -

[0071]类似地,与NM0S晶体管227-1或M7-2中的一个相比,具有较高电压的数据线205—丄(D)或205-2 (Dj将在更大程度上接通NM〇S晶体管227-1或227-2中的另一个,借此驱使具有较低电压的数据线205-1⑼或205-2 (DJ)降低到大于另一数据线205-1 (D)或205-2 (D_)经驱使而降低的程度。因此,在短暂延迟之后,具有略大电压的数据线205-1 (D)或205-2 (D_) 通过流出晶体管(source transistor) 211驱动到供应电压的电压Vcc,且另一数据线205-1 ⑼或205_2 (D—)通过汲入晶体管(sink transistor) 213驱动到参考电压的电压(例如,接地)。因此,交叉耦合NM0S晶体管227-1及227-2以及PM0S晶体管229-1及229-2用作感测放大器对,其放大数据线2〇5_1 (D)及2〇5_2 (D_)上的差分电压且操作以锁存从选定存储器单元感测的数据值。如本文中所使用,感测放大器206的交叉耦合锁存器可称为主要锁存器215。 [0072]实施例不限于 [0071] Similarly, as compared with NM0S transistors M7-2 one or 227-1, the data line having a higher voltage Shang 205- (D) or 205-2 (Dj will be turned to a greater extent NM another 〇S of transistor 227-1 or 227-2, thereby driving the data line having a lower voltage 205-1⑼ or 205-2 (DJ) than the other to reduce the data lines 205-1 (D) or 205 and data line driven by the degree of reduction (D_) -2. Thus, after a short delay, a voltage having a slightly larger 205-1 (D) or 205-2 (D_) through the outflow driving transistor (source transistor) 211 to a supply voltage Vcc voltage, and the other data line 205-1 ⑼ or 205_2 (D-) is driven by the drain transistor (sink transistor) 213 to the reference voltage (e.g., ground). Accordingly, cross-coupled transistors 227-1 NM0S transistors 229-1 and 227-2 and 229-2 and PM0S as a sense amplifier, the differential voltage on the latch and operative to amplify the data lines 2〇5_1 (D) and 2〇5_2 (D_) selected from embodiment is not limited to the data value of the memory cell is sensed. as used herein, the sense amplifier cross-coupled latch 206 may be referred to as a main latch 215. [0072] embodiment 2中说明的感测放大器206配置。作为实例,感测放大器206可为电流模式感测放大器及/或单端感测放大器(例如,耦合到一个数据线的感测放大器)。此外, 本发明的实施例不限于例如图2中所示的架构的折叠数据线架构。 Described in the second sense amplifier 206 is configured. As an example, the sense amplifier 206 may be a current mode sense amplifier and / or single-ended sense amplifier (e.g., coupled to a data line sense amplifier). Further, the present invention the embodiments are not limited to the data line architectures such as folding architecture shown in FIG. 2.

[0073]感测放大器206可连同计算组件231 —起操作以使用来自阵列的数据作为输入而执行各种逻辑运算。 [0073] The sense amplifier 206 can be calculated together with the assembly 231-- operation as an input from a variety of logical operations performed using data from the array. 在若干实施例中,可将逻辑运算的结果存储回到阵列而不经由数据线地址存取传送数据(例如,不触发列解码信号使得数据经由本地I/O线传送到阵列及感测电路外部的电路)。 In several embodiments, the result of the logic operation may be stored without access transfer data back to the array via a data line address (e.g., does not trigger the column decoder so that the data signal to the external measuring circuit array and sense via the local I / O lines circuitry). 因而,与各种先前方法相比,本发明的若干实施例可能够使用较少电力执行逻辑运算及其相关联的计算功能。 Thus, compared to a variety of methods previously, several embodiments of the present invention may be capable of performing a logic operation using less power and associated calculation function. 另外,由于若干实施例无需跨〗/〇线传送数据以执行计算功能(例如,在存储器与离散处理器之间),因此与先前方法相比,若干实施例可实现增加的并行处理能力。 Further, since the data need not be transmitted across a plurality〗 / square line embodiment executes calculation function (e.g., between the memory and discrete processors), as compared with previous methods, several embodiments may be implemented to increase the parallel processing capability.

[0074] 感测放大器206进一步可包含平衡电路214,其可经配置以平衡数据线205-1 〇)及205-2 (DJ。在此实例中,平衡电路214包括耦合在数据线205-1⑼与205-2 (D_)之间的晶体管224。平衡电路214还包括晶体管225-1及225-2,其各自具有耦合到平衡电压(例如,VDD/2) 的第一源极/漏极区域,其中VDD是与阵列相关联的供应电压。晶体管225-1的第二源极/漏极区域可耦合数据线205-1 (D),且晶体管225-2的第二源极/漏极区域可耦合数据线205-2 (D_)。晶体管224、225-1及225-2的栅极可耦合在一起且耦合到平衡(EQ)控制信号线226。因而,启动EQ启用晶体管224、225-1及225-2,这将数据线205-1⑼及205-2(D_)有效地短接在一起且短接到平衡电压(例如,Vcc/2)。 [0074] The sense amplifier 206 may further comprise balancing circuit 214, which may be square in order to balance the data lines 205-1) and 205-2 (DJ. In this example, the balancing circuit 214 includes a data line coupled configured 205-1⑼ 224. the balance between the transistor circuit 214 (D_) 205-2 225-1 and 225-2 further includes transistors, each having coupled to a balance voltage (e.g., VDD / 2) a first source / drain region which is associated with the array VDD supply voltage source of the second transistor 225-1 / drain regions may be coupled to the data lines 205-1 (D), and the transistor 225-2 of the second source / drain region may be coupled to the data lines 205-2 (D_). the gate of transistor 224,225-1 and 225-2 may be coupled together and to a balance (EQ) control signal line 226. thus, start enable transistor EQ 224,225- 1 and 225-2, and these data line 205-1⑼ 205-2 (D_) effectively shorted together and shorted to balance voltage (e.g., Vcc / 2).

[0075] 尽管图2展示包括平衡电路214的感测放大器206,但实施例不限于此,且平衡电路214可与感测放大器206离散地实施、以与图2中所示的配置不同的配置实施或完全不实施。 [0075] Although FIG. 2 shows a balancing circuit 214 includes a sense amplifier 206, but the embodiment is not limited thereto, and a balancing circuit 214 may be implemented with discrete sense amplifiers 206 to the configuration shown in FIG. 2 with different configurations embodiment or embodiments completely. [0076]如下文进一步描述,在若干实施例中,感测电路(例如,感测放大器206及计算组件231)可经操作以执行选定逻辑运算且最初将结果存储在感测放大器206或计算组件231中的一个中,而不经由I/O线从感测电路传送数据(例如,不经由例如列解码信号的启动执行数据线地址存取)。 [0076] As described further below, in several embodiments, the sensing circuit (e.g., sense amplifiers 206 and calculation component 231) may perform a logic operation selected by the operator and initially store the results of the sense amplifier 206 or calculated one assembly 231, not via the I / O line transmit data from the sensing circuitry (e.g., column decode start e.g. no signal is performed via the data line address to access).

[0077]逻辑运算(例如,涉及数据值的布尔逻辑函数)的执行是基本及常用的。 [0077] The logical operations (e.g., data relating to the value of Boolean logic functions) performed the base and common. 在许多较高阶函数中使用布尔逻辑函数。 Use Boolean logic functions in a number of higher-order functions. 因此,用改进的逻辑运算实现的速度及/或功率效率可翻译成较高阶功能性的速度及/或功率效率。 Thus, with the speed to achieve improved operation logic and / or power efficiency can be translated into a higher order function of the speed and / or power efficiency.

[0078]如图2中所示,计算组件231还可包括锁存器,其在本文中可称为次要锁存器264。 As shown in Figure [0078] 2, further comprising calculating a latch assembly 231, which may be referred to as the secondary latch 264 herein. 次要锁存器264可以类似于上文关于主要锁存器215描述的方式的方式配置及操作,只是包括次要锁存器的交叉耦合p沟道晶体管(例如,PMOS晶体管)对可使其相应源极耦合到供应电压(例如,VDD),且次要锁存器的交叉耦合n沟道晶体管(例如,NMOS晶体管)对可使其相应源极选择性地耦合到参考电压(例如,接地),使得连续启用次要锁存器除外。 Secondary latch 264 may be similar to the manner described above the latch 215 on the main embodiment described configuration and operation, only the cross-coupled p-channel transistor (eg, PMOS transistor) comprises a pair of secondary latch it respective voltage source coupled to a supply (e.g., the VDD), and the cross-coupled latch secondary n-channel transistor (eg, NMOS transistors) may have its respective source to be selectively coupled to a reference voltage (e.g., ground ), such that the secondary latch enable continuous exception. 计算组件的配置不限于图2中在231处展示的配置,且下文进一步描述各种其它实施例。 Any configuration of computing components in Figure 2 disposed at the display 231, and further described below various other embodiments.

[0079]图3是说明根据本发明的若干实施例的能够实施X0R逻辑运算的感测电路的示意图。 [0079] FIG. 3 is a schematic diagram of the sensing circuit can be implemented X0R logical operations according to several embodiments of the present invention. 图3展示耦合到一对互补感测线305-1及305-2的感测放大器306,及经由传递门307-1及307-2耦合到感测放大器306的计算组件331。 3 shows coupled to a pair of complementary sense lines 305-1 and 305-2 sense amplifier 306, and is coupled to the computing component 306 of the sense amplifier 331 via the transmission gates 307-1 and 307-2. 图3中所示的感测放大器306可对应于图2中所示的感测放大器206。 FIG sense amplifier 3306 may be shown in FIG. 2 correspond to sense amplifier 206. 图3中所示的计算组件331可对应于例如图1A中所示的感测电路(包含计算组件)150。 FIG computing component 331 shown in FIG 3 may correspond to a sensing circuit (comprising calculation component) 150 as shown in FIG. 1A, for example. 图3中所示的逻辑运算选择逻辑313可对应于例如图4中所示的逻辑运算选择逻辑413。 FIG logical operation selection logic 313 shown in Figure 3 correspond to the logical operation selection logic 413 shown in FIG. 4, for example.

[0080] 传递门307-1及307-2的栅极可受控于逻辑运算选择逻辑信号Pass。 [0080] The transfer gates 307-1 and 307-2 may be controlled by a gate logic operation signal selection logic Pass. 举例来说,逻辑运算选择逻辑的输出可耦合到传递门307-1及307-2的栅极。 For example, the logical operation of the logic gate output may be coupled to the transmission gates 307-1 and 307-2. 计算组件331可包括经配置以使数据值左移位及右移位的可加载移位寄存器。 Computing component 331 may be configured so that the data comprise values ​​of the left shift and right shift of the shift register can be loaded.

[0081] 根据图3中说明的实施例,计算组件331可包括经配置以使数据值左移位及右移位的可加载移位寄存器的相应级(例如,移位单元)。 [0081] According to the embodiment illustrated in Figure 3, the calculation component 331 may be configured to include the respective level (e.g., shift unit) data values ​​left shift and right shift of the shift register can be loaded. 举例来说,如图3中所说明,移位寄存器的各计算组件331 (例如,级)包括一对右移位晶体管381及386、一对左移位晶体管389及390以及一对反相器387及388。 For example, as illustrated in Figure 3, each shift register computation component 331 (e.g., level) comprises a pair of right shift transistors 381 and 386, a pair of left shift transistors 389 and 390 and a pair of inverters 387 and 388. 可将信号PHASE 1R、PHASE 2R、PHASE 1L及PHASE 2L施加到相应控制线382、383、391及392,以启用/停用对应计算组件331的锁存器上与根据本文中描述的实施例执行逻辑运算及/或移位数据相关联的反馈。 It may signal PHASE 1R, PHASE 2R, PHASE 1L PHASE 2L and applied to the corresponding control lines 382,383,391 and 392, to turn on / disabling the corresponding components of latch 331 is calculated in accordance with the embodiments described herein are performed feedback logic operation and / or data associated shift.

[0082]图3中所示的感测电路还展示耦合到若干逻辑选择控制输入控制线(包含ISO、TF、 TT、FT及FF)的逻辑运算选择逻辑313。 [0082] The sensing circuit shown in FIG. 3 also shows the logical operation of several logic logic select control input line is coupled to a control (containing ISO, TF, TT, FT and FF) 313. 从逻辑选择控制输入控制线上的逻辑选择控制信号的条件以及在经由确证ISO控制信号启用隔离晶体管时存在于互补感测线对305-1及305-2 上的数据值而确定从多个逻辑运算的逻辑运算选择。 Determining from a plurality of logic 305-1 and 305-2 on the data value of the selection control signal from the logic condition of the logic select control input on the control line and the isolation transistor is enabled via the control signals ISO confirmed present in a complementary sense lines logical operation selecting operation.

[0083] 根据各种实施例,逻辑运算选择逻辑313可包含四个逻辑选择晶体管:逻辑选择晶体管362,其耦合在交换晶体管342的栅极与TF信号控制线之间;逻辑选择晶体管352,其耦合在传递门307-1及307-2的栅极与TT信号控制线之间;逻辑选择晶体管354,其耦合在传递门307-1及307-2的栅极与FT信号控制线之间;及逻辑选择晶体管364,其耦合在交换晶体管342的栅极与FF信号控制线之间。 [0083] According to various embodiments, the logical operation is a logical selection logic 313 may include four transistors: logic selection transistor 362, which is coupled between the gate of the transistor 342 and the line switching control signal TF; logic selection transistor 352, which 307-1 coupled between the door and the transfer gate controlling signal line 307-2 to TT; a logical selection transistor 354, coupled between the door 307-1 and the gate line 307-2 and a control signal FT is transferred; and 364 between the coupled gate of the switching signal FF transistor logic selection transistor control line 342. 逻辑选择晶体管362及352的栅极通过隔离晶体管350-1 (具有耦合到ISO信号控制线的栅极)耦合到真感测线。 Logic gate select transistors 362 and 352 through isolation transistor 350-1 (having a control gate coupled to the signal line ISO) coupled to the true sense line. 逻辑选择晶体管364及354的栅极通过隔离晶体管350-2 (还具有耦合到ISO信号控制线的栅极)耦合到互补感测线。 Logic gate select transistors 364 and 354 through isolation transistor 350-2 (ISO further having a gate coupled to a control signal line) is coupled to a complementary sense lines.

[0084] 存在于互补感测线对305-1及305-2上的数据值可经由传递门307-1及307-2加载到计算组件331中。 [0084] in the presence of a complementary sense lines 305-1 and 305-2 on the data value transfer gate 307-1 and 307-2 may be loaded into computing component 331 via. 计算组件331可包括可加载移位寄存器。 Computing component 331 may include a loadable shift register. 当传递门307-1及307-2开启时, 互补感测线对305-1及305-2上的数据值被传递到计算组件331且借此被载入到可载入移位寄存器中。 When the transfer gate 307-1 and 307-2 is turned on, the complementary sense lines 305-1 to 305-2 and the value on the data is transmitted to the computing component 331 and thereby be loaded into the shift register can be loaded. 互补感测线对305-1及305-2上的数据值可为在触发感测放大器时存储在感测放大器306中的数据值。 Complementary sense lines 305-1 to 305-2 and data values ​​can be stored on the data values ​​in the sense amplifier 306 in the sense amplifier trigger. 逻辑运算选择逻辑信号pass为高以开启传递门3〇7-1及307-2。 Logic operation selection logic signal is high pass 3〇7-1 and to open transfer gate 307-2.

[0085] 130、1?、1'1'、? [0085] 130,1?, 1'1 ',? 1'及??控制信号可操作以基于感测放大器306中的数据值(<¥')及计算组件3:31中的数据值(“A”)选择逻辑函数进行实施。 1 'and the control signal is operable to ?? based on the data values ​​(<¥ sense amplifier 306' in embodiment selection logic function data values ​​( "A")) and 3:31 in computing component. 特定来说,130、1?、1'1^1\5^控制信号经配置以独立于存在于互补感测线对305-1及305-2上的数据值而选择逻辑函数进行实施(然而所实施逻辑运算的结果可取决于存在于互补感测线对305-1及305-2上的数据值)。 In particular, 130,1?, 1'1 ^ 1 \ 5 ^ control signal is configured to independently sense the presence of the complementary data line pair 305-1 and 305-2 on the values ​​selected logic function carried out (however, the results may depend on the implementation of the logic operation is present on the complementary sense lines 305-1 and 305-2 on the data values). 举例来说,130、了「、17/1'及?「控制信号直接选择逻辑运算进行实施,这是因为存在于互补感测线对305-1及305-2上的数据值并未传递通过用以操作传递门307-1及307-2的栅极的逻辑。 For example, 130, the "17/1 'and?" Select control signals logical operations directly carried out, because of the presence of the complementary sense lines 305-1 and 305-2 on the data values ​​are not transmitted through the to operate the logic gate of the transfer gate 307-1 and 307-2.

[0086]另外,图3展示经配置以在感测放大器313-7与计算组件331之间交换互补感测线对305-1及305-2的定向的交换晶体管342。 [0086] Further, FIG. 3 shows configured to sense amplifier 313-7 between the computing component 331 and a complementary switching directional sense lines 305-1 and 305-2 exchange transistor 342. 当交换晶体管342开启时,交换晶体管342的感测放大器306侧上的互补感测线对305-1及305-2上的数据值相反稱合(oppositely-couple) 到交换晶体管342的计算组件331侧上的互补感测线对305-1及305-2,且借此加载到计算组件331的可加载移位寄存器中。 When the switching transistor 342 is turned on, the exchange of complementary sense lines 306 on the side of the sense amplifier transistor 342 and 305-1 to 305-2 on the data value opposite to said engagement (oppositely-couple) to exchange computing component 331 of the transistor 342 complementary sense lines 305-1 and 305-2 on the side, and thereby computing component 331 is loaded into the shift register can be loaded.

[0087]当IS0控制信号线被启动且TT控制信号在真感测线上的数据值为“ 1”的情况下被启动(例如,为高)或FT控制信号在互补感测线上的数据值为“1”的情况下被启动(例如,为高)时,逻辑运算选择逻辑信号Pass可经启动(例如,为高)以开启传递门307-1及307-2 (例如,传导)。 Is activated (e.g., high) data or control signals FT complementary sense lines in the case where the [0087] When the control signal line is activated IS0 TT and the control signal data value of "1" in the true sense lines when the value "1" is started (e.g., high), the logic operation signal pass selection logic may be activated (e.g., high) to turn on the transfer gate 307-1 and 307-2 (e.g., conductivity).

[0088]真感测线上的数据值是“1”开启逻辑选择晶体管352及362。 [0088] The measured values ​​of the true sense of the data line is a "1" logic to enable the selection transistors 352 and 362. 互补感测线上的数据值是“1”开启逻辑选择晶体管354及364。 Data value complementary sense line is "1" on the select transistor 354 and logic 364. 如果ISO控制信号或对应感测线(例如,特定逻辑选择晶体管的栅极耦合到的感测线)上的相应TT/FT控制信号或数据值并非为高,那么传递门307-1及307-2将不会由特定逻辑选择晶体管开启。 If the corresponding TT ISO control signal or a corresponding sense line (e.g., specific logic gate coupled to the select transistor of the sensing line) / FT control signal or data value is not high, the transfer gate 307-1 and 307- 2 will not select transistor is turned on by specific logic.

[0089]当ISO控制信号线经启动且TF控制信号在真感测线上的数据值为“1”的情况下经启动(例如,为高)或FF控制信号在互补感测线上的数据值为“1”的情况下经启动(例如,为高)时,逻辑运算选择逻辑信号PassF可经启动(例如,为高)以开启交换晶体管342 (例如,传导)。 [0089] In the case where the control signal line via the ISO and TF start data value of the control signal in the true sense lines "1" by the start (e.g., high) FF data or control signals in a complementary sense lines when the value "1" by the start (e.g., high), the logic operation signal PassF selection logic may be activated (e.g., high) to turn on the switching transistor 342 (e.g., conductive). 如果对应感测线(例如,特定逻辑选择晶体管的栅极耦合到的感测线)上的相应控制信号或数据值并非为高,那么交换晶体管342将不会由特定逻辑选择晶体管开启。 If the corresponding sense line (e.g., specific logic gate coupled to the select transistor of the sensing line) on the respective control signal or data value is not high, the switching transistor 342 will not turn on the selection transistor by the particular logic.

[0090] Pass*控制信号不一定与Pass控制信号互补。 [0090] Pass * Pass the control signal and the control signal is not necessarily complementary. 可同时启动或撤销启动Pass及Pass* 控制信号两者。 Or simultaneously activate and deactivate Pass * Pass both the control signal. 然而,Pass及Pass*控制信号两者的同时启动使互补感测线对短接在一起, 其可为应避免的破坏性配置。 However, while Pass Pass * and both the control signal to start a complementary sense lines short together, which may be arranged to avoid destructive.

[0091]图3中说明的感测电路经配置以从四个逻辑选择控制信号直接选择多个逻辑运算中的一个进行实施(例如,逻辑运算选择并不取决于存在于互补感测线对上的数据值)。 The sensing circuit is configured in [0091] Figure 3 illustrates a plurality of logical operation to select one of four logic carried out directly from the selection control signal (e.g., the logical operation is not dependent on the presence of a complementary pair of sense line data values). 逻辑选择控制信号的一些组合可引起传递门307-1及307-2以及交换晶体管342两者同时开启,这使互补感测线对305-1及305-2短接在一起。 Selection control signal logic combination may cause some switching transistors 307-2 and 307-1 and the transfer gate 342 both turned on simultaneously, which makes the complementary sense lines are shorted together to 305-1 and 305-2. 根据本发明的若干实施例,可由图3中说明的感测电路实施的逻辑运算可为图4中所示的逻辑表中所概述的逻辑运算。 According to several embodiments of the present invention, the logic operation of the sensing circuit 3 described embodiments may be logical operation is a logical table shown in FIG. 4 may be outlined in FIG.

[0092]图4是说明根据本发明的若干实施例的由图3中所示的感测电路实施的可选择逻辑运算结果的逻辑表。 [0092] FIG. 4 is a logic table of the operation result select logic implemented by the sensing circuit shown in FIG 3 in accordance with several embodiments of the present invention. 四个逻辑选择控制信号(例如,TF、TT、FT及FF)连同存在于互补感测线上的特定数据值一起可用以选择多个逻辑运算中的一个进行实施,这涉及存储在感测放大器306及计算组件331中的开始数据值。 Four logic selection control signal (e.g., TF, TT, FT and FF) along with the specific data value is present in the complementary sense lines can be used together to select a plurality of logical operations performed in the embodiment, which relates to a sense amplifier in memory start data values ​​306 and 331 in the computing component. 四个控制信号连同存在于互补感测线上的特定数据值一起控制传递门307-1及307-2以及交换晶体管342的连续性,这又影响在触发之前/之后计算组件331及/或感测放大器306中的数据值。 Four control signals along with the specific data value is present in the complementary sense lines 307-1 and control transfer gate 307-2 and the continuity of the switching transistor 342, which in turn affects 331 and / or the sense of calculation before the trigger / after assembly data value sense amplifier 306. 可选择地控制交换晶体管342的连续性的能力有利于实施涉及反相数据值(例如,反相操作数及/或反相结果)等的逻辑运算。 Alternatively, the control capability of the transistor 342 is continuous exchange beneficial embodiment relates to inverted logic operation data values ​​(e.g., inverted operands and / or results of reverse phase) and the like.

[0093] 图4中说明的逻辑表4-1在444处展示栏A中所示的存储在计算组件331中的开始数据值,且在445处展示栏B中所示的存储在感测放大器306中的开始数据值。 Logic table illustrated in [0093] FIG. 44-1 start data value stored at 444 in the display shown in column A computing component 331, as shown at 445 and Display Panel B stored in the sense amplifier start data value 306. 逻辑表4-1中的其它3栏标头指代传递门307-1及307-2以及交换晶体管342的连续性,其可取决于四个逻辑选择控制信号(例如,TF、TT、FT及FF)的状态以及存在于互补感测线对305-1及305-2上的特定数据值而分别控制为开启或关闭。 Logic Table 4-1 column 3 other headers refer transfer gate 307-1 and 307-2 and the continuity of the switching transistor 342, which may depend on four logic selection control signal (e.g., TF, TT, FT and FF) state and the presence of the complementary sense lines 305-1 and 305-2 on the particular data value, respectively controlled to be turned on or off. “未开启”栏对应于传递门3〇7-1及307-2以及交换晶体管342都处于非传导条件,“开启真”对应于传递门3〇7_1及307-2处于传导条件,且“开启反相”对应于交换晶体管342处于传导条件。 "Not Open" column corresponding to the transfer gate and a switching transistor 307-2 3〇7-1 and 342 are in a non-conducting condition, the "on true" corresponding to the transfer gate 3〇7_1 and 307-2 in a conducting condition and the "on inverted "corresponds to the switching transistor 342 in a conducting condition. 逻辑表4-1中未反映对应于传递门307-1及307- 2 以及交换晶体管342都处于传导条件的配置,这是因为此导致感测线短接在一起。 Logic is not reflected in Table 4-1 corresponds to the transfer gate 307-1 and 307-2 and the switching transistor 342 are disposed in a conducting condition, because this leads to the sense lines are shorted together.

[0094] 经由对传递门307-1及307-2以及交换晶体管342的连续性的选择性控制,逻辑表4-1的上部分的三个栏中的每一个可与逻辑表4-1的下部分的三个栏中的每一个组合,以提供对应于九个不同逻辑运算的3x 3 = 9种不同结果组合,如由475处所示的各种连接路径所指示。 [0094] each via a transfer gate with a logic table 307-1 and three columns on a portion of the continuous selective control, logic table 307-2 and a switch transistor 342 4-1 4-1 each combination of a lower portion of column three, to provide nine different 3x 3 corresponding to the logical operation result = 9 different combinations, as indicated by the various connection paths shown at 475. 图4中说明的逻辑表4-2中概述可由如图1中所示的感测电路150实施的九种不同可选择逻辑运算,包含X0R逻辑运算。 FIG 4 logic described in Table 4-2 Summary FIG nine different selectable by sensing the logic operation circuit 150 shown in embodiment 1, comprising X0R logic operations.

[0095] 图4中说明的逻辑表4-2的栏展示包含逻辑选择控制信号的状态的标头480。 [0095] The column logic table illustrated in FIG. 44-2 show header contains the logic state of the selection control signal 480. 举例来说,在行476中提供第一逻辑选择控制信号的状态,在行477中提供第二逻辑选择控制信号的状态,在行478中提供第三逻辑选择控制信号的状态,且在行479中提供第四逻辑选择控制信号的状态。 For example, the row 476 provides a first logic state of the selection control signal, the row 477 provides a second logic state of the selection control signal, the third line 478 provides the logic state of the selection control signal, and the line 479 providing a fourth logic state of the selection control signal. 在行447中概述对应于结果的特定逻辑运算。 Specific logic operation line 447 corresponding to the summarized results.

[0096] 虽然实例实施例包含本文中已说明且描述的感测电路、感测放大器、计算组件、动态锁存器、隔离装置及/或移位电路的各种组合及配置,但本发明的实施例不限于本文中所明确陈述的所述组合。 [0096] While example embodiments have been described herein comprise various combinations and configurations described and the sensing circuit, the sense amplifier, the computing components, the dynamic latch, the isolation device and / or the shift circuit, the present invention is Example embodiments described herein are not limited to the combinations explicitly stated. 本文中公开的感测电路、感测放大器、计算组件、动态锁存器、隔离装置及/或移位电路的其它组合及配置明确包含于本发明的范围内。 The sensing circuit disclosed herein, a sense amplifier, the computing components, the dynamic latch, spacer devices and / or other combinations and configurations shift circuit expressly included within the scope of the present invention.

[0097]尽管本文中已说明及描述特定实施例,但所属领域的一般技术人员将了解,经计算以实现相同结果的布置可取代所示的特定实施例。 [0097] Although embodiments have been illustrated and described herein specific embodiments, but one of ordinary skill in the art will appreciate, the arrangement calculated to achieve the same results can be substituted as shown in particular. 本发明希望涵盖本发明的一或多个实施例的调适或变动。 The present invention is desirable adaptations or variations of the embodiments encompass one or more embodiments of the present invention. 应了解,己以说明性方式而非限制性方式进行上述描述。 It should be appreciated, it has to be illustrative manner rather than a restrictive manner described above. 所属领域的技术人员在检阅上述描述之后将了解上述实施例与本文中未具体描述的其它实施例的组合。 Those skilled in the art after reviewing the above description it will be appreciated that other embodiments of the combination of the above embodiments and not specifically described herein. 本发明的一或多个实施例的范围包含其中使用上述结构及方法的其它应用。 Range of one or more embodiments of the present invention includes other applications in which the above structures and methods. 因此,应参考所附权利要求书连同此类权利要求书所授权的等效物的全范围而确定本发明的一或多个实施例的范围。 Accordingly, reference should be appended claims, along with which such claims are entitled to the full scope of equivalents determine the scope of the one or more embodiments of the present invention.

[0098] 在前述具体实施方式中,为简化本发明的目的将一些特征集合在单一实施例中。 [0098] In the foregoing embodiment, to simplify the object of the present invention some features are set in a single embodiment. 本发明的此方法不应解释为反映以下意图:本发明的所公开实施例必须使用多于每一权利要求中所明确陈述的特征。 This method of disclosure is not to be interpreted as reflecting an intention that: the disclosed embodiments of the present invention have to use more features than are expressly each claim forth. 而是,如以下权利要求书反映,本发明目标在于少于单一公开实施例的全部特征。 Rather, as the following claims reflect book object of the invention lies in less than all features of a single disclosed embodiment. 因此,以下权利要求书特此并入到具体实施方式中,其中每一权利要求自身独立作为单独实施例。 Thus, the following claims are hereby incorporated into the Detailed Description, with each claim as its own independent separate embodiment.

Claims (33)

1. 一种设备,其包括: 存储器装置,其中所述存储器装置包括: 存储器单元阵列; 感测电路,其经由多个感测线耦合到所述阵列,所述感测电路包含感测放大器及经配置以执行逻辑运算的计算组件;及存储器控制器,其耦合到所述阵列及感测电路,所述存储器控制器经配置以: 接收指令块,所述指令块包含多个程序指令; 将所述指令块存储在所述阵列中;及检索程序指令以使用所述计算组件执行逻辑运算。 1. An apparatus, comprising: a memory means, wherein said memory means comprises: a memory cell array; a sensing circuit, coupled to the array via a plurality of sensing lines, the sensing circuit comprises a sense amplifier and computing component configured to perform a logic operation; and a memory controller coupled to the array and sense circuitry, the memory controller is configured to: receive an instruction block, said instruction block comprising a plurality of program instructions; and the instruction block stored in the array; and retrieving program instructions to use the calculation component performing a logic operation.
2. 根据权利要求1所述的设备,其中所述存储器单元阵列是动态随机存取存储器DRAM 单元。 2. The apparatus according to claim 1, wherein the memory cell array is a dynamic random access memory (DRAM) cells.
3. 根据权利要求1所述的设备,其中所述多个程序指令包括与存储器中处理PIM命令相关联的多个程序指令。 3. The apparatus according to claim 1, wherein a plurality of said plurality of program instructions comprising program instructions associated with the memory command processing PIM.
4. 根据权利要求3所述的设备,其中所述存储器控制器经配置以使用DRAM协议及DRAM 逻辑及电接口来接收所述指令块,且检索个别程序指令以使用所述计算组件执行逻辑运算。 4. The apparatus according to claim 3, wherein said memory controller and a DRAM protocol DRAM-logic and electrical interface configured to receive the instruction block, and retrieves program instructions to use the individual calculation component performing a logic operation .
5. 根据权利要求1所述的设备,其中在所述存储器控制器处接收的所述指令块通过主机预解析。 5. The apparatus according to claim 1, wherein said instruction block received at the memory controller at the host by pre-parsing.
6. 根据权利要求1所述的设备,其中所述存储器单元阵列包含多个存储器单元库,其中所述存储器装置包含耦合到所述多个库中的每一个的库仲裁器,且其中每一库包含所述存储器控制器,所述存储器控制器经配置以: 从所述库仲裁器接收与所述库相关的指令块;以及将所述指令块存储到如由主机解析的所述库上的多个位置。 6. The apparatus according to claim 1, wherein said memory cell array comprises a plurality of banks of memory cells, wherein each of said memory means comprises a library arbiter coupled to the plurality of libraries, and wherein each library contains the memory controller, the memory controller is configured to: receive an instruction associated with the block of the library from the library arbiter; to instructions such as a block and said stored resolved by the host in the library multiple locations.
7. 根据权利要求6所述的设备,其中每一存储器控制器经配置以: 接收指令以开始执行程序指令; 从所述库的所述多个位置检索个别程序指令以重复使用,以处置所述指令块内所含有的分支、循环、逻辑及数据运算; 在所述库本地高速缓存所检索的个别程序指令;以及重新高速缓存所检索的个别程序指令以重复使用。 7. The apparatus according to claim 6, wherein each memory controller is configured to: receive an instruction to begin executing program instructions; retrieving program instructions from said respective plurality of locations in the library to be reused, to disposal branches, loops, and logic operation within the data contained in said instruction block; individual programs in the local cache database retrieved instruction; individual programs and re-cache the retrieved instructions to reuse.
8. 根据权利要求7所述的设备,其中: 所述设备进一步包含耦合到所述感测电路的逻辑电路,所述逻辑电路包含呈感测放大器形式的锁存器;且其中所述存储器控制器经配置以将所检索的程序指令高速缓存且重新高速缓存到所述逻辑电路。 8. The apparatus of claim 7, wherein: said apparatus further comprises a logic circuit coupled to the sensing circuit, the logic circuit comprises as a form of the sense amplifier latch; and wherein said memory control It is configured to program instructions retrieved and re-cache the cache to the logic circuit.
9. 根据权利要求1到8所述的设备,其中所述设备包括经配置以经由通道控制器耦合到主机的多个存储器装置;且其中所述通道控制器经配置以将所述指令块发送到所述多个存储器装置中的每一个的库仲裁器。 9. The apparatus according to claim 1 to claim 8, wherein said apparatus is configured to include a plurality of memory devices coupled to a host controller via the passage; and wherein the controller sends a channel command to the block is configured to each of a plurality of memory arbiter library device.
10. 根据权利要求1到8所述的设备,其中所述设备经配置以: 经由库仲裁器接收后续指令块到所述存储器装置的库;以及在所述存储器控制器执行先前接收的指令块时将所述后续指令块存储到所述库的多个位置,以有利于使用所述计算组件开始未来逻辑运算。 10. The device according to claim 8, wherein the apparatus is configured to: receive a subsequent instruction via arbiter block library to the library of the memory device; and a block in the memory controller executes the instruction received previously when the subsequent instruction block into a plurality of positions in the library in order to facilitate the use of the calculation component the next logical operation begins.
11. 一种设备,其包括: 通道控制器,其经配置以: 接收包含多个程序指令的指令块; 分配存储器装置中的多个位置以存储所述指令块;以及将所述指令块发送到所述存储器装置;及库仲裁器,其与所述存储器装置相关联并耦合到所述通道控制器,所述库仲裁器接收所述指令块并将所述指令块发送到所述存储器装置中的多个库当中的适当库,其中每一库包括: 存储器单元阵列; 感测电路,其经由多个感测线耦合到所述阵列,所述感测电路包含感测放大器及经配置以实施逻辑运算的计算组件;及存储器控制器,其耦合到所述阵列及所述感测电路,其中所述存储器控制器经配置以: 从所述库仲裁器接收到所述库的所述指令块;以及将所述接收的指令块存储到由所述通道控制器分配的所述阵列中的多个位置。 11. An apparatus, comprising: a channel controller, which is configured to: receive an instruction block comprising a plurality of program instructions; a plurality of location allocation memory devices to store the instruction block; and transmitting the instruction blocks to the memory means; and a library arbiter associated with the memory device and a controller coupled to the channel, the arbiter receives the library and the instructions of said instruction block blocks sent to the memory device among suitable library in multiple libraries, wherein each bank comprises: a memory cell array; a sensing circuit, coupled via a plurality of sense lines to the array, the sensing circuit comprises a sense amplifier and configured to computing component embodiment of the logic operation; and a memory controller coupled to the array and the sensing circuit, wherein the memory controller is configured to: receiving the instructions from the library to the library arbiter block; and the received instruction blocks stored in said plurality of array positions assigned by the channel controller.
12. 根据权利要求11所述的设备,其中: 所述存储器单元阵列为动态随机存取存储器DRAM单元;且所述存储器控制器经配置以使用DRAM协议及DRAM逻辑及电接口以: 经由所述库仲裁器从所述通道控制器接收所述指令块;以及执行所述指令块中的程序指令以在所述计算组件上执行逻辑运算。 12. The apparatus as claimed in claim 11, wherein: the memory cell array is a dynamic random access memory (DRAM) cells; and the memory controller is configured to use protocol DRAM and DRAM-logic and electrical interfaces to: via the library from the channel arbiter controller receiving said instruction block; and executing the instruction block of program instructions to perform logical operations on the computing component.
13. 根据权利要求12所述的设备,其中存储器控制器经配置以: 经由所述库仲裁器从所述通道控制器接收指令以开始执行程序指令;以及检索来自所述阵列中的所述多个位置的程序指令以执行以引起所述计算组件执行逻辑运算。 13. The apparatus as claimed in claim 12, wherein the memory controller is configured to: receive an instruction from the channel controller via said arbiter library to begin executing program instructions; and retrieving from said plurality of said array program instructions to perform position calculation component to cause said performing a logic operation.
14. 根据权利要求13所述的设备,其中所述存储器控制器经配置以: 在所述库本地高速缓存所检索的程序指令;以及重新高速缓存所检索的程序指令用于重复使用以处置所述指令块内所含有的分支、循环、逻辑及数据运算。 14. The apparatus according to claim 13, wherein the memory controller is configured to: program instructions in the local cache are retrieved libraries; and program instructions to re-cache the retrieved for re-use to disposal branches, loops, and logic operation within the data contained in the said instruction block.
15. 根据权利要求14所述的设备,其中所述设备进一步包含耦合到所述感测电路的逻辑电路,所述逻辑电路包括呈感测放大器形式的锁存器;且所述存储器控制器经配置以高速缓存及重新高速缓存在与所述阵列的间距上的所检索的程序指令。 15. The apparatus according to claim 14, wherein said apparatus further comprises a logic circuit coupled to the sensing circuit, the logic circuit comprises, in the form of a sense amplifier latch; and the memory controller the program instructions disposed on a pitch of the array to the retrieved cache, and re-cache.
16. 根据权利要求11到15所述的设备,其中所述设备包括耦合到所述通道控制器的多个存储器装置,且其中所述通道控制器将所述指令块发送到所述多个存储器装置当中的适当库仲裁器。 11 16. The apparatus according to claim 15, wherein said apparatus comprises a plurality of memory devices coupled to the channel controller, wherein the channel controller and the instruction is transmitted to the plurality of memory blocks library appropriate means among arbiter.
17. 根据权利要求11到15所述的设备,其中所述存储器控制器经配置以: 在所述存储器控制器执行先前接收的指令块时接收后续指令块到所述库;以及将后续指令块存储到如由所述通道控制器分配的所述阵列中的多个位置,以有利于未来执行以引起所述计算组件执行逻辑运算。 11 17. The apparatus according to claim 15, wherein the memory controller is configured to: when receiving the memory controller performs the previously received block of instructions subsequent to the instruction block base; and a subsequent instruction blocks stored in the array as a plurality of positions of the channel allocation controller in order to facilitate future performed to cause the calculation component performing a logic operation.
18.根据权利要求11到15所述的设备,其中所述阵列中的所述多个位置是多个子阵列的部分。 11 18. The apparatus according to claim 15, wherein said plurality of positions of said array are part of a plurality of sub-arrays.
19.根据权利要求11到15所述的设备,其中所述存储器控制器经配置以控制所述感测电路以实施逻辑函数,包含八_、01?、吣1\\01?、隱吣及^)1?逻辑函数。 11 19. The apparatus according to claim 15, wherein the memory controller is configured to control the sensing circuit to implement a logic function, comprising eight _, 01 ?, 01 ?, \\ 1 Qin Qin and implicit ^) 1? logic function. ^ ' 2〇•根据权利要求19所述的设备,其中所述存储器控制器经配置以控制所述感测电路以执行非布尔逻辑运算,包含复制、比较及擦除。 ^ '• 2〇 apparatus according to claim 19, wherein the memory controller is configured to control the sense circuitry to perform a non-Boolean logic operation, comprising copying, comparing, and erase.
21. —种设备,其包括: 通道控制器,其耦合到多个存储器装置,所述通道控制器经配置以: 接收包含多个程序指令的指令块;以及分配所述多个存储器装置中的多个位置以存储所述指令块;以及库仲裁器,其耦合到每一存储器装置的所述通道控制器,所述库仲裁器耦合到每一存储器装置中的多个库,所述库仲裁器用以接收所述指令块,其中每一库包括: 存储器单元阵列; 感测电路,其经由多个感测线耦合到所述阵列,所述感测电路包含感测放大器及经配置以实施逻辑运算的计算组件;及存储器控制器,其耦合到所述阵列及所述感测电路,其中所述存储器控制器经配置以: 从所述库仲裁器接收所述指令块;以及将所述指令块存储到如由所述通道控制器分配的所述阵列中的多个位置;以及检索程序指令以执行以引起所述计算组件执行逻辑运算。 21. - species apparatus comprising: a channel controller coupled to a plurality of memory devices, said channel controller is configured to: receiving instruction block comprising a plurality of program instructions; and allocating said plurality of memory devices instructions to store a plurality of positions of said block; and libraries arbiter coupled to the controller for each memory channel device, the arbiter is coupled to a plurality of libraries each library memory devices, arbitration of the library unit to receive the instruction block, wherein each bank comprises: a memory cell array; a sensing circuit, coupled to the array via a plurality of sensing lines, the sensing circuit comprises a sense amplifier and configured to implement the logic computing component operation; and a memory controller coupled to the array and the sensing circuit, wherein the memory controller is configured to: from the library to receive the command arbiter block; and the instruction block into a plurality of positions of said array as assigned by the channel control; and search program instructions to perform the calculation component to cause performing a logic operation.
22. 根据权利要求21所述的设备,其中在所述通道控制器处接收的所述程序指令是用于存储器中处理PIM装置的预解析程序指令。 22. The apparatus according to claim 21, wherein the program instructions received at the controller the channel is a memory for pre-analysis program instruction processing apparatus PIM.
23. 根据权利要求21所述的设备,其中: 所述存储器单元阵列是动态随机存取存储器DRAM单元,且所述多个位置是子阵列;且所述存储器控制器经配置以使用DRAM协议及DRAM逻辑及电接口以: 经由所述库仲裁器从所述通道控制器接收所述指令块;以及执行所述接收的指令块中的程序指令以引起所述计算组件执行逻辑运算。 23. The apparatus according to claim 21, wherein: the memory cell array is a dynamic random access memory (DRAM) cells, and a plurality of subarray positions; and the memory controller is configured to use protocol and DRAM DRAM-logic and electrical interfaces to: library via said arbiter from the channel controller receives the instruction block; and instruction blocks executed in the received program instructions to cause the computing component performing a logic operation.
24. 根据权利要求21到23所述的设备,其中存储器控制器经配置以: 经由所述库仲裁器从所述通道控制器接收指令以开始执行所述指令块; 检索来自所述阵列中的所述多个位置的程序指令以执行以引起所述计算组件执行逻辑运算; 在所述库本地高速缓存所检索的程序指令;以及重新高速缓存所检索的程序指令用于重复使用以处置所述指令块内所含有的分支、循环、逻辑及数据运算。 21 24. The apparatus according to claim 23, wherein the memory controller is configured to: receive an instruction from the channel controller via said arbiter library to begin executing the instruction block; retrieving from said array program instructions to perform a plurality of positions to cause the computing component performing a logic operation; program instructions in the library of the local cache are retrieved; re-program instructions and cache the retrieved for reuse at the disposal branches, loops, and logic operation data contained within the instruction block.
25. 根据权利要求24所述的设备,其中所述存储器控制器经配置以: 在所述存储器控制器执行先前接收的指令块时接收后续指令块到所述库;以及将所述后续指令块存储到所述阵列中的多个位置,其与执行先前接收的指令块并行以便有利于所述后续指令块的未来执行。 25. The apparatus according to claim 24, wherein the memory controller is configured to: when receiving the memory controller performs the previously received block of instructions subsequent to the instruction block library; and the subsequent instruction block a plurality of storage positions in the array, and the execution of the preceding instruction block which is received in parallel in order to facilitate the next execution of the subsequent instruction block.
26.—种用于操作存储器装置以作为经预解析指令的存储的方法,其包括: 接收包含多个程序指令的指令块到所述存储器装置中的库,其中所述库包括: 存储器单元阵列; 感测电路,其耦合到所述阵列,所述感测电路包含感测放大器及经配置以实施逻辑运算的计算组件;及存储器控制器,其耦合到所述阵列及所述感测电路; 将所述指令块存储在所述阵列中;及从所述阵列接收程序指令以引起所述计算组件执行逻辑运算。 26.- method of operating a memory means for storing as a pre-parsed instructions, comprising: instructions for receiving a block comprising a plurality of program instructions to the memory device in a library, wherein the library comprises: a memory cell array ; sensing circuit, coupled to the array, the sensing circuit comprises a sense amplifier and configured to implement the logic operation of computing components; and a memory controller coupled to the array and the sensing circuit; the instruction block stored in the array; and program instructions received from the array to cause the computing component performing a logic operation.
27.根据权利要求26所述的方法,其中接收包含所述多个程序指令的所述指令块包括: 接收包含与存储器中处理PIM命令相关联的多个经预解析程序指令的指令块。 The instruction block 27. The method according to claim 26, wherein said plurality of program instructions include receiving comprises: receiving a instruction block in the memory associated with the processing command associated PIM preresolved plurality of program instructions.
28.根据权利要求26所述的方法,其中所述阵列是动态随机存取存储器阵列DRAM,且存储所述指令块包括将所述指令块存储在所述DRAM的多个子阵列中。 28. The method according to claim 26, wherein said array is a dynamic random access memory DRAM array, and storing said instruction blocks comprising a plurality of instruction blocks stored in said sub-arrays of the DRAM.
29.根据权利要求26所述的方法,其中接收、存储及检索包括:使用DRAM协议及DRAM逻辑及电接口接收、存储及检索所述程序指令。 29. The method of claim 26, wherein the receiving, storage and retrieval comprising: a DRAM protocol and the electrical interface and DRAM-logic receiving, storing and retrieving the program instructions.
30. 根据权利要求26到29所述的方法,其中所述方法包括: 在所述存储器控制器处接收指令以开始执行所述指令块中的程序指令; 从所述阵列检索所述程序指令以使用所述计算组件执行逻辑运算; 在到所述库的间距上高速缓存所述所检索程序指令;以及在到所述库的间距上重新高速缓存所述所检索程序指令以重复使用,以处置分支、循环、逻辑及数据运算。 30. The method of claim 26 to 29 claim, wherein the method comprises: receiving an instruction at the memory controller to begin executing the instruction block of program instructions; retrieved from the array to the program instructions using the calculation component performing a logic operation; pitch on said library cache to said program instructions being retrieved; and program instructions on said distance to said library cache re retrieved for reuse, to handle branches, loops, and logic operation data.
31. 根据权利要求30所述的方法,其中在到所述库的间距上高速缓存及重新高速缓存所述程序指令包括:在耦合到所述感测电路的额外逻辑电路中且在与所述阵列的间距上高速缓存及重新高速缓存。 31. The method according to claim 30, wherein the pitch of the library to the cache and re-cache the program instructions comprising: an additional logic circuit coupled to the sensing circuit and in the the pitch of the array and re-cache the cache.
32. 根据权利要求30所述的方法,其中所述方法包括: 在所述存储器控制器执行来自先前接收的指令块的程序指令时接收包含多个程序指令的后续指令块到所述库;及与执行来自所述先前接收的指令块的程序指令并行地将所述后续指令块存储到所述阵列。 32. The method according to claim 30, wherein the method comprises: receiving a plurality of subsequent instructions in the program when the program executes instructions from the memory controller previously received instruction block to block in the library; and from the implementation of the previously received block of instructions in parallel with the program instructions subsequent to the instruction block memory array.
33.根据权利要求26到29所述的方法,其中所述方法包括: 经由库仲裁器接收包含经预解析程序指令的指令块到所述存储器装置上的多个库中的相应库。 33. The method according to claim 26 to 29 claim, wherein said method comprises: an instruction pre-parsed program instructions received via the arbiter library comprising a plurality of blocks to the appropriate library database on the memory device.
34.根据权利要求33所述的方法,其中所述方法包括: 经由通道控制器接收所述指令块到多个存储器装置中的每一个上的所述库仲裁器;及使用所述通道控制器中的逻辑分配每一相应库的所述阵列中的多个位置。 34. The method according to claim 33, wherein the method comprises: receiving said instruction block to each of the plurality of memory devices in the library arbiter via the channel controller; and the use of the channel controllers the plurality of positions each respective array logic library in the distribution.
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