KR100314129B1 - Semiconductor implementing bank and data input/output line architecture to reduce data input/output line loading - Google Patents

Abstract

A semiconductor memory device embodied by a bank configuration method and a data input / output line arrangement method capable of reducing the load of a data input / output line are disclosed. The present invention provides a semiconductor memory device having a plurality of banks, in which a plurality of memory cell data in a selected bank is input / output through data input / output lines, each bank being divided into two or more subbanks, Each bank is divided into upper and lower memory blocks, and the upper and lower memory blocks in the bank group share data input / output lines.

Description

Semiconductor implementing bank and data input / output line architecture to reduce data input / output line loading}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a bank configuration method and a data input / output line arrangement method for reducing the load on a data input / output line.

In general, in order to improve the performance of a computer system, the performance of the CPU and the performance of the memory device for storing data, programs, and the like required by the CPU are required. In order to improve the performance of the memory device, the amount of input / output data transmitted per unit time must be increased. As a method of increasing the amount of input / output data, there is a method of increasing the number of input / output data bits or increasing the access speed.

As a representative example thereof, a synchronous DRAM (hereinafter referred to as SDRAM) may be mentioned. The amount of data read or written at one time in the synchronous DRAM is directly affected by the number of input / output lines and is defined by data input / output rules such as × 16 or × 18. Therefore, memory cell bit line data corresponding to the number of data input / output lines of x16 or x18 is transmitted to the data input / output line.

The data input / output line ultimately reads or writes data of the memory cell, and the data of the memory cell loaded on the data input / output line determines the operation speed of the semiconductor memory device. The speed is determined by the time required for sensing data stored in the memory cell to be read and outputting the data to the data input / output line, or the time required to transfer the data to be written from the data input / output line to the memory cell.

As shown in FIG. 1, the data input / output line is shared with a plurality of banks, thereby increasing the load of the data input / output line. A large load on the data input / output line slows down the read and write operations of the memory cell data, resulting in a problem that the characteristics of the synchronous DRAM deteriorate.

Therefore, a method for reducing the load on the data input / output line is required.

An object of the present invention is to provide a bank configuration method and a data input / output line arrangement method which can reduce the load of the data input / output lines.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a data input / output line structure shared in a plurality of conventional banks.

2 is a diagram illustrating a semiconductor memory device including a bank configuration method and a data input / output line layout method according to an exemplary embodiment of the present invention.

The present invention for achieving the above object has a plurality of banks, a plurality of memory cell data in the selected bank is input and output through the data input and output lines, each of the banks divided into two or more subbanks Each bank is divided into upper and lower memory blocks, and the upper and lower memory blocks of the bank group share data input / output lines. .

Preferably, the lower data input / output line connecting the lower memory blocks of the subbanks does not extend to the upper memory block of any one of the subbanks, and the upper data input / output line connecting the upper memory blocks of the subbanks is also present. It does not extend to the bottom memory block of any one of the subbanks.

In each bank group, predetermined subbanks of the subbanks are symmetrically disposed on both the left and right sides of the upper and lower data input / output lines, and the remaining subbanks are arranged on both the left and right sides of the upper and lower data input / output lines. It is suitable to be arranged parallel to the banks.

According to the arrangement method of the bank and the data input / output lines of the present invention as described above, the load on the data input / output lines can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements. The present invention is described with respect to a synchronous semiconductor memory device which operates in synchronization with a clock which is widely used in recent years. In order to realize wide-channel and high performance of the synchronous semiconductor memory device, the number of banks and data input / output lines may be configured in various ways. An example composed of 32 data input / output lines that satisfy the 32 input / output specification is described.

2 illustrates a semiconductor memory device illustrating a bank configuration method and a data input / output line arrangement method according to an embodiment of the present invention. Referring to this, the semiconductor memory device 2 is composed of four banks A-BANK, B-BANK, C-BANK, and D-BANK, each of which is composed of a plurality of memory cells arranged in rows and columns. Banks of A-BANK, B-BANK, C-BANK, D-BANK are divided into two subbanks: A-BANK_1, A-BANK_2, B-BANK_1, B-BANK_2, C-BANK_1, and C-BANK_2. , D-BANK_1, D-BANK_2).

Here, the memory cell addressing method of the sub-banks A-BANK_1 and A-BANK_2 in the A bank A-BANK is the same. In other words, the position of the memory cell selected by the address designating one memory cell in the sub-bank A-BANK_1 is the same as the position of the memory cell selected in the sub-bank A-BANK_2. That is, when the upper memory block 10 in the sub-bank A-BANK_1 is selected, the upper memory block 10 is also selected in the sub-bank A-BANK_2. A subbanks B-BANK_1, B-BANK_2, C-BANK_1, C-BANK_2, D-BANK_1, and D-BANK_2 belonging to the other banks B-BANK, C-BANK and D-BANK are also A. The addressing method is the same as in the sub-banks A-BANK_1 and A-BANK_2 of the bank A-BANK.

A group of sub-banks A-BANK_1, B-BANK_1, C-BANK_1, and D-BANK_1 are assigned to the first bank group 4, and another group of sub-banks A-BANK_2, B-BANK_2 and C-BANK_2. , D-BANK_2 is arranged to belong to the second bank group 6.

Each of the sub-banks A-BANK_1, B-BANK_1, C-BANK_1, and D-BANK_1 in the first bank group 4 also has upper and lower memory blocks 10, 11, 20, 21, 30, 31, and 40. 41, wherein one bank, for example, the A bank A-BANK, is the upper and lower memory blocks 10 and 11 according to the highest address among the addresses connected to the A bank A-BANK. Separated by.

Each of the upper and lower memory blocks 10 and 11 of the A bank A-BANK is also divided into two sub memory blocks 10A, 10B, 11A, and 11B, and each sub memory block of the upper memory block 10 ( The memory cell data in 10A and 10B are transferred to the global data line G-IO through eight local data lines L-IO. Thereafter, the global data line G-IO is connected to the upper data input / output line DIO_u. In addition, the memory cell data in each of the sub memory blocks 11A and 11B of the lower memory block 11 is also transferred to the global data line G-IO through eight local data lines L-IO, thereby providing lower data input / output. It is connected to the line DIO_l.

In the first bank group 4, the upper memory blocks 10, 20, 30, and 40 of the sub-banks A-BANK_1, B-BANK_1, C-BANK_1, and D-BANK_1 have upper data input / output lines DIO_u. The lower memory blocks 11, 21, 31, and 41 share the lower data input / output line DIO_l. Similarly, in the second bank group 6, the upper memory blocks 10, 20, 30, and 40 of the sub-banks A-BANK_2, B-BANK_2, C-BANK_2, and D-BANK_2 have upper data input / output lines ( The DIO_u) is shared and the lower memory blocks 11, 21, 31, and 41 share the lower data input / output line DIO_l. Each of the upper and lower data input / output lines DIO_u and DIO_l includes 16 data input / output lines.

Here, the arrangement of the subbanks A-BANK_1, B-BANK_1, C-BANK_1, and D-BANK_1 in the first bank group 4 based on the upper and lower data input / output lines DIO_u and DIO_l will be described. The A sub-bank A-BANK_1 and the B sub-bank B-BANK_1 are on the left side of the upper and lower data input / output lines DIO_u and DIO_l, and the C sub-bank C-BANK_1 and the D sub-bank D-BANK_1 are The upper and lower data input / output lines DIO_u and DIO_l are disposed in parallel with each other. The A subbank A-BANK_1 and the C subbank C-BANK_1 are symmetrical with the upper and lower data input / output lines DIO_u and DIO_l, and the B subbank B-BANK_1 and the D subbank D-. BANK_1 is also disposed symmetrically on the upper and lower data input / output lines DIO_u and DIO_l.

Therefore, the lower data input / output line DIO_l connecting the lower memory blocks 11 and 21 of the A sub-bank A-BANK_1 and the B sub-block B-BANK_1 has an upper end of the A sub-bank A-BANK_1. Since it does not extend to the memory block 10, the line load by this portion is reduced. In addition, the upper end data input / output line DIO_u connecting the upper memory blocks 30 and 40 of the C subbank C-BANK_1 and the D subblock D-BANK_1 also has a lower end of the D subbank D-BANK_1. Since it does not extend to the memory block 41, the line load by this portion is reduced. Accordingly, such a data input / output line structure has a relatively small line load compared to a large line load connected to all of a plurality of conventional banks.

The upper and lower data input / output lines DIO_u and DIO_l are connected to a data line sense amplifier IOSA and a data line driver DIOD, which read memory cell data in a selected bank, for example, an A bank. In operation, the data transmitted to the upper and lower data input / output lines DIO_u and DIO_l are sensed and amplified and transmitted to the data output buffer (not shown).

The operation of a semiconductor memory device having such a bank and data input / output line arrangement method will now be described.

First, in the data input / output method of the A bank A-BANK, when the A bank A-BANK is selected, all of the sub-banks A-BANK_1 and A-BANK_2 in the first and second bank groups 4 and 6 are selected. Is activated. When the upper memory block 10 of the sub-bank A-BANK_1 is selected, the upper memory block 10 is also simultaneously selected in the sub-bank A-BANK_2. In the first bank group 4, memory cell data in each of the sub memory blocks 10A and 10B of the upper memory block 10 is transferred to the global data line G-IO through eight local data lines L-IO. It is transmitted and connected to the 16 upper data input / output lines DIO_u. In addition, in the second bank group 6, the memory cell data in each of the sub memory blocks 10A and 10B of the upper memory block 10 is connected to the global data line G-IO through eight local data lines L-IO. ) Is connected to the 16 upper data input / output lines DIO_u.

Accordingly, the memory cell data is inputted and outputted from the 16 upper data input / output lines DIO_u in the first bank group 4 and the 16 upper data input / output lines DIO_u in the first bank group 6. Therefore, the 32 memory cell data satisfying the 32 input / output specification (spec.) In which the input and output are simultaneously input and output.

Since the data input / output method to the other banks B-BANK, C-BANK, and D-BABK is the same as the A bank A-BANK described above, a detailed operation description will be omitted to avoid duplication of description.

Therefore, the arrangement method of the bank and the data input / output lines of the present invention has the effect of reducing the load on the data input / output lines.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the method of arranging a bank and a data input / output line according to the present invention, a lower data input / output line connecting lower memory blocks 11 and 21 of an A subbank A-BANK_1 and a B subblock B-BANK_1. The DIO_l does not extend to the upper memory block 10 of the A subbank A-BANK_1, and the upper memory blocks 30 and 40 of the C subbank C-BANK_1 and the D subblock D-BANK_1. Note that the upper data input / output line DIO_u connecting the () is also not extended to the lower memory block 41 of the D sub-bank D-BANK_1, thereby reducing the line load by these portions.

Claims (3)

In a semiconductor memory device having a plurality of banks, a plurality of memory cell data in the selected bank is input and output through the data input and output lines, Each of the banks is divided into two or more subbanks, and is divided into bank groups including one of the subbanks. Each of the subbanks in the bank group is also divided into upper and lower memory blocks. And the upper and lower memory blocks share the data input / output lines. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises: The lower end data input / output line connecting the lower end memory blocks of the subbanks does not extend to the upper end memory block of any one of the subbanks, and the upper end data input / output line connects the upper end memory blocks of the subbanks. And the memory module does not extend to a lower memory block of one of the subbanks. The method of claim 1, wherein each bank group is Predetermined subbanks of the subbanks are symmetrically disposed on both left and right sides of the upper and lower data input / output lines, and the remaining subbanks are disposed on both the left and right sides of the upper and lower data input / output lines. The semiconductor memory device, characterized in that arranged in parallel with respect to.