KR100486221B1 - Memory device having multi-banks sharing i/o lines - Google Patents

Abstract

Disclosed is a memory device which is arranged such that an input / output line is shared with a neighboring memory bank and the capacitive load of the input / output line is not increased, and the layout efficiency is improved. It includes a plurality of memory banks, at least one input / output line shared in the plurality of memory banks and transferring data written to or read from each memory bank, and disposed in each of the memory banks, and having a row address. A bit line sense amplifier for sensing and amplifying bit line data of the memory bank output in response to the bit line; and an output signal of the bit line sense amplifier by activating the bank selection signal. And a bank select switch for transmitting a signal, and a column select switch shared with the plurality of memory banks, and configured to transmit a signal transmitted by the bank select switch to the data input / output line.

Description

Memory device having a plurality of memory banks sharing input and output lines {Memory device having multi-banks sharing I / O lines}

The present invention relates to a semiconductor memory device, and more particularly, to a memory device in which a plurality of memory banks share input / output lines.

As semiconductor memory devices are highly integrated, there is an inevitable increase in chip size. Accordingly, with the recognition that the structure of word lines, bit lines, and data buses is limited in speeding up and reducing power of memory devices, attempts to reduce latency by appropriately arranging these wires reduce capacitive loads. Is active. In particular, an input / output line that reads data amplified from a bit line sense amplifier to the outside is required to transmit data to a specific data output pad, so that the length is long and it is difficult to speed up.

FIG. 1 is a diagram illustrating an arrangement of a memory bank and an input / output line in a conventional semiconductor memory device 10 having two memory banks.

)이 배치되어 있으며, 각 입출력 라인에는 입출력 감지 증폭기(28)와 기입 드라이버(30)가 배치되어 있다. 칩의 외곽에는, 복수개의 데이터 입출력 패드(32)가 배치되어 있다.Looking at the structure, the memory cell array is divided into bank A and bank B, and each memory bank is divided into eight blocks 12 to 26 and 52 to 66 having the same size. Each memory block has an input / output line (I / O,

) And an input / output sense amplifier 28 and a write driver 30 are arranged in each input / output line. On the outside of the chip, a plurality of data input / output pads 32 are arranged.

As shown, memory blocks arranged to correspond to the top and bottom of the memory blocks of the banks A and B may write data to the memory bank or transmit data to the memory bank through the same data input / output pins DQ0 to DQ7. . For example, the input / output lines disposed in each of the first blocks 12 and 52 of the banks A and B are combined into one data path and connected to one data input / output pin DQ0. Therefore, as shown, when the pads 32 are arranged outside the chip, the data line of one bank to reach a specific data output pad becomes very long.

That is, according to the conventional structure mentioned, since one block in the bank A and one block in the bank B corresponding thereto must be multiplexed into one input / output line, the length of the input / output line becomes long and the operation speed of the chip decreases. do. In addition, an independent input / output sense amplifier 28 and a write driver 30 must be disposed in each memory block, thereby increasing the area of the chip. In addition, memory cell size is reduced due to the development of memory manufacturing process technology, and the width (a) of the memory block is gradually reduced, making it difficult to secure space for the input / output sense amplifier and write driver arrangement required per memory block. There is. In particular, when a plurality of input / output lines are employed to increase the output bandwidth, it is difficult to secure layout space for the plurality of input / output sense amplifiers 28 and the write driver 30 for each memory bank.

FIG. 2 is a diagram illustrating another conventional example in which a memory bank and an input / output line are disposed, and the same reference numerals as in FIG. 1 denote the same members.

)을 공유하고 있다.As shown in Fig. 2, the memory array is divided into bank A and bank B, and each memory bank is divided into eight blocks 12 to 26 and 52 to 66 having the same size. One block of the bank B is disposed at the lower portion so as to correspond to the one block of the bank A disposed at the upper portion. Corresponding bank blocks of bank A and bank B are input / output lines (I / O,

) Are sharing.

According to the above structure, since two memory blocks share an input / output line, the number of required input / output sense amplifiers 28 and write drivers 30 can be reduced, thereby reducing the layout area.

However, since banks A and B are located at the top and the bottom, the length of the input / output line is long, and the number of the column select switches connected to the input / output line is doubled compared to the case shown in FIG. Accordingly, there is a problem that the capacitive load of the input / output line is increased and the operating speed of the memory device is lowered.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a memory device in which an input / output line is shared with a neighboring memory bank and is arranged such that the capacitive load of the input / output line is not increased, and the layout efficiency is improved.

According to an aspect of the present invention, there is provided a memory device including: a plurality of memory banks and at least one input / output line shared in the plurality of memory banks and transferring data written to or read from each memory bank; And a bit line sense amplifier disposed in each of the memory banks, the bit line sense amplifier sensing and amplifying bit line data of the memory bank output in response to a row address, and an output of the bit line sense amplifier selected by a column address. And a column select switch for transmitting the column select line and the predetermined bank select signal to the input / output line.

The column select switch unit may be disposed to correspond to the bit line sense amplifier, and may be shared by a bank select switch configured to transmit an output signal of the bit line sense amplifier by activation of the bank select signal, and the plurality of memory banks. And a column select switch for transmitting the signal transmitted by the bank select switch to the data input / output line, wherein the bank select signal is a signal that is activated after the bit line data output from the selected memory bank is sufficiently amplified.

In the semiconductor memory device according to the present invention, since a plurality of memory banks adjacent in the lateral direction share the input / output line, the length of the input / output line is reduced to almost 1/2 compared to the case in which the semiconductor memory device is adjacent in the longitudinal direction, thereby operating speed of the memory device Will be faster. In addition, since the input / output line sense amplifier and the write driver need to be disposed within a plurality of block widths, even if the size of the memory cell is reduced and the memory block width is reduced, the spatial margin can be secured as compared with the related art. Therefore, even if a plurality of input / output line structures are employed to increase the output bandwidth, a space in which a plurality of input / output sense amplifiers and write drivers corresponding thereto are disposed is secured. In addition, since the column select switches are shared in a plurality of (N) memory banks, the number of the column select switches connected to the input / output lines is reduced to 1 / N, so that the parasitic capacitance is reduced, thereby increasing the data transfer rate. .

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

FIG. 3 is a schematic block diagram illustrating a memory device according to a first embodiment of the present invention.

)이 공유되도록 배치된다. 따라서, 한 쌍의 메모리 블록 즉, 메모리 두 개당 입출력 라인 감지 증폭기(150)와 기입 드라이버(160)가 하나씩 배치된다. 메모리 장치(100)의 외곽에는 복수개의 데이터 입출력 패드들(170)이 배치되어 있다.As shown, in the memory device 100 according to the present invention, a memory cell array is divided into a plurality of banks A and B, for example. The bank A and the bank B are divided into a plurality of, for example, eight memory blocks 102 to 116 and 202 to 216 having the same size, and the respective memory blocks of the bank A and the bank B alternate with each other in the transverse direction. Is placed. That is, the first block 102 of the bank A, the first block 202 of the bank B, the second block 104 of the bank A and the second block 204 of the bank B are arranged laterally adjacent to each other, The remaining 12 blocks are similarly arranged. A pair of memory blocks, e.g., the first block 102 of bank A and the first block 202 of bank B, may comprise input / output lines (I / O,

) Are arranged to be shared. Therefore, one input / output line sense amplifier 150 and one write driver 160 are disposed per pair of memory blocks, that is, two memories. The plurality of data input / output pads 170 are disposed outside the memory device 100.

As described above, unlike the prior art (see FIG. 2) in which two longitudinally neighboring memory blocks share an input / output line, the two neighboring memory blocks in a horizontal direction share an input / output line. Therefore, the length of the input / output line is reduced to almost 1/2, thereby increasing the operating speed of the memory device. In addition, as illustrated, since the input / output line sense amplifier 150 and the write driver 160 need to be disposed in the two memory block widths 2a, the size of the memory cells is reduced and the memory block widths a are reduced. Even if compared to the conventional space can be secured. Therefore, even if a plurality of input / output line structures are employed to increase the output bandwidth, a space in which a plurality of input / output sense amplifiers and write drivers corresponding thereto are disposed is secured. In addition, the number of column select switches connected to the input / output line is reduced to 1/2, so that the parasitic capacitance is reduced, thereby increasing the data transmission speed. This will be described with reference to FIG. 4.

FIG. 4 is a diagram illustrating the arrangement of memory banks and input / output lines when the two memory banks illustrated in FIG. 3 are provided.

)과 각 메모리 뱅크의 각 비트라인(BL,

)에 대응되는 비트라인 감지 증폭기들(130, 140, 230, 240)이 구비된다.As shown in FIG. 4, the memory device according to the present invention includes a plurality of memory banks arranged in a row, for example, banks A and B. FIG. The memory device may further include input / output lines (I / O, shared in the banks A and B).

) And each bit line BL of each memory bank

Bit line sense amplifiers 130, 140, 230, and 240 corresponding to the N th) are provided.

)은 각 메모리 뱅크로 기입되거나 메모리 뱅크로부터 독출되는 데이터를 전송하는 역할을 하며, 상기 비트라인 감지 증폭기들(130, 140, 230, 240)은 로우 어드레스(row adress)에 응답하여 출력되는 비트라인(BL,

) 데이터를 감지하고 증폭하는 역할을 한다. 본 발명의 일 실시예에 따른 상기 입출력 라인(I/O,

)은 출력 밴드폭을 증가시킬 수 있도록 복수개로 구성될 수 있으며, 이 경우, 각 입출력 라인에 입출력 라인 감지 증폭기(150)와 기입 드라이버(160)가 배치된다.The input / output line (I / O,

) Transmits data written to or read from each memory bank, and the bit line sense amplifiers 130, 140, 230, and 240 are output in response to a row address. (BL,

) It senses and amplifies data. The input / output line (I / O, according to an embodiment of the present invention)

) May be configured in plural to increase the output bandwidth. In this case, the input / output line sense amplifier 150 and the write driver 160 are disposed in each input / output line.

)과 비트라인 감지 증폭기들(130, 140, 230, 240)은 칼럼 선택 스위치부들(180, 190)을 통해 연결된다. 상기 칼럼 선택 스위치부들(180, 190) 각각은, 뱅크 선택 스위치들(132, 142, 232, 242)과 칼럼 선택 스위치들(134, 144)를 구비한다. 본 발명의 바람직한 실시예에 따르면, 상기 뱅크 선택 스위치들(132, 142, 232, 242)은 메모리 뱅크별로 배치된 비트라인 감지 증폭기에 대응되도록 배치되며, 상기 칼럼 선택 스위치들(134, 144)은 복수개의 메모리 뱅크 즉, 뱅크 A와 뱅크 B에 공유된다.The input / output line (I / O,

) And the bit line sense amplifiers 130, 140, 230, and 240 are connected through the column select switch units 180 and 190. Each of the column select switch units 180 and 190 includes bank select switches 132, 142, 232, and 242 and column select switches 134 and 144. According to a preferred embodiment of the present invention, the bank select switches 132, 142, 232, and 242 are arranged to correspond to bit line sense amplifiers arranged for each memory bank, and the column select switches 134 and 144 may be arranged. It is shared by a plurality of memory banks, that is, banks A and B.

) 사이에 위치하여, 대응되는 비트라인 감지 증폭기들로부터 출력되는 데이터를 입출력 라인으로 전송하거나, 외부로부터 입력되는 데이터를 상기 비트라인 감지 증폭기로 전달한다.The bank select switches 132, 142, 232, and 242 and the column select switches 134 and 144 may include bit line sense amplifiers 130, 140, 230, and 240 and input / output lines (I / O,

) And transmit data output from the corresponding bit line sense amplifiers to the input / output line, or transfer data input from the outside to the bit line sense amplifier.

The column select switches 134 and 144 shared in the bank A and the bank B are connected to the column select lines CSLi and CSLn selected by the column address and driven by activation of the column select line. The bank select switches 132, 142, 232, and 242 are driven by activation of separate bank select signals? BSA and? BSB. The bank selection signals? BSA and? BSB are signals driven after a predetermined time delay from a low active operation of a corresponding memory bank. Preferably, the bank selection signals? The bit line sense amplifiers 130, 140, 230, and 240 are activated signals after the amplification of the voltage difference between the bit line pairs.

The column select switches 134 and 144 and the bank select switches 132, 142, 232, and 242 may be configured as NMOS transistors, and both the column select switch and the bank select control switch may be turned on. Only when turned on, data can be written to or read from the memory cell. That is, the column select switch units 134 and 144 according to the present invention are selected even if the column select line is activated so that the column select switches 134 and 144 shared between the bank A and the bank B are turned on. If the switches 132, 142, 232, and 242 are not turned on, the data writing or reading operation is impossible.

As described above, since the memory bank information is input and the data is read from the corresponding memory bank in the state in which the low active operation of the memory bank is completed, one data is selectively loaded on the input / output line shared in the plurality of memory banks.

As mentioned above, bank A and bank B not only share the input / output lines, but also the column select switches. As a result, the number of the column select switches connected to the input / output lines is reduced to 1/2 compared with the related art. Therefore, the capacitive load present in the input / output line may be reduced, thereby increasing the data transfer rate.

FIG. 5 is a diagram illustrating an arrangement of memory banks according to a second embodiment of the present invention. The second embodiment of the present invention is the same as the first embodiment except for the case where four memory banks are provided, and the same reference numerals denote the same members.

)을 공유하도록 배치된다. 따라서, 4 개의 메모리 블록당 입출력 라인 감지 증폭기(150)와 기입 드라이버(160)가 하나씩 배치된다. 여기서, 출력 밴드 폭을 증가시키기 위해 상기 입출력 라인이 복수개 구비되는 경우, 상기 입출력 라인 감지 증폭기(150)와 기입 드라이버(160)는 입출력 라인과 동일한 개수로 구비된다.As shown, in the memory device 300 according to another embodiment of the present invention, the memory cell array is divided into four memory banks (bank A, bank B, bank C, and bank D). Banks A through D are each divided into a plurality of, for example, four memory blocks 302 to 308, 402 to 408, 502 to 508, and 602 to 608, each having the same size, and the blocks alternate with each other laterally Are arranged. That is, the first block 302 of the bank A, the first block 402 of the bank B, the first block 502 of the bank C, the first block 602 of the bank D are disposed adjacent to each other in the lateral direction, The remaining 12 blocks are similarly arranged. Four memory blocks, for example, the first blocks 302, 402, 502, and 602 of banks A, B, C, and D may include an input / output line (I / O,

) Is arranged to share. Thus, one input / output line sense amplifier 150 and one write driver 160 are disposed per four memory blocks. Here, when a plurality of input / output lines are provided to increase the output bandwidth, the input / output line sense amplifier 150 and the write driver 160 are provided in the same number as the input / output lines.

As described above, the semiconductor memory device of the present invention has the following advantages.

First, since a plurality of horizontally adjacent memory banks share input / output lines, the input / output sense amplifier and the write driver can be shared, thereby reducing the layout area.

Second, since the column select switches are shared in a plurality of (N) memory banks, the number of column select switches connected to the input / output lines is reduced to 1 / N, so that the parasitic capacitance is reduced and the data transfer rate can be increased.

Third, since the input / output line sense amplifier and the write driver need to be disposed within a plurality of block widths, even if the size of the memory cell becomes small and the memory block width becomes small, it is possible to secure a space margin as compared with the related art. Therefore, even if a plurality of input / output line structures are employed to increase the output bandwidth, a space in which a plurality of input / output sense amplifiers and write drivers are disposed is secured, thereby improving layout efficiency.

1 is a diagram illustrating an arrangement of a memory bank and an input / output line of a conventional semiconductor memory device having two memory banks.

2 is a diagram illustrating another conventional example in which a memory bank and an input / output line are disposed.

3 is a schematic block diagram illustrating a memory device according to a first embodiment of the present invention.

FIG. 4 is a diagram illustrating the arrangement of memory banks and input / output lines when the two memory banks illustrated in FIG. 3 are provided.

5 is a schematic block diagram illustrating a memory device according to a second embodiment of the present invention.

Claims (5)

A plurality of memory banks each divided into a plurality of memory blocks of the same size; At least one input / output line shared by the plurality of memory banks arranged in a row, and configured to transmit data written to or read from each memory bank; A bit line sense amplifier disposed in each of the memory banks and configured to sense and amplify bit line data of the memory bank output in response to a row address; And A column select switch for transmitting the output of the bit line sense amplifier to the input / output line by activation of a predetermined bank select signal and a column select line selected by a column address, Each block of the plurality of memory banks is arranged alternately adjacent to blocks of the other memory banks at least once in a row, Wherein each of the input / output line, the bit line sense amplifier, and the column select switch unit are shared by blocks of a plurality of other memory banks arranged in the row, and are disposed within a width of the shared plurality of memory blocks. Memory device. The method of claim 1, wherein the column selection switch unit, A bank select switch disposed to correspond to the bit line sense amplifier and transmitting an output signal of the bit line sense amplifier by activating the bank select signal; And And a column select switch shared by the plurality of memory banks and configured to transmit a signal transmitted by the bank select switch to the data input / output line.  The method of claim 2, wherein the bank selection signal, And a bit line data output from the selected memory bank is a signal which is activated after being sufficiently amplified.  The semiconductor memory device of claim 2, wherein the column select switch and the bank select switch are configured of NMOS transistors.  The memory device of claim 1, wherein the memory device comprises: An input / output sense amplifier installed by the number of input / output lines so as to sense, amplify, and output a signal transmitted from the bit line sense amplifier to the input / output line; And And a write driver for transmitting a signal output from the input / output sense amplifier.

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