CN104281545A - Data reading method and data reading equipment - Google Patents
Data reading method and data reading equipment Download PDFInfo
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- CN104281545A CN104281545A CN201310291218.2A CN201310291218A CN104281545A CN 104281545 A CN104281545 A CN 104281545A CN 201310291218 A CN201310291218 A CN 201310291218A CN 104281545 A CN104281545 A CN 104281545A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/282—Cycle stealing DMA
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/28—DMA
- G06F2213/2806—Space or buffer allocation for DMA transfers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention discloses a data reading method and data reading equipment, which relate to the field of computers and are capable of reducing operation complexity and power consumption during the sequential reading of mass data. The concrete scheme is that the data reading method comprises the following steps: sending the row address, in a memory, of data which needs to be read to the memory by an MC (memory controller) so as to enable the memory to conveniently store data in the corresponding row of the row address in the memory into a buffer zone of the memory; sending a first command to the memory by the MC so as to enable the memory to conveniently traverse all column addresses according to the first command to send the data which need to be read to the MC, wherein the data which need to be read are all the data which are stored in the buffer zone and are in the corresponding row of the row address, and the first command is used for activating a direct memory in the memory to access a DMA (direct memory access) logic; receiving the data which need to be read and are sent by the memory by the MC. The data reading method and data reading equipment disclosed by the invention are used in a data reading process.
Description
Technical field
The present invention relates to computer realm, particularly relate to a kind of method for reading data and equipment.
Background technology
As everyone knows, computer system generally by processor, internal memory, input equipment, output device and bus five part form, wherein internal memory be used to specimens preserving device run needed for data and instruction, dynamic RAM (Dynamic Random Access Memory, DRAM) is that the main flow of the internal memory of current computer system realizes.
All generally that the mode adding row by row realizes to the reading of data in DRAM, concrete, as Memory Controller Hub (Memory Controller, MC) central processing unit (Center Processing Unit is received, during the data access instruction CPU) sent, first data access instruction is resolved to the row address and column address that obtain needing the data of access in DRAM, then row address is sent to DRAM, to make DRAM, the data of this row address corresponding row are stored in row buffer (row buffer), finally again column address is sent to DRAM, such DRAM just can choose the data block needing to read from row buffer according to the column address received, and be sent in the buffer memory of MC by the data line between DRAM and MC, CPU is sent to by needing the data block read again by MC.This shows, traditional method for reading data functionally can meet requirements for access, but under such as reading the scene such as large files or playing video file, CPU needs from DRAM, get a large amount of data of continuous print, traditional method is that CPU sends multiple data access instruction to MC, so that MC constantly sends multiple column address to DRAM, like this to guarantee to read a large amount of continuous print data, but such complicated operation and power consumption is high.
This needs are read continuously to the scene of mass data, prior art provides a solution, at third generation double data rate Synchronous Dynamic Random Access Memory (Double-Data-Rate Three Synchronous Dynamic Random Access Memory, DDR3SDRAM) in specification, the operation that (burst read) is read in a kind of burst is proposed, particularly by burst read order, MC only needs to send a row address and a column address to DRAM, DRAM just can by the continuous print N(N<9 from this column address) individual data block reads and is sent to MC.
In prior art, at least there are the following problems: well-known, in DRAM, the size of data line is generally 4KB-64KB, and in the specification of DDR3SDRAM, carry out the reading of data with the data bit width of maximum 8 times from the angle of MC, that is the size of disposable maximum reading data is 512bit, granularity is larger than traditional 64bit or 128bit, but still much smaller than the size of data line in DRAM, to read the data line of the DRAM of buffer memory in whole row buffer, still need repeatedly to send burst read order, that is still there will be complicated operation and the problems such as power consumption height.Therefore, needing to read continuously in the scene of mass data, how at reduction operation complexity, and reducing the important topic that power consumption height has become those skilled in the art's research.
Summary of the invention
Embodiments of the invention provide a kind of method for reading data and equipment, reduce the operation complexity in mass data reading process continuously and power consumption.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A first aspect of the present invention, provides a kind of method for reading data, comprising:
Memory Controller Hub MC is sent to described storer, so that described storer is stored in the buffer zone of described storer by described storer with the data of described row address corresponding row by needing the data row address in memory read;
Described MC sends the first order to described storer, so that the described data read that need are sent to described MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row, and described first order is for activating the direct memory access logic in described storer;
Described MC receives the described data needing to read that described storer sends.
In conjunction with first aspect, in a kind of possible implementation, before the row address of the data needing reading is sent to storer by described Memory Controller Hub MC, also comprise:
Described MC receives the data access instruction that central processor CPU sends; Wherein, described data access instruction comprises the data described row address in which memory that described needs read;
Described MC resolves described data access instruction and obtains described row address.
In conjunction with first aspect and above-mentioned possible implementation, in the implementation that another kind is possible, described data access instruction comprises sign, and it is all data of described row address corresponding row that described sign is used to indicate the described data read that need;
Described MC resolves described data access instruction and obtains described row address, comprising:
Described MC resolves described data access instruction and obtains described row address and described sign;
Described MC sends the first order to described storer, comprising:
Described MC sends described first order according to described sign to described storer.
In conjunction with first aspect and above-mentioned possible implementation, in the implementation that another kind is possible, described method also comprises:
When not needing to write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in storing in described buffer zone, described MC sends the second order to described storer, so that described storer cuts out the row corresponding with described row address, and the bit line (bitline) in described storer is set to predeterminated voltage; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
In conjunction with first aspect and above-mentioned possible implementation, in the implementation that another kind is possible, after described MC receives the data of the described needs reading that described storer sends, also comprise:
When zeros data need be carried out with described row address corresponding row in described storer, described MC sends the 3rd order to described storer, so that described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order, and writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
A second aspect of the present invention, provides a kind of method for reading data, comprising:
Storer receives the row address that Memory Controller Hub MC sends; Wherein, described row address is the data row address in which memory needing to read;
Described storer is stored in the buffer zone of described storer by described storer with the data of described row address corresponding row;
Described storer receives the first order that described MC sends; Wherein, described first order is for activating the direct memory access logic in described storer;
The described data read that need are sent to described MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row.
In conjunction with second aspect, in a kind of possible implementation, also comprise:
Described storer receives the second order that described MC sends; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone;
Described storer cuts out the row corresponding with described row address, and the bit line (bitline) in described storer is set to predeterminated voltage.
In conjunction with second aspect and above-mentioned possible implementation, in the implementation that another kind is possible, described storer according to described first order traversal all column addresss by described need read data be sent to described MC after, also comprise:
Described storer receives the 3rd order that described MC sends; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row;
Described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order;
Described storer writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing.
A third aspect of the present invention, provides a kind of Memory Controller Hub, comprising:
First transmitting element, for needing the data row address in memory read to be sent to described storer, so that described storer is stored in the buffer zone of described storer by described storer with the data of described row address corresponding row;
Second transmitting element, for sending the first order to described storer, so that the described data read that need are sent to described Memory Controller Hub MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row, and described first order is for activating the direct memory access logic in described storer;
First receiving element, for receiving the described data needing to read that described storer sends.
In conjunction with the third aspect, in a kind of possible implementation, also comprise:
Second receiving element, before the row address of the data needing reading being sent to storer at described first transmitting element, receives the data access instruction that central processor CPU sends; Wherein, described data access instruction comprises the data described row address in which memory that described needs read;
Resolution unit, the described data access instruction obtained for resolving described second receiving element obtains described row address.
In conjunction with the third aspect and above-mentioned possible implementation, in the implementation that another kind is possible, described data access instruction comprises sign, and it is all data of described row address corresponding row that described sign is used to indicate the described data read that need;
Described resolution unit, the described data access instruction obtained specifically for resolving described second receiving element obtains described row address and described sign;
Described second transmitting element, sends described first order specifically for the described sign obtained according to described resolution unit to described storer.
In conjunction with the third aspect and above-mentioned possible implementation, in the implementation that another kind is possible, also comprise:
4th transmitting element, for when not needing to write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in storing in described buffer zone, the second order is sent to described storer, so that described storer cuts out the row corresponding with described row address, and is set to predeterminated voltage by described storer for bit line (bitline);
Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
In conjunction with the third aspect and above-mentioned possible implementation, in the implementation that another kind is possible, also comprise:
5th transmitting element, after the data that the described needs sent for receiving described storer at described first receiving element read, when zeros data need be carried out with described row address corresponding row in described storer, the 3rd order is sent to described storer, so that described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order, and writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
A fourth aspect of the present invention.A kind of storer is provided, comprises:
First receiving element, for receiving the row address that Memory Controller Hub MC sends; Wherein, described row address is the data row address in which memory needing to read;
Storage unit, for being stored in the buffer zone of described storer by the data of the described row address corresponding row obtained with described first receiving element in described storer;
Second receiving element, for receiving the first order that described MC sends; Wherein, described first order is for activating the direct memory access logic in described storer;
The described data read that need are sent to described MC for all column addresss of described first order traversal obtained according to described second receiving element by transmitting element; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row.
In conjunction with fourth aspect, in a kind of possible implementation, also comprise:
3rd receiving element, for receiving the second order that described MC sends; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone;
Processing unit, for closing the row corresponding with described row address, and is set to predeterminated voltage by the bit line (bitline) in described storer.
In conjunction with fourth aspect and above-mentioned possible implementation, in the implementation that another kind is possible, also comprise:
4th receiving element, for described transmitting element according to described first order traversal all column addresss by described need read data be sent to described MC after, receive described MC send the 3rd order; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row;
Reset unit, all reset with the data of described row address corresponding row described in storing in described buffer zone for described 3rd order obtained according to described 4th receiving element;
Write back unit, for writing back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after described clearing unit clearing.
The method for reading data that the embodiment of the present invention provides and equipment, MC is sent to storer by needing the data row address in memory read, so that storer is stored in the buffer zone of storer by storer with the data of row address corresponding row, then MC sends the first order to storer, MC is sent to according to all column addresss of the first order traversal by needing the data read to make storer, now MC just can reception memorizer send needs read data, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, DRAM activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of method for reading data process flow diagram that Fig. 1 provides for one embodiment of the invention;
A kind of method for reading data process flow diagram that Fig. 2 provides for another embodiment of the present invention;
The another kind of method for reading data process flow diagram that Fig. 3 provides for another embodiment of the present invention;
Fig. 4 is that the one of data read operation provided by the invention simplifies state machine diagram;
A kind of Memory Controller Hub composition schematic diagram that Fig. 5 provides for another embodiment of the present invention;
The another kind of Memory Controller Hub composition schematic diagram that Fig. 6 provides for another embodiment of the present invention;
A kind of storer composition schematic diagram that Fig. 7 provides for another embodiment of the present invention;
The another kind of storer composition schematic diagram that Fig. 8 provides for another embodiment of the present invention;
Another Memory Controller Hub composition schematic diagram that Fig. 9 provides for another embodiment of the present invention;
Another storer composition schematic diagram that Figure 10 provides for another embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
One embodiment of the invention provides a kind of method for reading data, and as shown in Figure 1, the method can comprise:
101, MC is sent to storer, so that storer is stored in storer in the buffer zone of storer with the data of row address corresponding row by needing the data row address in memory read.
Wherein, MC can be sent to storer, so that storer is by being stored in the buffer zone of storer with the data of this row address corresponding row of storing in storer by needing the data row address in memory read.
Optionally, before the data row address in memory that needs read can be sent to storer by MC, MC can receive the data access instruction that CPU sends, wherein, this data access instruction is that CPU needs to send when reading data from storer, and this data access instruction comprises the data row address in memory that needs read, after MC receives data access instruction, just can the data access instruction received be resolved, obtain the data row address in memory that CPU needs to read.
Further alternative, can also comprise sign in data access instruction, this sign is used to indicate needs the data read to be all data of row address corresponding row, and so MC can obtain row address and sign by resolution data access instruction.
102, MC sends the first order to storer, so that storer is sent to MC according to all column addresss of the first order traversal by needing the data read.Wherein, the data read are needed to be that store in buffer zone with all data that are row address corresponding row.
Wherein, in the application scenarios reading large files or playing video file, need from storer, read a large amount of continuous print data, the data read now are needed to be that store in buffer zone with all data that are row address corresponding row, so MC just can send the first order to storer, so that storer can travel through all column addresss according to the first order, by store in buffer zone and all data of row address corresponding row be sent in the buffer memory of MC by the data line between storer and MC, like this in the scene such as reading the needs such as large files or playing video file continuous reading mass data, by the single command that MC sends to storer, achieve the reading of continuous mass data.Wherein this first order is for activating direct memory access (DMA) (Direct Memory Access, the DMA) logic in storer.
Optionally, when data access instruction comprises sign, and MC resolution data access instruction is when obtaining this sign, so MC just can send the first order according to this sign to storer, concrete can be indicate CPU to need to read a large amount of continuous print data with a bit in data access instruction, so now MC just can send the first order to storer, so as storer can by store in buffer zone with all digital independent of row address corresponding row out.Be understandable that, if do not comprise sign in data access instruction, or contain the column address needing to read data, so conventionally can send column address, so that storer by the digital independent corresponding with column address out directly to storer.
103, the data that the needs that MC reception memorizer sends read.
Wherein, the first order is sent to storer at MC, storer according to first order traversal all column addresss by store in buffer zone be sent to MC with the data of row address corresponding row after, MC just can reception memorizer send needs read data, and the data received are stored in the buffer memory of MC, the data read will be needed to be sent to CPU, and then CPU is made to obtain the data needing reading.
It should be noted that, the storer in the embodiment of the present invention can be DRAM, and the embodiment of the present invention does not do concrete restriction at this to storer.
The method for reading data that the embodiment of the present invention provides, MC is sent to storer by needing the data row address in memory read, so that storer is stored in the buffer zone of storer by storer with the data of row address corresponding row, then MC sends the first order to storer, MC is sent to according to all column addresss of the first order traversal by needing the data read to make storer, now MC just can reception memorizer send needs read data, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, DRAM activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
Another embodiment of the present invention provides a kind of method for reading data, and as shown in Figure 2, the method can comprise:
201, storer receives the row address that MC sends.Wherein, this row address is the data row address in memory needing to read.
Wherein, when CPU needs the reading carrying out data, data read command can be sent to MC, MC resolves the data read command received, obtain the data row address in memory that CPU needs to read, then be sent to storer by resolving the row address obtained, now storer just can receive the row address that MC sends.
202, storer is stored in storer in the buffer zone of storer with the data of row address corresponding row.
Wherein, after MC receives the row address of MC transmission, just according to the row address received, can be stored in storer in the buffer zone of storer with the data of this row address corresponding row.
203, storer receives the first order that MC sends.
Wherein, in the application scenarios reading large files or playing video file, need from storer, read a large amount of continuous print data, MC can send the first order to storer, and then storer just can receive the first order that MC sends.Wherein this first order is for activating the dma logic in storer.
204, storer is sent to MC according to all column addresss of the first order traversal by needing the data read.Wherein, the data that these needs read are that store in buffer zone with all data that are row address corresponding row
Wherein, after storer receives the first order of MC transmission, just the dma logic in storer can be activated, now dma logic just can send according to sequential the column address added up from 0, such storer just can travel through all column addresss by store in buffer zone with the reading of all data sequence of row address corresponding row, obtain the data needing to read, and be sent in the buffer memory of MC by the data line between storer and MC by needing the data read, so that the data that the needs received read are sent to CPU by MC, and then make CPU obtain the data needing reading.
It should be noted that, the storer in the embodiment of the present invention can be DRAM, and the embodiment of the present invention does not do concrete restriction at this to storer.
The method for reading data that the embodiment of the present invention provides, the row address that storer sends according to the MC received, be stored in the buffer zone of storer by storer with the data of this row address corresponding row, then according to the first order that the MC received sends, dma logic in storer is activated, make storer can travel through all column addresss and be sent to MC by needing the data read, so that the data that the needs received read are sent to CPU by MC, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, storer activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
Another embodiment of the present invention provides a kind of method for reading data, and as shown in Figure 3, the method can comprise:
As everyone knows, such as reading, large files or playing video file etc. are continuous to be read in the application scenarios of mass data, can first data be read internal memory from hard disk, then so that CPU can read a large amount of data by continuous print, but the scheme reading continuous mass data in prior art has complicated operation, the defects such as power consumption is large, the method of the digital independent that the embodiment of the present invention provides, by adding new order, make reading in the application scenarios of mass data continuously, the operation complexity in mass data reading process continuously and power consumption can be effectively reduced, concrete implementation process can with reference to following steps.
301, MC receives the data access instruction that CPU sends.
Wherein, when CPU needs the reading carrying out data, can send data access instruction to MC, now MC just can receive the data access instruction that CPU sends.Wherein, can comprise the data row address in memory that needs read, can also comprise sign in this data access instruction, this sign is used to indicate needs the data read to be all data of row address corresponding row.
302, MC resolution data access instruction obtains row address and sign.
Wherein, after MC receives the data access instruction of CPU transmission, just can the data access instruction received be resolved, obtain the row address comprised in data access instruction, and the sign comprised in data access instruction.
303, row address is sent to storer by MC.
Wherein, after MC resolution data access instruction obtains row address, can send this row address to storer, this row address can be sent to storer by ACTIVE order.
304, storer is stored in storer in the buffer zone of storer with the data of row address corresponding row.
Wherein, after storer receives the row address of MC transmission, just can be stored in storer in the buffer zone of storer with the data of row address corresponding row.
305, MC sends the first order according to sign to storer.
Wherein, from step 301, it is be used to indicate to need the data read to be all data of row address corresponding row that MC resolves the sign obtained, so in embodiments of the present invention, MC does not send read command (wherein comprising the column address of the data of needs access in this read command) to storer, but the newer command of embodiment of the present invention interpolation is sent to storer, namely MC sends the first order to storer, and this first order is for activating the dma logic in storer.
It should be noted that, in the embodiment of the present invention, new the first order added can existing control command uses in multiplexing prior art pin represent, such as, and the pin used during multiplexing transmission read command, if certainly there is the untapped pin of existing control signal, also the pin that existing control command uses can not be used, but adopt the combination of untapped pin or untapped pin to represent, first the Read order of such as DDR3 can use A0-A15 selected line, then A0-A9 is used, A11 chooses row, the A12-A15 do not used when sending column address can be adopted in the embodiment of the present invention to encode, such as A12-A15 pin is adopted to be 0001, activate the dma logic reading full line, to reach the object reading full line, also just say when A12-A15 pin is 0001, represent that MC have sent RAS_READ order to storer.
306, storer is sent to MC according to all column addresss of the first order traversal by needing the Data Data read.Wherein, the data read are needed to be that store in buffer zone with all data that are row address corresponding row
Wherein, in embodiments of the present invention, when being all data with row address corresponding row of storage in buffer zone when needing the data read, that single command reads storage in buffer zone with all data that are row address corresponding row in order to realize, the embodiment of the present invention increases a simple dma logic in memory, this dma logic is after the first order receiving MC transmission, the column address added up from 0 can be sent according to sequential control, like this after storer receives the first order of MC transmission, dma logic in storer is activated, now storer just can travel through all column addresss, and then according to store in the reading buffer zone of temporal order with all data of row address corresponding row, and the data read out are sent in the buffer memory of MC by the data line between MC.Such as, the size of buffer zone is 4KB, and that store in buffer zone is also 4KB with size that the is data of row address corresponding row, data bit width between storer and MC is 64bit, namely 8 bytes, according to the size of the data bit width between storer and MC and buffer zone, can obtain column address is 9, the dma logic so now added in memory needs it can export the column address signal (0-511) of 9 according to sequential, so that storer can store in the reading buffer zone of order with all data of row address corresponding row, and all data read are sent in the buffer memory of MC.Wherein, in order to ensure that storer can read out the data of the storage of buffer zone accurately according to sequential, dma logic needs to produce column address in strict accordance with the reading sequential of storer.
Optionally, when MC receives the data of the needs reading that storer sends, following steps 307 can be performed:
307, MC is sent to CPU by needing the data read.
Wherein, when MC receive that storer sends with the data of row address corresponding row after, just can be sent to CPU by what receive with the data of row address corresponding row, so that CPU obtains the data needing to read.
Optionally, as everyone knows, read in the process of data each, also need the data that the last time stored in buffer zone accesses to be write back in row corresponding to storage unit in storer, and the bitline of buffer zone is set to predeterminated voltage, but in a lot of application scenarios, there will be data just useless after running through, the process that so writes back just becomes nonsensical, but also can bring corresponding power consumption.Such as, when memory source is nervous, current no internal storage data just can be exchanged to disk to reach recovery internal memory by exchange (Swap) technology, and the data read at this moment just need not write-back again.Therefore the data that in the embodiment of the present invention, step 308-step 309 does not need after achieving reading by the new order added no longer write back, and are the ready work of reading of data next time.
308, when store in buffer zone do not need to write back in row corresponding with row address in storer with the data of row address corresponding row time, MC to storer send second order.
Wherein, when store in buffer zone do not need to write back in row corresponding with row address in storer with the data of row address corresponding row time, MC can send the second order to storer.Such as, the second order be PRECHARGE_WITHOUT_RESTORE order, and the description of refer step 305, and when can to work as A12-A15 pin be 0010, expression sends PRECHARGE_WITHOUT_RESTORE order.Wherein, this second order is used to indicate storer does not need writing back in storer with row address corresponding row with the data of row address corresponding row of storing in buffer zone.
309, storer cuts out the row corresponding with row address, and the bit line (bitline) in storer is set to predeterminated voltage.
Wherein, after storer receives the second order of MC transmission, storer do not perform by store in buffer zone with the data of row address corresponding row write back in storer with the operation in row address corresponding row, but directly close the row corresponding with row address, and the bitline in storer is set to predeterminated voltage, and now storer will enter idle condition, when waiting the row address again receiving MC transmission, enter state of activation again, carry out the read operation of data next time.That is with the addition of new be used to indicate storer do not need by store in buffer zone with the data of row address corresponding row write back in storer with the order in row address corresponding row after, storer carries out the simplification state machine of read operation as shown in Figure 4, BA wherein in Fig. 4 is the abbreviation of BankActive, for memory block activates, it is a block of the storage particle of composition storer, PRE is the abbreviation of precharge, refers to pre-charged.It should be noted that, need in the simplification state machine shown in Fig. 4 read data be in certain row certain row data, therefore after the storage area activation of block according to column address read need data.
It should be noted that, in the embodiment of the present invention, step 308-step 309 can perform after the step 307, can perform on carrying out before digital independent once again, and the embodiment of the present invention did not limit in this concrete execution time to step 308-step 309.
Optionally, " zero page (data are the page of 0 entirely) " is distributed in the application scenarioss such as kernel thread use at the kernel of such as operating system, operating system and application developer are in order to routine data safety, often there is the operation being carried out by the bulk memory of distribution resetting, prior art is ceaselessly write zero to internal memory by normal write operation and is realized, and such operating efficiency is very low.The full line that in the embodiment of the present invention, step 310-step 311 achieves storer by new the 3rd order added resets, and improves the efficiency of clear operation.
310, when carrying out zeros data with row address corresponding row in storer, MC sends the 3rd order to storer.
Wherein, when zeros data need be carried out with row address corresponding row in storer, MC sends the 3rd order to storer, such as, the 3rd order is BUF_RESET order, and reference table 1, when can to work as A12-A15 pin be 0011, represent and send BUF_RESET order, wherein, the 3rd order is used to indicate storer by the zeros data with row address corresponding row.
311, storer is ordered all resetting with the data of row address corresponding row of storing in buffer zone according to the 3rd, and by writing back in row corresponding with row address in storer with the data of row address corresponding row after clearing.
Wherein, when storer receives the 3rd order of MC transmission, can gating buffer zone self reset logic or be gated for buffer zone add reset logic, by the whole clearing disposable with the data of row address corresponding row stored in buffer zone, then by writing back in row corresponding with row address in storer with the data of row address corresponding row after clearing.
The method for reading data that the embodiment of the present invention provides, MC is sent to storer by needing the data row address in memory read, so that storer is stored in the buffer zone of storer by storer with the data of row address corresponding row, then MC sends the first order to storer, MC is sent to according to all column addresss of the first order traversal by needing the data read to make storer, now MC just can reception memorizer send needs read data, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, DRAM activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
And, for the data do not re-used after reading, storer no longer carries out written-back operation, reduce further power consumption, and storer is by efficiently resetting buffer zone, achieve the clearing to bulk contiguous memory in storer, improve clear operation efficiency and reduce CPU and MC control burden.
Another embodiment of the present invention provides a kind of Memory Controller Hub, as shown in Figure 5, comprising: the first transmitting element 41, second transmitting element 42, first receiving element 43.
First transmitting element 41, for needing the data row address in memory read to be sent to described storer, so that described storer is stored in described storer in the buffer zone of described storer with the data of described row address corresponding row.
Second transmitting element 42, for sending the first order to described storer, so that the described data read that need are sent to described Memory Controller Hub MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row, and described first order is for activating the direct memory access logic in described storer.
First receiving element 43, for receiving the described data needing to read that described storer sends.
Further, described Memory Controller Hub can also comprise: the second receiving element 44, resolution unit 45.
Second receiving element 44, before the row address of the data needing reading being sent to storer at described first transmitting element 41, receives the data access instruction that central processor CPU sends; Wherein, described data access instruction comprises the data described row address in which memory that described needs read.
Resolution unit 45, the described data access instruction obtained for resolving described second receiving element 44 obtains described row address.
Further, described data access instruction comprises sign, and it is all data of described row address corresponding row that described sign is used to indicate the described data read that need.
Described resolution unit 45, the described data access instruction obtained specifically for resolving described second receiving element 44 obtains described row address and described sign;
Described second transmitting element 42, sends described first order specifically for the described sign obtained according to described resolution unit 45 to described storer.
Further, as shown in Figure 6, described Memory Controller Hub can also comprise: the 4th transmitting element 46.
4th transmitting element 46, for when not needing to write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in storing in described buffer zone, the second order is sent to described storer, so that described storer cuts out the row corresponding with described row address, and is set to predeterminated voltage by described storer for bit line (bitline).
Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
Further, described Memory Controller Hub can also comprise: the 5th transmitting element 47.
5th transmitting element 47, after the data that the described needs sent for receiving described storer at described first receiving element 43 read, when zeros data need be carried out with described row address corresponding row in described storer, the 3rd order is sent to described storer, so that described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order, and writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
The Memory Controller Hub that the embodiment of the present invention provides, storer is sent to by needing the data row address in memory read, so that storer is stored in the buffer zone of storer by storer with the data of row address corresponding row, then MC sends the first order to storer, MC is sent to according to all column addresss of the first order traversal by needing the data read to make storer, now MC just can reception memorizer send needs read data, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, DRAM activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
And, for the data do not re-used after reading, storer no longer carries out written-back operation, reduce further power consumption, and storer is by efficiently resetting buffer zone, achieve the clearing to bulk contiguous memory in storer, improve clear operation efficiency and reduce CPU and MC control burden.
Another embodiment of the present invention provides a kind of storer, as shown in Figure 7, comprising: the first receiving element 51, storage unit 52, second receiving element 53, transmitting element 54.
First receiving element 51, for receiving the row address that Memory Controller Hub MC sends; Wherein, described row address is the data row address in which memory needing to read.
Storage unit 52, for being stored in the data of the described row address corresponding row obtained with described first receiving element 51 in described storer in the buffer zone of described storer.
Second receiving element 53, for receiving the first order that described MC sends; Wherein, described first order is for activating the direct memory access logic in described storer.
The described data read that need are sent to described MC for all column addresss of described first order traversal obtained according to described second receiving element 53 by transmitting element 54; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row.
Further, as shown in Figure 8, described storer can also comprise: the 3rd receiving element 55, processing unit 56.
3rd receiving element 55, for receiving the second order that described MC sends; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
Processing unit 56, for closing the row corresponding with described row address, and is set to predeterminated voltage by the bit line (bitline) in described storer.
Further, described storer can also comprise: the 4th receiving element 57, reset unit 58, write back unit 59.
4th receiving element 57, for described transmitting element 54 according to described first order traversal all column addresss by described need read data be sent to described MC after, receive described MC send the 3rd order; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
Reset unit 58, all reset with the data of described row address corresponding row described in storing in described buffer zone for described 3rd order obtained according to described 4th receiving element 57.
Write back unit 59, write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after described clearing unit 58 is reset.
The storer that the embodiment of the present invention provides, according to the row address that the MC received sends, be stored in the buffer zone of storer by storer with the data of this row address corresponding row, then according to the first order that the MC received sends, dma logic in storer is activated, make storer can travel through all column addresss and be sent to MC by needing the data read, so that the data that the needs received read are sent to CPU by MC, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, storer activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
And, for the data do not re-used after reading, storer no longer carries out written-back operation, reduce further power consumption, and storer is by efficiently resetting buffer zone, achieve the clearing to bulk contiguous memory in storer, improve clear operation efficiency and reduce CPU and MC control burden.
Another embodiment of the present invention provides a kind of Memory Controller Hub, as shown in Figure 9, comprising: transmitter 61, receiver 62.
Transmitter 61, for needing the data row address in memory read to be sent to described storer, so that described storer is stored in the buffer zone of described storer by described storer with the data of described row address corresponding row;
Described transmitter 61, also for sending the first order to described storer, so that the described data read that need are sent to described Memory Controller Hub MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row, and described first order is for activating the direct memory access logic in described storer.
Described receiver 62, for receiving the described data needing to read that described storer sends.
Further, described receiver 62, also for before the row address of data read is sent to storer, receiving the data access instruction that central processor CPU sends by needing at described transmitter 61; Wherein, described data access instruction comprises the data described row address in which memory that described needs read.
Described Memory Controller Hub can also comprise: processor 63.
Described processor 63, the described data access instruction obtained for resolving shown receiver 62 obtains described row address.
Further, described data access instruction comprises sign, and it is all data of described row address corresponding row that described sign is used to indicate the described data read that need.
Described processor 63, the described data access instruction obtained specifically for resolving described receiver 62 obtains described row address and described sign.
Described transmitter 61, sends described first order specifically for the described sign obtained according to described processor 63 to described storer.
Further, described transmitter 61, also for when not needing to write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in storing in described buffer zone, the second order is sent to described storer, so that described storer cuts out the row corresponding with described row address, and is set to predeterminated voltage by described storer for bit line (bitline).
Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
Further, described transmitter 61, after the data that the described needs also sent for receiving described storer at described receiver 62 read, when zeros data need be carried out with described row address corresponding row in described storer, the 3rd order is sent to described storer, so that described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order, and writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
The Memory Controller Hub that the embodiment of the present invention provides, storer is sent to by needing the data row address in memory read, so that storer is stored in the buffer zone of storer by storer with the data of row address corresponding row, then MC sends the first order to storer, MC is sent to according to all column addresss of the first order traversal by needing the data read to make storer, now MC just can reception memorizer send needs read data, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, DRAM activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
And, for the data do not re-used after reading, storer no longer carries out written-back operation, reduce further power consumption, and storer is by efficiently resetting buffer zone, achieve the clearing to bulk contiguous memory in storer, improve clear operation efficiency and reduce CPU and MC control burden.
Another embodiment of the present invention provides a kind of storer, as shown in Figure 10, comprising: bus interface 71, processor 72, and wherein, described bus interface 71 is for communicating with external unit.
Bus interface 71, for receiving the row address that Memory Controller Hub MC sends; Wherein, described row address is the data row address in which memory needing to read.
Processor 72, for being stored in the data of the described row address corresponding row obtained with described bus interface 71 in described storer in the buffer zone of described storer.
Described bus interface 71, also for receiving the first order that described MC sends; Wherein, described first order is for activating the direct memory access logic in described storer.
Described bus interface 71, for being sent to described MC according to all column addresss of described first order traversal by the described data read that need; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row.
Further, described bus interface 71, also for receiving the second order that described MC sends; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
Described processor 72, also for cutting out the row corresponding with described row address, and is set to predeterminated voltage by the bit line (bitline) in described storer.
Further, described bus interface 71, also for described according to described first order traversal all column addresss by described need read data be sent to described MC after, receive described MC send the 3rd order; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
Described processor 72, described 3rd order also for obtaining according to described bus interface 71 all resets with the data of described row address corresponding row described in storing in described buffer zone; And write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing.
The storer that the embodiment of the present invention provides, according to the row address that the MC received sends, be stored in the buffer zone of storer by storer with the data of this row address corresponding row, then according to the first order that the MC received sends, dma logic in storer is activated, make storer can travel through all column addresss and be sent to MC by needing the data read, so that the data that the needs received read are sent to CPU by MC, the data that these needs read are that store in buffer zone with all data that are row address corresponding row, storer activates the dma logic in storer by the first order received, MC is sent to all data of row address corresponding row to guarantee traveling through all column addresss by what store in buffer zone, just all data in buffer zone can be read like this by single command, reduce the operation complexity in mass data reading process continuously and power consumption.
And, for the data do not re-used after reading, storer no longer carries out written-back operation, reduce further power consumption, and storer is by efficiently resetting buffer zone, achieve the clearing to bulk contiguous memory in storer, improve clear operation efficiency and reduce CPU and MC control burden.
Through the above description of the embodiments, those skilled in the art can be well understood to the mode that the present invention can add required common hardware by software and realize, and can certainly pass through hardware, but in a lot of situation, the former is better embodiment.Based on such understanding, technical scheme of the present invention can embody with the form of software product the part that prior art contributes in essence in other words, this computer software product is stored in the storage medium that can read, as the floppy disk of computing machine, hard disk or CD etc., comprise some instructions and perform method described in each embodiment of the present invention in order to make a computer equipment (can be personal computer, server, or the network equipment etc.).
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (16)
1. a method for reading data, is characterized in that, comprising:
Memory Controller Hub MC is sent to described storer, so that described storer is stored in the buffer zone of described storer by described storer with the data of described row address corresponding row by needing the data row address in memory read;
Described MC sends the first order to described storer, so that the described data read that need are sent to described MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row, and described first order is for activating the direct memory access logic in described storer;
Described MC receives the described data needing to read that described storer sends.
2. method for reading data according to claim 1, is characterized in that, before the row address of the data needing reading is sent to storer by described Memory Controller Hub MC, also comprises:
Described MC receives the data access instruction that central processor CPU sends; Wherein, described data access instruction comprises the data described row address in which memory that described needs read;
Described MC resolves described data access instruction and obtains described row address.
3. method for reading data according to claim 2, is characterized in that, described data access instruction comprises sign, and it is all data of described row address corresponding row that described sign is used to indicate the described data read that need;
Described MC resolves described data access instruction and obtains described row address, comprising:
Described MC resolves described data access instruction and obtains described row address and described sign;
Described MC sends the first order to described storer, comprising:
Described MC sends described first order according to described sign to described storer.
4. the method for reading data according to any one of claim 1-3, is characterized in that, described method also comprises:
When not needing to write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in storing in described buffer zone, described MC sends the second order to described storer, so that described storer cuts out the row corresponding with described row address, and the bit line (bitline) in described storer is set to predeterminated voltage; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
5. the method for reading data according to any one of claim 1-3, is characterized in that, after described MC receives the data of the described needs reading that described storer sends, also comprises:
When zeros data need be carried out with described row address corresponding row in described storer, described MC sends the 3rd order to described storer, so that described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order, and writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
6. a method for reading data, is characterized in that, comprising:
Storer receives the row address that Memory Controller Hub MC sends; Wherein, described row address is the data row address in which memory needing to read;
Described storer is stored in the buffer zone of described storer by described storer with the data of described row address corresponding row;
Described storer receives the first order that described MC sends; Wherein, described first order is for activating the direct memory access logic in described storer;
The described data read that need are sent to described MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row.
7. method for reading data according to claim 6, is characterized in that, also comprises:
Described storer receives the second order that described MC sends; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone;
Described storer cuts out the row corresponding with described row address, and the bit line (bitline) in described storer is set to predeterminated voltage.
8. method for reading data according to claim 6, is characterized in that, described storer according to described first order traversal all column addresss by described need read data be sent to described MC after, also comprise:
Described storer receives the 3rd order that described MC sends; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row;
Described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order;
Described storer writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing.
9. a Memory Controller Hub, is characterized in that, comprising:
First transmitting element, for needing the data row address in memory read to be sent to described storer, so that described storer is stored in the buffer zone of described storer by described storer with the data of described row address corresponding row;
Second transmitting element, for sending the first order to described storer, so that the described data read that need are sent to described Memory Controller Hub MC according to all column addresss of described first order traversal by described storer; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row, and described first order is for activating the direct memory access logic in described storer;
First receiving element, for receiving the described data needing to read that described storer sends.
10. Memory Controller Hub according to claim 9, is characterized in that, also comprises:
Second receiving element, before the row address of the data needing reading being sent to storer at described first transmitting element, receives the data access instruction that central processor CPU sends; Wherein, described data access instruction comprises the data described row address in which memory that described needs read;
Resolution unit, the described data access instruction obtained for resolving described second receiving element obtains described row address.
11. Memory Controller Hub according to claim 10, is characterized in that, described data access instruction comprises sign, and it is all data of described row address corresponding row that described sign is used to indicate the described data read that need;
Described resolution unit, the described data access instruction obtained specifically for resolving described second receiving element obtains described row address and described sign;
Described second transmitting element, sends described first order specifically for the described sign obtained according to described resolution unit to described storer.
12. Memory Controller Hub according to any one of claim 9-11, is characterized in that, also comprise:
4th transmitting element, for when not needing to write back in row corresponding with described row address in described storer with the data of described row address corresponding row described in storing in described buffer zone, the second order is sent to described storer, so that described storer cuts out the row corresponding with described row address, and is set to predeterminated voltage by described storer for bit line (bitline);
Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone.
13. Memory Controller Hub according to any one of claim 9-11, is characterized in that, also comprise:
5th transmitting element, after the data that the described needs sent for receiving described storer at described first receiving element read, when zeros data need be carried out with described row address corresponding row in described storer, the 3rd order is sent to described storer, so that described storer all resets with the data of described row address corresponding row described in storing in described buffer zone according to described 3rd order, and writes back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after clearing; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row.
14. 1 kinds of storeies, is characterized in that, comprising:
First receiving element, for receiving the row address that Memory Controller Hub MC sends; Wherein, described row address is the data row address in which memory needing to read;
Storage unit, for being stored in the buffer zone of described storer by the data of the described row address corresponding row obtained with described first receiving element in described storer;
Second receiving element, for receiving the first order that described MC sends; Wherein, described first order is for activating the direct memory access logic in described storer;
The described data read that need are sent to described MC for all column addresss of described first order traversal obtained according to described second receiving element by transmitting element; Wherein, the described data read that need are that store in described buffer zone with all data that are described row address corresponding row.
15. storeies according to claim 14, is characterized in that, also comprise:
3rd receiving element, for receiving the second order that described MC sends; Wherein, described second order is used to indicate described storer does not need to write back in described storer with described row address corresponding row with the data of described row address corresponding row described in storing in described buffer zone;
Processing unit, for closing the row corresponding with described row address, and is set to predeterminated voltage by the bit line (bitline) in described storer.
16. storeies according to claim 14, is characterized in that, also comprise:
4th receiving element, for described transmitting element according to described first order traversal all column addresss by described need read data be sent to described MC after, receive described MC send the 3rd order; Wherein, described 3rd order is used to indicate described storer by the zeros data of described and described row address corresponding row;
Reset unit, all reset with the data of described row address corresponding row described in storing in described buffer zone for described 3rd order obtained according to described 4th receiving element;
Write back unit, for writing back in row corresponding with described row address in described storer with the data of described row address corresponding row described in after described clearing unit clearing.
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| CN108694138A (en) * | 2017-04-10 | 2018-10-23 | 爱思开海力士有限公司 | Controller and its operating method |
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| CN112331253A (en) * | 2020-10-30 | 2021-02-05 | 深圳市宏旺微电子有限公司 | Chip testing method, terminal and storage medium |
| CN116719755A (en) * | 2023-08-10 | 2023-09-08 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for multi-application memory access |
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