CN109344093B - Cache structure, and method and device for reading and writing data - Google Patents
Cache structure, and method and device for reading and writing data Download PDFInfo
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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Abstract
The invention provides a cache structure, a method and a device for reading and writing data, wherein the cache structure comprises: the data storage modules comprise a plurality of first data storage blocks, and can perform two times of reading operation or can perform one time of reading operation and one time of writing operation on the plurality of first data storage blocks in one reading and writing clock period, wherein N is an integer greater than or equal to 1; n write channels for receiving data and two read channels for reading data. In one read-write cycle, the cache structure can perform N times of write operation and two times of read operation.
Description
Technical Field
The invention relates to the technical field of network chips, in particular to a cache structure, a method and a device for reading and writing data.
Background
An important function of the network chip is to forward data, and the process is usually as follows: receiving data, caching the data in a cache structure, calculating to obtain a forwarding outlet of the data, reading the data, and forwarding the data through the forwarding outlet.
In practice, the cache structure usually consists of a number of data storage modules, and these storage modules usually consist of a number of data storage blocks, each data storage block can store data of fixed length and has a unique address, and usually within one read-write clock cycle, the data storage module can perform two read operations, or one read operation and one write operation; it can be understood that, in a high-density network chip, multiple read operations and/or write operations may be required in one read-write cycle, and then the existing storage module cannot meet the requirement, that is, a plurality of data storage modules need to be combined to obtain a cache structure, and multiple read operations and/or multiple write operations can be performed on the cache structure in one read-write cycle. In the present application, the invention is directed to obtain a cache structure based on the data storage module, and the cache structure can complete multiple write operations and two read operations in one read-write cycle.
Therefore, how to design a cache structure capable of completing multiple write operations and two read operations in one read/write cycle based on the existing data storage block becomes a problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a cache structure, a method and a device for reading and writing data.
In order to achieve one of the above objects, an embodiment of the present invention provides a cache structure, including: the data storage modules comprise a plurality of first data storage blocks, and can perform two times of reading operation or can perform one time of reading operation and one time of writing operation on the plurality of first data storage blocks in one reading and writing clock period, wherein N is an integer greater than or equal to 1; n write channels for receiving data and two read channels for reading data.
As a further improvement of an embodiment of the present invention, the data storage module further includes: the FIFO buffer module and the address storage module, the address storage module comprises a plurality of second data storage blocks, each second data storage block can store the addresses of two first data storage blocks, and the address storage module can perform two times of reading operations or can perform one time of reading operation and one time of writing operation within one reading and writing clock cycle.
The embodiment of the invention provides a method for reading and writing data, which comprises the following steps:
receiving a read instruction for characterizing reading of at most two data and/or a write instruction for characterizing writing of at most N data;
establishing a one-to-one mapping relation between the N writing channels and N data storage modules in the N +1 data storage modules based on a preset algorithm;
when determining that a first write channel corresponding to any first data storage module in the N data storage modules contains data and two read addresses received from two read channels both correspond to the first data storage module, establishing a mapping relation between the first write channel and the remaining one of the N +1 data storage modules;
and executing read operation and/or write operation on the N +1 data storage modules according to the mapping relation.
As a further improvement of an embodiment of the present invention, the establishing a one-to-one mapping relationship between N write channels and N data storage modules in the N +1 data storage modules based on a preset algorithm includes:
based on a random algorithm, selecting N data storage modules from the N +1 data storage modules, and establishing a one-to-one mapping relation between the N writing channels and the N data storage modules.
As a further improvement of an embodiment of the present invention, the establishing a one-to-one mapping relationship between N write channels and N data storage modules in the N +1 data storage modules based on a preset algorithm includes: establishing a mapping relation between the ith writing channel and the jth data storage module, wherein,
i and k are integers, i is more than or equal to 1 and less than or equal to N, and k is more than or equal to 0 and less than or equal to N;
the establishing a mapping relationship between the first write channel and the remaining one of the N +1 data storage modules includes: establishing a mapping relation between the first writing channel and the Lth data storage module, wherein,
and the FIFO buffer module corresponding to the L-th data storage module is not empty.
As a further improvement of an embodiment of the present invention, the performing a write operation includes:
when determining that the FIFO buffer module in any second data storage module is not full, reading and deleting a plurality of addresses from an address storage module in the second data storage module, and entering the plurality of addresses PUSH into the FIFO buffer module;
an address is output from the FIFO buffer module POP;
and when the write channel corresponding to the second data storage module contains data, writing the data in the write channel corresponding to the second data storage module into the first data storage block corresponding to the address, and returning the address.
As a further improvement of an embodiment of the present invention, the performing the read operation on the N +1 data storage modules includes:
receiving at most two read addresses from two read channels, writing each read address into an address storage module of a data storage module corresponding to the read address, and executing the following operations on each read address: and acquiring a third data storage module corresponding to the read address, and reading data in a first data storage block corresponding to the read address in the third data storage module.
The embodiment of the invention provides a device for reading and writing data, which comprises the following modules:
the command receiving module is used for receiving a read command for representing reading at most two data and/or a write command for representing writing at most N data;
the distribution module is used for establishing a one-to-one mapping relation between the N writing channels and N data storage modules in the N +1 data storage modules based on a preset algorithm;
a conflict resolution module, configured to establish a mapping relationship between a first write channel and a remaining one of the N +1 data storage modules when it is determined that a first write channel corresponding to an arbitrary first data storage module of the N data storage modules contains data and two read addresses received from two read channels both correspond to the first data storage module;
and the read-write operation module is used for executing read operation and/or write operation on the N +1 data storage modules according to the mapping relation.
As a further improvement of an embodiment of the present invention, the allocating module further performs:
based on a random algorithm, selecting N data storage modules from the N +1 data storage modules, and establishing a one-to-one mapping relation between the N writing channels and the N data storage modules.
As a further improvement of an embodiment of the present invention, the allocating module further performs: establishing a mapping relation between the ith writing channel and the jth data storage module, wherein,
i and k are integers, i is more than or equal to 1 and less than or equal to N, and k is more than or equal to 0 and less than or equal to N;
the conflict resolution module further performs: establishing a mapping relation between the first writing channel and the Lth data storage module, wherein,
and the FIFO buffer module corresponding to the L-th data storage module is not empty.
Compared with the prior art, the invention has the technical effects that: the embodiment of the invention provides a cache structure, a method and a device for reading and writing data, wherein the cache structure comprises the following components: the data storage modules comprise a plurality of first data storage blocks, and can perform two times of reading operation or can perform one time of reading operation and one time of writing operation on the plurality of first data storage blocks in one reading and writing clock period, wherein N is an integer greater than or equal to 1; n write channels for receiving data and two read channels for reading data. In one read-write cycle, the cache structure can perform N times of write operation and two times of read operation.
Drawings
FIG. 1 is a schematic diagram of a buffer structure in the present invention;
fig. 2 is a schematic flow chart of a method for reading and writing data of a cache structure according to a second embodiment of the present invention;
FIG. 3 is a diagram illustrating a first mapping relationship between a write channel and a data storage module according to a second embodiment of the present invention;
FIG. 4 is a second mapping relationship diagram between the write channel and the data storage module according to the second embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
The invention provides a cache structure, which can complete N times of writing operation and two times of reading operation in one reading and writing period, and is provided with N writing channels and two reading channels; the writing operation is specifically as follows: writing data into some writing channels, then obtaining the data from the N writing channels by the cache structure, writing the obtained data into one or more data storage modules, and returning an address; the reading operation is specifically as follows: and writing the read address into the read channel, then obtaining the read address from the read channel by the cache module, reading the data in the data storage block corresponding to the read address, and outputting the data.
An embodiment of the present invention provides a cache structure, including: the data storage modules comprise a plurality of first data storage blocks, and can perform two times of reading operation or can perform one time of reading operation and one time of writing operation on the plurality of first data storage blocks in one reading and writing clock period, wherein N is an integer greater than or equal to 1; n write channels for receiving data and two read channels for reading data. Here, "one read operation and one write operation" mean that the data storage module can simultaneously perform one read operation and one write operation in one read-write cycle. The term "two read operations" refers to the data storage module being capable of performing two read operations simultaneously during one read and write cycle. Here, the first data storage blocks exist as an integral module, and 1 read 1 write or 2 read can be performed on the integral module in one read and write cycle.
Preferably, the data storage module further comprises:
the address storage module comprises a plurality of second data storage blocks, each second data storage block can store addresses of two First data storage blocks, and the address storage module can perform two read operations or can perform one read operation and one write operation within one read-write clock cycle. Here, as shown in fig. 1, each data storage module includes a plurality of first data storage blocks, a FIFO buffer module and an address storage module, wherein the address storage module is capable of storing addresses of all the first data storage blocks, and the FIFO buffer module is capable of buffering a plurality of addresses in the address storage module.
An embodiment of the present invention provides a method for reading and writing data, as shown in fig. 2, including the following steps:
step 201: receiving a read instruction for characterizing reading of at most two data and/or a write instruction for characterizing writing of at most N data; here, there is a unified clock signal in the network chip, and the buffer structure is provided with an enable terminal, and if the enable terminal receives the read enable signal and the write enable signal, and the clock signal is a rising edge (e.g., rising edge or falling edge), it indicates that the buffer structure receives a command to read data and/or write data, so that the buffer structure can start reading and writing data. It will be appreciated that if a write data instruction is received, the cache structure will receive a number of data (up to N) to be written; if a read data command is received, the cache structure receives addresses (at most two) of the first data memory blocks.
Step 202: establishing a one-to-one mapping relation between the N writing channels and N data storage modules in the N +1 data storage modules based on a preset algorithm; in this step, N data storage modules are selected from the N +1 data storage modules, and one data storage module (which may be referred to as a spare data storage module) remains.
Step 203: when determining that a first write channel corresponding to any first data storage module in the N data storage modules contains data and two read addresses received from two read channels both correspond to the first data storage module, establishing a mapping relation between the first write channel and the remaining one of the N +1 data storage modules; here, if the first write channel corresponding to the first data storage module contains data, it indicates that the first data storage module needs to perform one write operation in the read-write clock cycle, and if both read addresses correspond to the first data storage module, it indicates that the first data storage module needs to perform two read operations in the read-write clock cycle; in one read-write clock cycle, the first data storage blocks in the first data storage module can only perform two read operations, or one read operation and one write operation, that is, the first data storage module cannot complete the 2-read-1-write operation, that is, there is a read-write conflict. In order to solve the problem, in this step, a mapping relationship is established between the first write channel and the spare data storage module, that is, 2 read operations are performed on the first data storage module, and 1 write operation is performed on the spare data storage module.
Step 204: and executing read operation and/or write operation on the N +1 data storage modules according to the mapping relation. It is understood that, in step 201, if a read instruction is received, in step 204, only "read operation is performed on all of the N +1 data storage modules"; if a write command is received, in step 204, only "write operation is performed on all of the N +1 data storage modules"; if a read command and a write command are received, then in step 204, only "read and write operations are performed on all of the N +1 data storage modules" need to be performed.
It can be understood that, after step 203 is completed, if there is no read-write conflict in each data storage module, the data in the write channel may be written into the corresponding data storage module, the read address is obtained from the read channel, the data in the first data storage block corresponding to the read address is obtained, and then the data is output through the read channel. It can be understood that if a certain write channel does not contain data, the operation of writing data to the data storage module corresponding to the channel is not required; correspondingly, if a certain read channel does not contain a read address, the read channel does not need to be subjected to data reading operation.
Here, it is understood that, in step 204, the probability of writing to the spare data storage module is generally small, and therefore, in order to improve the space utilization of each data storage module, each time step 202 is executed, a different data storage module can be selected as the spare data storage module, i.e., each data storage module is selected as the spare data storage moduleThe probability of the modules being as equal as possible
Preferably, the establishing a one-to-one mapping relationship between the N write channels and N data storage modules of the N +1 data storage modules based on a preset algorithm includes: based on a random algorithm, selecting N data storage modules from the N +1 data storage modules, and establishing a one-to-one mapping relation between the N writing channels and the N data storage modules. Here, each data storage module is provided with
Is selected to finally obtain the N data storage modules, it can be understood that the probability that the data storage module is selected as the spare data storage module is
Optionally, the random algorithm may be: during the first execution of step 202, the h-th data storage module is selected as the spare data storage module, and during the second execution of step 202, the h + 1-th data storage module is selected as the spare data storage module, and then the h +2, h +3, …, N +1, 2, …, h, …, i.e. the N +1 data storage modules are arranged into a circle, and each time step 202 is executed, the next data storage module is selected as the spare data storage module, thereby ensuring that the probability of each data storage module being selected as the spare data storage module is strictly equal to the probability of each data storage module being selected as the spare data storage module
Preferably, the establishing a one-to-one mapping relationship between the N write channels and N data storage modules of the N +1 data storage modules based on a preset algorithm includes: establishing a mapping relation between the ith writing channel and the jth data storage module, wherein,
i and k are integers, i is more than or equal to 1 and less than or equal to N, and k is more than or equal to 0 and less than or equal to N;
the establishing a mapping relationship between the first write channel and the remaining one of the N +1 data storage modules includes: establishing a mapping relation between the first writing channel and the Lth data storage module, wherein,
and the FIFO buffer module corresponding to the L-th data storage module is not empty.
Here, when N is 5 and k is 2, the mapping relationship between the channels and the data storage modules is as shown in fig. 3, that is, the write channel No. 1 corresponds to the data storage module No. 3, the write channel No. 2 corresponds to the data storage module No. 4, the write channel No. 3 corresponds to the data storage module No. 5, the write channel No. 4 corresponds to the data storage module No. 6, the write channel No. 5 corresponds to the data storage module No. 1, and the data storage module No. 2 is the spare data storage module; when N is 5 and k is 0, the mapping relationship between the channels and the data storage modules is as shown in fig. 4, that is, the write channel No. 1 corresponds to the data storage module No. 1, the write channel No. 2 corresponds to the data storage module No. 2, the write channel No. 3 corresponds to the data storage module No. 3, the write channel No. 4 corresponds to the data storage module No. 4, the write channel No. 5 corresponds to the data storage module No. 5, and the data storage module No. 6 is the spare data storage module.
Optionally, when step 202 is executed N +1 times, the value of k is different, so that when step 202 is executed N +1 times, the spare data storage modules selected each time are different, and thus each data storage module has equal chance to become a spare data storage module. For example, the value of k may be, in order, h +1, h +2, …, N, 0, 1, 2, …, h +1, …, i.e., the N +1 data storage modules are arranged in a circle, and each time step 202 is performed, the next data storage module is selected as the spare data storage module, thereby ensuring that the probability that each data storage module is selected as the spare data storage module is exactly equal to
Preferably, the performing a write operation includes: when determining that the FIFO buffer module in any second data storage module is not full, reading and deleting a plurality of addresses from an address storage module in the second data storage module, and entering the plurality of addresses PUSH into the FIFO buffer module; here, if the FIFO buffer block is not full, some addresses in the address storage block may be read out and PUSH into the FIFO buffer block. Here, since the address storage block supports only 1 read 1 write or 2 read in one read and write cycle, the number of "several addresses" can be controlled according to actual situations, for example, data in one second data storage block is read from the address storage block each time; it is understood that, if the second data storage block read stores two addresses, after the data is read from the second data storage block, the data needs to be split into two addresses.
An address is output from the FIFO buffer module POP;
and when the write channel corresponding to the second data storage module contains data, writing the data in the write channel corresponding to the second data storage module into the first data storage block corresponding to the address, and returning the address. As shown in fig. 1, each data storage module corresponds to a unique FIFO buffer module and a unique address storage module, for example, in fig. 1, a data storage module 1 corresponds to a FIFO buffer module 1 and an address storage module 1, a data storage module 2 corresponds to a FIFO buffer module 2 and an address storage module 2, …, and a data storage module N +1 corresponds to a FIFO buffer module N +1 and an address storage module N + 1. It is understood that the addresses of all data storage blocks in the data storage module can be stored in the corresponding address storage module.
Here, if data is to be read from the cache structure, a read address needs to be provided, and it is understood that after writing a data, the address of the first data block to which the data is written needs to be returned for a subsequent read operation.
Here, after the initialization of the address storage block is completed, the read address is 0, and the write address is the maximum depth of the address storage block. In the read operation, the read address is added with 1, and in the write operation, the write address is added with 1. And re-accumulation to zero if added to the maximum depth of the address storage module. It will be appreciated that the address storage module is also a FIFO.
Optionally, the executing the write operation further includes: and when the write channel corresponding to the second data storage module does not contain data, the address PUSH is put into a FIFO buffer module of the second data storage module. If no data is contained, the write operation is not required, and the address PUSH can be entered into the FIFO buffer module for the next read and use.
Optionally, the executing the write operation further includes: and if the write channel corresponding to the second data storage module contains data and the second data storage module is full of data, the write operation fails.
Preferably, the executing performs a read operation on the N +1 data storage modules, including: receiving at most two read addresses from two read channels, writing each read address into an address storage module of a data storage module corresponding to the read address, and executing the following operations on each read address: and acquiring a third data storage module corresponding to the read address, and reading data in a first data storage block corresponding to the read address in the third data storage module. Here, the first data memory block of the third data memory module corresponding to the read address is obtained, and then the data is read from the first memory area and output.
Optionally, the writing each read address into an address storage module in the data storage module corresponding to the read address includes: and when the two read addresses are determined to correspond to the same fourth address storage module, combining the two read addresses into one piece of data and storing the data into the address storage module in the fourth address storage module. Here, the address storage block does not support two write operations in the same read and write cycle, and the second data storage block can store addresses of two first data storage blocks, and thus, two read addresses can be combined into one piece of data and then the data can be stored in the first data storage block.
In summary, the cache structure in the present invention includes N +1 data storage modules, and all the data storage modules can be used for storing data, that is, the utilization rate is high, and the N-write 2-read capability is supported.
The embodiment of the invention also provides a device for reading and writing data, which comprises the following modules:
the command receiving module is used for receiving a read command for representing reading at most two data and/or a write command for representing writing at most N data;
the distribution module is used for establishing a one-to-one mapping relation between the N writing channels and N data storage modules in the N +1 data storage modules based on a preset algorithm;
a conflict resolution module, configured to establish a mapping relationship between a first write channel and a remaining one of the N +1 data storage modules when it is determined that a first write channel corresponding to an arbitrary first data storage module of the N data storage modules contains data and two read addresses received from two read channels both correspond to the first data storage module;
and the read-write operation module is used for executing read operation and/or write operation on the N +1 data storage modules according to the mapping relation.
Preferably, the allocation module further performs: based on a random algorithm, selecting N data storage modules from the N +1 data storage modules, and establishing a one-to-one mapping relation between the N writing channels and the N data storage modules.
Preferably, the allocation module further performs: establishing a mapping relation between the ith writing channel and the jth data storage module, wherein,
i and k are integers, i is more than or equal to 1 and less than or equal to N, and k is more than or equal to 0 and less than or equal to N;
the conflict resolution module further performs: establishing a first write channel and an Lth write channelA mapping relationship of the data storage modules, wherein,
and the FIFO buffer module corresponding to the L-th data storage module is not empty.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (9)
1. A cache structure, comprising:
the data storage modules comprise a plurality of first data storage blocks, and can perform two times of reading operation or can perform one time of reading operation and one time of writing operation on the plurality of first data storage blocks in one reading and writing clock period, wherein N is an integer greater than or equal to 1;
n write channels for receiving data and two read channels for reading data;
the data storage module further comprises:
the FIFO buffer module and the address storage module, the address storage module comprises a plurality of second data storage blocks, each second data storage block can store the addresses of two first data storage blocks, and the address storage module can perform two times of reading operations or can perform one time of reading operation and one time of writing operation within one reading and writing clock cycle.
2. A method for reading and writing data, comprising the steps of:
receiving a read instruction for characterizing reading of at most two data and/or a write instruction for characterizing writing of at most N data;
establishing a one-to-one mapping relation between the N writing channels and N data storage modules in the N +1 data storage modules based on a preset algorithm;
when determining that a first write channel corresponding to any first data storage module in the N data storage modules contains data and two read addresses received from two read channels both correspond to the first data storage module, establishing a mapping relation between the first write channel and the remaining one of the N +1 data storage modules;
and executing read operation and/or write operation on the N +1 data storage modules according to the mapping relation.
3. The method according to claim 2, wherein the establishing a one-to-one mapping relationship between the N write channels and N data storage modules of the N +1 data storage modules based on a preset algorithm includes:
based on a random algorithm, selecting N data storage modules from the N +1 data storage modules, and establishing a one-to-one mapping relation between the N writing channels and the N data storage modules.
4. A method of reading and writing data according to claim 2, wherein:
the establishing of a one-to-one mapping relationship between the N write channels and the N data storage modules in the N +1 data storage modules based on a preset algorithm includes: establishing a mapping relation between the ith writing channel and the jth data storage module, wherein,
i and k are integers, i is more than or equal to 1 and less than or equal to N, and k is more than or equal to 0 and less than or equal to N;
said establishing a first write channel with saidThe mapping relationship of the remaining one of the N +1 data storage modules includes: establishing a mapping relation between the first writing channel and the Lth data storage module, wherein,
and the FIFO buffer module corresponding to the L-th data storage module is not empty.
5. The method of claim 2, wherein the performing a write operation comprises:
when determining that the FIFO buffer module in any second data storage module is not full, reading and deleting a plurality of addresses from an address storage module in the second data storage module, and entering the plurality of addresses PUSH into the FIFO buffer module;
an address is output from the FIFO buffer module POP;
and when the write channel corresponding to the second data storage module contains data, writing the data in the write channel corresponding to the second data storage module into the first data storage block corresponding to the address, and returning the address.
6. The method of claim 2, wherein said performing a read operation on said N +1 data storage modules comprises:
receiving at most two read addresses from two read channels, writing each read address into an address storage module of a data storage module corresponding to the read address, and executing the following operations on each read address: and acquiring a third data storage module corresponding to the read address, and reading data in a first data storage block corresponding to the read address in the third data storage module.
7. An apparatus for reading and writing data, comprising:
the command receiving module is used for receiving a read command for representing reading at most two data and/or a write command for representing writing at most N data;
the distribution module is used for establishing a one-to-one mapping relation between the N writing channels and N data storage modules in the N +1 data storage modules based on a preset algorithm;
a conflict resolution module, configured to establish a mapping relationship between a first write channel and a remaining one of the N +1 data storage modules when it is determined that a first write channel corresponding to an arbitrary first data storage module of the N data storage modules contains data and two read addresses received from two read channels both correspond to the first data storage module;
and the read-write operation module is used for executing read operation and/or write operation on the N +1 data storage modules according to the mapping relation.
8. The apparatus for reading from and writing to data according to claim 7, wherein the assigning module further performs:
based on a random algorithm, selecting N data storage modules from the N +1 data storage modules, and establishing a one-to-one mapping relation between the N writing channels and the N data storage modules.
9. An apparatus for reading from and writing to data according to claim 7, wherein:
the allocation module further performs: establishing a mapping relation between the ith writing channel and the jth data storage module, wherein,
i and k are integers, i is more than or equal to 1 and less than or equal to N, and k is more than or equal to 0 and less than or equal to N;
the conflict resolution module further performs: establishing a mapping relation between the first writing channel and the Lth data storage module, wherein,
and the FIFO buffer module corresponding to the L-th data storage module is not empty.
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