CN115080455A - Computer chip, computer board card, and storage space distribution method and device - Google Patents
Computer chip, computer board card, and storage space distribution method and device Download PDFInfo
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- CN115080455A CN115080455A CN202211003294.4A CN202211003294A CN115080455A CN 115080455 A CN115080455 A CN 115080455A CN 202211003294 A CN202211003294 A CN 202211003294A CN 115080455 A CN115080455 A CN 115080455A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
Abstract
The application discloses a computer chip, a computer board card, a storage space distribution method and a device, relates to the technical field of computers, the technical field of chips and the technical field of multi-party safety calculation, and comprises the following steps: the system comprises a read-write address management module and a plurality of chip control modules, wherein the chip control modules are connected with a memory; the memory is divided into a plurality of memory cell blocks, and the memory space of the memory cell blocks is not less than the maximum single task data length; the read-write address management module allocates a storage unit block in an idle state for a computing task to be executed based on a unit block state lookup table, acquires a storage space address of the storage unit block based on a unit block address mapping table, and changes the state of the storage unit block into an occupied state in the unit block state lookup table; and the chip control module reads and writes data related to the calculation task according to the storage space address. The method and the device realize the purpose of avoiding generating storage fragments for data storage in a multi-core parallel data processing mechanism.
Description
Technical Field
The present application relates to the field of computer technologies, chip technologies, and multi-party secure computing technologies, and in particular, to a computer chip, a computer board, and a storage space allocation method and apparatus.
Background
In the practical application of computer technology, a computer board card is generally used. Taking a typical board card system composed of a CPU and a computer chip as an example, each board card may have an FPGA (Programmable Array logic) chip as a control chip and a plurality of dedicated computing chips to form a typical multi-core computing system. In the system, a special computing chip has the capability of high-speed concurrent processing tasks and can be used for executing computing tasks of multi-party secure computation and privacy computation, for example, a special encryption chip can simultaneously process modular multiplication and modular exponentiation at high speed. Data required by these computing tasks usually uses a large-capacity Dynamic Memory, such as a DRAM (Dynamic Random Access Memory) as a physical medium for data caching, so as to ensure that a computing chip can obtain enough input data at any time, and meanwhile, there is enough space for storing computing results output by the computing chip.
In such a multi-core parallel system, the task types and data volumes of the computing tasks received by each computing chip may be different, and since the computing chips perform parallel computing on the computing tasks, the starting and ending times of the computing tasks processed by the computing chips are different. Thus, the time at which the space used to buffer the input and output data is released is also different.
In the existing data communication, a ring buffer (ring buffer) is generally used as a data structure for storing data transmitted and received in the communication. A ring buffer is an end-to-end ring used for buffering (buffering) task data in data communication. The circular buffer typically has one read pointer and one write pointer (one in pointer and one out pointer). The read pointer points to data readable in the ring buffer and the write pointer points to a writable buffer in the ring buffer. Data reading and writing of the buffer can be achieved by moving the read and write pointers.
Compared with a linked list queue access speed, the data storage management mode adopting the ring buffer has the advantages that the access speed is high, the data are stored in the buffer until new data cover the data, and therefore, the time for garbage collection is not needed, and the method is one of the most common data management modes in data communication at present.
However, since the ring buffer is a first-in first-out circular buffer, which requires that the task that is cached first should be released first, in the multi-core parallel data processing mechanism, many memory fragments may occur, and some fragments may not even store the input data of one task, so the conventional ring buffer scheme is not suitable for the multi-core parallel system.
Disclosure of Invention
The embodiment of the application provides a computer chip, a computer board card, a storage space distribution method and a storage space distribution device, which are used for solving the problem that a plurality of storage fragments are generated by adopting a ring buffer in a multi-core parallel data processing mechanism in the prior art.
An embodiment of the present application provides a computer chip, including: the system comprises a read-write address management module and a plurality of chip control modules, wherein the chip control modules are connected with a memory;
the storage space of the memory is divided into a plurality of storage unit blocks, the storage space of the storage unit blocks is not smaller than the maximum single task data length, and the maximum single task data length is the maximum value of the single task data lengths of various computing tasks to be executed;
the plurality of chip control modules are respectively connected with the plurality of computing chips in a one-to-one correspondence manner;
the read-write address management module is used for allocating a storage cell block in an idle state for a calculation task to be executed based on a cell block state lookup table, acquiring a storage space address of the allocated storage cell block based on a cell block address mapping table, and changing the state of the storage cell block into an occupied state in the cell block state lookup table;
and the chip control module is used for reading and writing data related to the calculation task aiming at the calculation task executed by the connected calculation chip according to the storage space address of the storage unit block allocated to the calculation task.
Further, the read-write address management module is further configured to, for a computation task that has been executed, change the state of a memory cell block allocated to the computation task into an idle state in the cell block state lookup table.
Furthermore, the sizes of the memory spaces of the plurality of memory cell blocks are the same, and the memory space address of the memory cell block in the cell block address mapping table is the memory space first address.
Further, the number of the plurality of memory cell blocks is greater than the number of the plurality of computing chips.
The embodiment of the present application further provides a computer board card, including: any one of the computer chips described above, the memory, and the plurality of computing chips.
The embodiment of the present application further provides a storage space allocation method, which is applied to a computer chip, where the computer chip is connected to a memory, the storage space of the memory is divided into a plurality of memory cell blocks, the storage space of the memory cell blocks is not less than a maximum single task data length, the maximum single task data length is a maximum value of single task data lengths of various computing tasks to be executed, the computer chip is connected to a plurality of computing chips, and the computing chips are used for executing the computing tasks, and the method includes:
for a calculation task to be executed, distributing a storage cell block in an idle state for the calculation task based on a cell block state lookup table;
based on the unit block address mapping table, obtaining a memory space address of the allocated memory unit block, wherein the memory space address is used for storing data related to the computing task;
the state of the memory cell block is changed to an occupied state in the cell block state look-up table.
Further, the method also comprises the following steps:
for a completed executed computing task, changing the state of a memory cell block allocated for the computing task to an idle state in the cell block state lookup table.
Further, the memory spaces of the plurality of memory cell blocks are the same in size, and the memory space address of the memory cell block in the cell block address mapping table is the memory space head address.
Further, the number of the plurality of memory cell blocks is greater than the number of the plurality of computing chips.
The embodiment of the present application further provides a memory space allocation device, which is applied to a computer chip, the computer chip is connected to a memory, the memory space of the memory is divided into a plurality of memory cell blocks, the memory space of the memory cell blocks is not less than the maximum single task data length, the maximum single task data length is the maximum value of the single task data lengths of various computing tasks to be executed, the computer chip is connected to a plurality of computing chips, the computing chips are used for executing the computing tasks, the device includes:
the state query module is used for distributing a storage cell block in an idle state for the calculation task based on the cell block state lookup table aiming at the calculation task to be executed;
the address acquisition module is used for acquiring the allocated memory space address of the memory cell block based on the cell block address mapping table, wherein the memory space address is used for storing data related to the calculation task;
and the state updating module is used for changing the state of the memory cell block into an occupied state in the cell block state lookup table.
Further, the state updating module is further configured to, for a executed computation task, change the state of a memory cell block allocated for the computation task into an idle state in the cell block state lookup table.
Furthermore, the sizes of the memory spaces of the plurality of memory cell blocks are the same, and the memory space address of the memory cell block in the cell block address mapping table is the memory space first address.
Further, the number of the plurality of memory cell blocks is greater than the number of the plurality of computing chips.
Embodiments of the present application further provide an electronic device, including a processor and a machine-readable storage medium storing machine-executable instructions executable by the processor, the processor being caused by the machine-executable instructions to: implementing any of the above memory space allocation methods.
An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the computer program implements any of the above-mentioned storage space allocation methods.
Embodiments of the present application further provide a computer program product containing instructions, which when run on a computer, cause the computer to perform any of the above-mentioned memory space allocation methods.
The beneficial effect of this application includes:
the computer chip provided by the embodiment of the application comprises a read-write address management module and a plurality of chip control modules, wherein the chip control modules are connected with a memory; the storage space of the memory is divided into a plurality of storage unit blocks, the storage space of the storage unit blocks is not smaller than the maximum single task data length, and the maximum single task data length is the maximum value of the single task data lengths of various computing tasks to be executed; the plurality of chip control modules are respectively connected with the plurality of computing chips in a one-to-one correspondence manner; the read-write address management module is used for allocating a storage cell block in an idle state for a calculation task to be executed based on a cell block state lookup table, acquiring a storage space address of the allocated storage cell block based on a cell block address mapping table, and changing the state of the storage cell block into an occupied state in the cell block state lookup table; and the chip control module is used for reading and writing data related to the calculation task aiming at the calculation task executed by the connected calculation chip according to the storage space address of the storage unit block allocated to the calculation task. The computer chip is connected with a plurality of computing chips, the computing chips can execute computing tasks in parallel, and a multi-core parallel data processing mechanism is formed.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
fig. 1 is a schematic structural diagram of a computer chip provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of a computer chip according to another embodiment of the present application;
fig. 3 is a flowchart of a storage space allocation method according to an embodiment of the present application;
fig. 4 is a flowchart of a method for allocating memory space according to another embodiment of the present application;
fig. 5 is a schematic structural diagram of a storage space allocation apparatus according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to provide an implementation scheme for avoiding memory fragmentation for data storage in a multi-core parallel data processing mechanism, embodiments of the present application provide a computer chip, a computer board, a memory space allocation method, and a device. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
An embodiment of the present application provides a computer chip, as shown in fig. 1, including: the system comprises a read-write address management module and a plurality of chip control modules, wherein the chip control modules are connected with a memory;
the storage space of the memory is divided into a plurality of storage unit blocks, the storage space of the storage unit blocks is not smaller than the maximum single task data length, and the maximum single task data length is the maximum value of the single task data lengths of various computing tasks to be executed;
the plurality of chip control modules are respectively connected with the plurality of computing chips in a one-to-one correspondence manner;
the read-write address management module is used for allocating a storage cell block in an idle state for a calculation task to be executed based on a cell block state lookup table, acquiring a storage space address of the allocated storage cell block based on a cell block address mapping table, and changing the state of the storage cell block into an occupied state in the cell block state lookup table;
and the chip control module is used for reading and writing data related to the calculation task aiming at the calculation task executed by the connected calculation chip according to the storage space address of the storage unit block allocated to the calculation task.
The computer chip is connected with a plurality of computing chips which can execute computing tasks in parallel, and a multi-core parallel data processing mechanism is formed.
In the embodiment of the present application, when reading and writing data related to a computation task for the computation task, the chip control module may specifically read task input data of the computation task from a memory space address of the allocated memory cell block, and store computation result data obtained by the computation task executed by the connected computation chip into the memory space address.
The read-write address management module and the chip control module can be realized by hardware circuit logic or virtual modules.
In the embodiment of the application, the current state of each memory cell block is stored in the cell block state lookup table, and is in an idle state or an occupied state, and may also be described as a clean page (clean) indicating an idle state and a dirty page (dirty) indicating an occupied state; the unit block address mapping table stores the storage space address of each storage unit block in the memory.
In the embodiment of the present application, the read-write address management module may be further configured to, for a executed computation task, change a state of a memory cell block allocated to the computation task into an idle state in a cell block state lookup table, so as to facilitate subsequent allocation of a memory space for a new computation task.
In an embodiment of the present application, the sizes of the storage spaces of the plurality of storage unit blocks may be the same, and correspondingly, the storage space address of the storage unit block in the unit block address mapping table may be the first address of the storage space, that is, the use of data reading and writing for the storage unit block may be implemented in combination with the fixed-size storage space of the storage unit block.
In one embodiment of the present application, the number of the plurality of memory cell blocks may be greater than the number of the plurality of computing chips, so as to improve the efficiency of the plurality of computing chips in executing the computing task in parallel. Further, the number of the plurality of memory cell blocks may be more than 2 times the number of the plurality of computing chips, so as to further improve performance.
In the embodiment of the application, the read-write address management module can acquire the single task data length of each computing task to be executed by each computing chip from the upper computer to which the read-write address management module belongs, select the maximum value as the maximum single task data length, and also can directly acquire the maximum single task data length from the upper computer, and divide the storage space of the memory into a plurality of storage unit blocks based on the maximum single task data length, and create the unit block state lookup table and the unit block address mapping table based on the divided plurality of storage unit blocks.
In this embodiment of the present application, for a computation task, the read-write address management module may allocate two memory cell blocks in an idle state to the computation task, where one memory cell block is used to store task input data, and another memory cell block is used to store a computation result.
In an embodiment of the present application, as shown in fig. 2, the computer chip may further include an interconnection module, the interconnection module is respectively connected to the memory and the plurality of chip control modules, and the plurality of chip control modules can complete data reading and writing for the memory through the interconnection module.
The interconnection module can also be regarded as a memory controller, and is used for realizing control and transmission operations such as protocol conversion and the like in the data transmission process between the plurality of chip control modules and the memory.
In the using process of the computer chip, the upper computer to which the computer chip belongs can issue the computing task to the computer chip through the PCIe interface of the computer chip, other modules (such as a task receiving module in fig. 2) of the computer chip distribute the new computing task to a certain computing chip for execution, a read-write address management module distributes a storage cell block for the new computing task, and the upper computer stores the task input data of the new computing task into the storage cell block, or the upper computer stores the task input data of the new computing task into the storage cell block through the task receiving module, the read-write address management module can inform the storage space address of the storage cell block distributed for the new computing task to a chip control module connected with the computing chip distributed for the new computing task, and the chip control module realizes the transmission of the task input data and the calculation result of the calculation task through the information interaction with the calculation chip, the calculation result is also stored in the storage unit block, and the upper computer reads the calculation result from the storage unit block through a PCIe interface, or the upper computer reads the calculation result from the storage unit block through the task receiving module.
In an embodiment of the present application, the computer chip may be a programmable chip, such as an FPGA chip, and the memory may be a DRAM.
Based on the computer chip provided by the embodiment of the present application, the embodiment of the present application further provides a computer board, as shown in fig. 1 and fig. 2, including any one of the computer chips, a memory, and a plurality of computer chips.
In fig. 1 and 2, n computing chips, namely, computing chip 0 to computing chip n-1, are included.
Based on the computer chip provided by the embodiment of the present application, an embodiment of the present application further provides a storage space allocation method, which is applied to a computer chip, the computer chip is connected to a memory, the storage space of the memory is divided into a plurality of memory cell blocks, the storage space of the memory cell block is not smaller than a maximum single task data length, the maximum single task data length is a maximum value of single task data lengths of various computing tasks to be executed, the computer chip is connected to a plurality of computing chips, and the computing chips are used for executing the computing tasks, as shown in fig. 3, the method includes:
step 33 changes the state of the memory cell block to an occupied state in a cell block state look-up table.
By adopting the storage space allocation method, aiming at a multi-core parallel data processing mechanism consisting of a computer chip and a plurality of computing chips, because the storage space of a memory is divided into a plurality of storage unit blocks, and the storage space of each storage unit block is not smaller than the maximum single task data length, when the computing chips execute computing tasks in parallel, compared with a ring buffer, the requirement that the tasks which are cached and entered firstly are released is not needed any more, each computing chip can occupy the storage unit blocks in an idle state at any time based on the task execution condition and release the storage unit blocks, and the storage unit blocks in the idle state can be effectively used by the computing chips no matter where the storage unit blocks are located in the memory, and no storage fragments can be generated.
The method and apparatus provided by the present application are described in detail below with reference to the accompanying drawings using specific embodiments.
An embodiment of the present application provides a storage space allocation method, which is applied to any one of the computer chips described above, as shown in fig. 4, and includes:
and step 41, aiming at the calculation task to be executed, distributing the storage cell block in the idle state for the calculation task based on the cell block state lookup table.
In this step, the computing task to be executed may be sent to the computer chip through a PCIe interface, where the computer chip belongs to the upper computer.
Specifically, the upper computer may send a computing task to be executed to a task receiving module of the computer chip through the PCIe interface, where the task receiving module allocates a task ID to the computing task and sends the task ID to the read-write address management module.
The read-write address management module inquires a unit block state lookup table aiming at the new calculation task, searches out a storage unit block in an idle state from the unit block, and distributes the storage unit block for the calculation task from the storage unit block in the idle state.
In particular, two memory cell blocks may be allocated, wherein one memory cell block is used for storing task input data and the other memory cell block is used for storing calculation results.
In the embodiment of the present application, the cell block state lookup table may be as shown in table 1 below:
table 1: cell block state lookup table
The memory cell block includes n memory cell blocks, and each memory cell block records a current state, is in an idle state or an occupied state, and may also be described as a clean page (clean) indicating an idle state and a dirty page (dirty) indicating an occupied state.
And step 42, acquiring the memory space address of the memory cell block which is allocated based on the cell block address mapping table, wherein the memory space address is used for storing data related to the calculation task.
In this step, the read-write address management module searches a unit block address mapping table for a memory unit block allocated to the new calculation task, where the unit block address mapping table stores a memory space address of each memory unit block in the memory, and obtains the allocated memory space address of the memory unit block.
In the embodiment of the present application, the unit block address mapping table may be as shown in table 2 below:
table 2: unit block address mapping table
Wherein n memory cell blocks are included, a memory space address is recorded corresponding to each memory cell block, and when the size of the memory space of each memory cell block is the same, the memory space address may be a head address.
And step 44, the read-write address management module sends the acquired storage space address of the storage unit block to an upper computer or a task receiving module and a chip control module connected with a computing chip responsible for executing the new computing task.
And step 45, after receiving the storage space address of the storage unit block, the upper computer or the task receiving module stores the task input data of the new calculation task into the storage unit block according to the storage space address.
And step 47, the chip control module sends the acquired task input data to a connected computing chip, and the computing chip executes the computing task based on the received task input data to obtain a computing result and sends the computing result to the connected chip control module.
And step 48, the chip control module stores the received calculation result of the calculation task into the storage unit block according to the storage space address of the storage unit block, so that the upper computer can obtain the calculation result, or the task receiving module can obtain the calculation result and forwards the calculation result to the upper computer.
And informs the read-write address management module that the calculation task is completed.
Or the upper computer or the task receiving module informs the read-write address management module that the calculation task is executed after obtaining the calculation result.
In the above memory space allocation method, for the read-write address management module, when a new computation task and a completed computation task arrive at the same time, only one path of the cell block state lookup table can be operated at any time through one lock module based on a lock mechanism.
Based on the same inventive concept, according to the memory space allocation method provided in the above embodiment of the present application, correspondingly, another embodiment of the present application further provides a memory space allocation apparatus applied to a computer chip, where the computer chip is connected to a memory, the memory space of the memory is divided into a plurality of memory cell blocks, the memory space of the memory cell blocks is not less than a maximum single task data length, the maximum single task data length is a maximum value of single task data lengths of various computing tasks to be executed, the computer chip is connected to a plurality of computing chips, the computing chips are used for executing the computing tasks, and a schematic structural diagram thereof is shown in fig. 5, and specifically includes:
a state query module 51, configured to, for a computation task to be executed, allocate a memory cell block in an idle state to the computation task based on a cell block state lookup table;
an address obtaining module 52, configured to obtain, based on the unit block address mapping table, a memory space address of the allocated memory unit block, where the memory space address is used for storing data related to the calculation task;
a state updating module 53, configured to change the state of the memory cell block to an occupied state in the cell block state lookup table.
Further, the state updating module 53 is further configured to, for a executed computing task, change the state of the memory cell block allocated for the computing task to an idle state in the cell block state lookup table.
Furthermore, the sizes of the memory spaces of the plurality of memory cell blocks are the same, and the memory space address of the memory cell block in the cell block address mapping table is the memory space first address.
Further, the number of the plurality of memory cell blocks is greater than the number of the plurality of computing chips.
The functions of the above modules may correspond to the corresponding processing steps in the flows shown in fig. 3 or fig. 4, and are not described herein again.
The storage space allocation device provided by the embodiment of the application can be realized by a computer program. It should be understood by those skilled in the art that the above-mentioned module division is only one of many module division, and if the module is divided into other modules or not, it is within the scope of the present application as long as the storage space allocation apparatus has the above-mentioned functions.
An electronic device is further provided in an embodiment of the present application, as shown in fig. 6, and includes a processor 61 and a machine-readable storage medium 62, where the machine-readable storage medium 62 stores machine-executable instructions that can be executed by the processor 61, and the processor 61 is caused by the machine-executable instructions to: and realizing any storage space distribution method.
An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the computer program implements any of the above-mentioned storage space allocation methods.
Embodiments of the present application further provide a computer program product containing instructions, which when run on a computer, cause the computer to perform any of the above-mentioned memory space allocation methods.
The machine-readable storage medium in the electronic device may include a Random Access Memory (RAM) and a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus, the electronic device, the computer-readable storage medium, and the computer program product embodiment, since they are substantially similar to the method embodiment, the description is relatively simple, and in the relevant places, reference may be made to the partial description of the method embodiment.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (12)
1. A computer chip, comprising: the device comprises a read-write address management module and a plurality of chip control modules, wherein the chip control modules are connected with a memory;
the storage space of the memory is divided into a plurality of storage unit blocks, the storage space of the storage unit blocks is not smaller than the maximum single task data length, and the maximum single task data length is the maximum value of the single task data lengths of various computing tasks to be executed;
the plurality of chip control modules are respectively connected with the plurality of computing chips in a one-to-one correspondence manner;
the read-write address management module is used for allocating a storage cell block in an idle state for a calculation task to be executed based on a cell block state lookup table, acquiring a storage space address of the allocated storage cell block based on a cell block address mapping table, and changing the state of the storage cell block into an occupied state in the cell block state lookup table;
and the chip control module is used for reading and writing data related to the calculation task aiming at the calculation task executed by the connected calculation chip according to the storage space address of the storage unit block allocated to the calculation task.
2. The computer chip of claim 1, wherein the read-write address management module is further configured to change, for a completed computing task, a state of a block of memory cells allocated for the computing task to an idle state in the cell block state lookup table.
3. The computer chip of claim 1, wherein the memory spaces of the plurality of memory cell blocks are the same size, and the memory space address of a memory cell block in the cell block address mapping table is a memory space head address.
4. The computer chip of claim 1, wherein a number of the plurality of blocks of memory cells is greater than a number of the plurality of compute chips.
5. A computer board card, comprising: the computer chip of any of claims 1-4, the memory, and the plurality of computing chips.
6. A method for allocating memory space, wherein the method is applied to a computer chip, the computer chip is connected to a memory, the memory space of the memory is divided into a plurality of memory cell blocks, the memory space of the memory cell blocks is not less than a maximum single task data length, the maximum single task data length is a maximum value of the single task data lengths of various computing tasks to be executed, the computer chip is connected to a plurality of computing chips, the computing chips are used for executing the computing tasks, the method comprises:
for a calculation task to be executed, distributing a storage cell block in an idle state for the calculation task based on a cell block state lookup table;
based on the unit block address mapping table, obtaining a memory space address of the allocated memory unit block, wherein the memory space address is used for storing data related to the computing task;
the state of the memory cell block is changed to an occupied state in the cell block state look-up table.
7. The method of claim 6, further comprising:
for a completed executed computing task, changing the state of a memory cell block allocated for the computing task to an idle state in the cell block state lookup table.
8. The method of claim 6, wherein the memory spaces of the plurality of memory cell blocks are the same size, and the memory space address of the memory cell block in the cell block address mapping table is a memory space head address.
9. The method of claim 6, wherein a number of the plurality of blocks of memory cells is greater than a number of the plurality of compute chips.
10. A memory space allocation apparatus applied to a computer chip, wherein the computer chip is connected to a memory, the memory space of the memory is divided into a plurality of memory cell blocks, the memory space of the memory cell blocks is not less than a maximum single task data length, the maximum single task data length is a maximum value of single task data lengths of various computing tasks to be performed, the computer chip is connected to a plurality of computing chips, and the computing chips are used for performing the computing tasks, the apparatus comprising:
the state query module is used for distributing a storage cell block in an idle state for the calculation task based on the cell block state lookup table aiming at the calculation task to be executed;
the address acquisition module is used for acquiring the allocated memory space address of the memory cell block based on the cell block address mapping table, wherein the memory space address is used for storing data related to the calculation task;
and the state updating module is used for changing the state of the memory cell block into an occupied state in the cell block state lookup table.
11. An electronic device comprising a processor and a machine-readable storage medium storing machine-executable instructions executable by the processor, the processor being caused by the machine-executable instructions to: carrying out the method of any one of claims 6 to 9.
12. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method of any one of claims 6 to 9.
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