CN100590609C - Method for managing dynamic internal memory base on discontinuous page - Google Patents
Method for managing dynamic internal memory base on discontinuous page Download PDFInfo
- Publication number
- CN100590609C CN100590609C CN200810059862A CN200810059862A CN100590609C CN 100590609 C CN100590609 C CN 100590609C CN 200810059862 A CN200810059862 A CN 200810059862A CN 200810059862 A CN200810059862 A CN 200810059862A CN 100590609 C CN100590609 C CN 100590609C
- Authority
- CN
- China
- Prior art keywords
- memory
- page
- data
- management unit
- memory management
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention relates to a dynamic memory management method. The prior memory management method influences the utilization rate and the real-time performance of the memory. The dynamic memory management method of the invention comprises the following steps of memory allocation, memory recycle and address mapping, and has the details that a memory unit is divided into memory pages with the same size, and data which are logically connected are allowed to be stored in the memory pages which are not physically connected. The invention adopts the way of combining a counter and FIFO to manage the memory pages, so as to enable the memory allocation and the memory recycle to be more flexible, and the external fragment problem during the memory allocation is eliminated, thereby the utilization rateof the memory is improved, and the allocation and the recycle of the memory have the characteristics of real-time performance and predictability.
Description
Technical field
The invention belongs to the integrated circuit (IC) design field, the method for Memory Allocation, storage and management in the network service chip that real-time requires is particularly arranged, specifically is a kind of dynamic memory management method based on discontinuous page.
Background technology
According to the different mode of data access, managing internal memory has many diverse ways usually.When the order that deposits in take out of data is identical, manage with buffering (Buffer) structure that is similar to first in first out (FIFO) usually, for example forwarding queue is exactly to manage with multi-form Buffer in the switch.When the taking-up of data order with deposit order in not simultaneously, a slice free cells (Hole) then might appear in complete memory storage unit, be dispersed in small pieces free cells in the storage allocation if can not correctly handle these, will greatly influence the utilization factor of internal memory.
The Dram method that software is realized adopts the mode of continuous dispensing more, with the memory block of two doubly linked list structure management free time.Along with constantly carrying out of Memory Allocation, recovery, idle chained list will increase gradually, for search time of finding a suitable memory block from this idle chained list also increases accordingly, and should the time relevant, so can't satisfy the requirement of real-time with the memory block size of request.And, the memory allocation method that this software is realized, in order to reduce fragment problems, the function of cutting apart (splitting) and merging (coalescing) that all adds internal memory, but the introducing of these methods also has influence on the time determinacy (Time-BoundedService) of memory management to a certain extent.
Summary of the invention
Purpose of the present invention overcomes the deficiencies in the prior art exactly, and a kind of dynamic memory management method based on discontinuous page is provided.
Dynamic memory management method of the present invention is according to the feature of data stream in the applied environment internal storage location to be divided into the identical page of size, these pages are minimum units of Memory Allocation, also be the least unit of memory management, this EMS memory management process comprises that specifically Memory Allocation, internal memory reclaim and map addresses.Wherein:
The method of Memory Allocation is based in the discrete physically page or leaf of data storage that allows to link to each other in logic, and concrete steps comprise:
1, when the host requests Memory Allocation, the memory size of surplus resources of the more current internal memory of memory management unit (comprising free page total amount and Data Labels symbol DataID) and host requests, if the free page total amount is greater than the page total amount of host requests, and still have available Data Labels symbol in the memory management unit, then continue Memory Allocation, otherwise finish Memory Allocation.The information that continues Memory Allocation and end Memory Allocation returns to main frame behind a system clock, for host query.If the continuation Memory Allocation, memory management unit will be used the method for " first zero detects " to find an available identifier, and this identifier is distributed to this part data from the binary vector of storage DataID information.
2, the Memory Allocation unit enters substantive allocated phase, and memory management unit is closed new Memory Allocation request responding.Simultaneously, memory management unit is read the page number of available page or leaf from idle page table administrative unit, and is written in the data page table administrative unit according to the number of pages of request.Available page or leaf in the idle page table is decided by the value in the allocation model register from counter or fifo queue (FIFO).When the value in this register was 1, idle page table administrative unit obtained the page number of available page or leaf from counter; When the value in this register is 0, from fifo queue, obtain the page number of available page or leaf.
If 3 all pages of distributing to main frame all move on to the data page table from idle page table transfer, then this Memory Allocation is finished, and memory management unit reenters the state that receives the Memory Allocation request, waits for request next time; Do not move on to the data page table from idle page table transfer fully if distribute to all pages of main frame, then forward 2 to, proceed page and shift.
The method concrete steps that internal memory reclaims comprise:
1, when the host requests Memory Allocation, the surplus resources of the more current internal memory of memory management unit and the memory size of host requests, if the free page total amount is greater than the page total amount of host requests, and still have available Data Labels symbol in the memory management unit, then memory management unit starts the count-down device corresponding with this request, the timing initial value is T0, and the timing step-length is 1 second, and the time reference of timing is imported by the outside.
If 2 certain requests are being become internal memory of the distribution of work, and when the timer timing corresponding with this time request arrived zero, the shared memory source of data still was not recovered, and then changes 4; If before the timer countdown was to zero, main frame did not re-use the data in this page, can write the instruction of reclaiming internal memory to memory management unit, require memory management unit to reclaim shared page and the data identifier resource of this part data.Need point out to require the Data Labels symbol (DataID) of the data correspondence that reclaims in the instruction.In this process, memory management unit stops count-down device and it is reset to T0.
3, receive main frame when sending the instruction of " the recovery internal memory " that show when the internal register of memory management unit, all corresponding pages of Data Labels symbol in the instruction are read from the data page table successively, and be written in the idle page table, change 5 then.Wherein read identical with the total amount of the shared page of the corresponding data of the number of times that writes and this Data Labels symbol.
4, when the count-down device timing arrives zero, the data shared memory source corresponding with this timer still is not recovered, then when data page table and idle page table are all idle, the page of overtime data occupancy is read successively from the data page table and write in the idle page table, simultaneously after all pages reclaim, the corresponding binary vector position of Data Labels symbol of this data occupancy is resetted again, i.e. data collection identifier (DataID) resource.
5, internal memory reclaims and finishes.
Map addresses is transformed into the actual address that can visit physical memory with the logical address of user capture, and in applied environment of the present invention, the data in the internal memory write continuously and read.At such data stream feature, the method step of map addresses comprises:
1, when main frame needs access memory, writes the instruction of a request read-write earlier to memory management unit.Wherein, when the main frame rdma read, when sending read request, indicate the pairing data identifier of the data that need read; And when main frame need be write internal memory, only need to send write request, and the pairing identifier of data is managed automatically by memory management unit, and this identifier is distributed by the Memory Allocation unit when the host requests Memory Allocation.
2, memory management unit is receiving main frame when needing the instruction of access memory, data identifier with institute's visit data correspondence is the base address, skew is zero, be combined into a new address, the page number of the first page of data storage in the reading of data page table, and this page number deposited in " current page number " register.Wherein, during address combination, with the high p position of data identifier as the address, and the low d position of address is complete zero.P is defined as w-d, and wherein w is the width of address wire in the internal memory, and d is the page or leaf bias internal of logical address, and correspondingly, the size of each sheet page is 2
dByte (Byte).
3, when main frame begins access memory, the low d position of the logical address of memory management unit intercepting main frame current accessed, as the low d position of physical address, and be the high p position of address with the value in " current page number " register, be combined as can access memory physical address.If the logical address of host access is not last byte in one page, then change 4; If the logical address of host access is last byte in one page, memory management unit is in same system cycle, the high p position of the logical address of intercepting main frame current accessed, the data of this p position are added 1 (being designated as p1) and are combined into a new address with the data identifier of current accessed data, with the page number in this address reading data page table management unit, and when next system cycle, the page number that will obtain from the data page table is updated in " current page table " register.
4, if the host access internal memory finishes, then in memory management unit, write the instruction of " finishing visit ", memory management unit " current page table " register that resets, and wait for the request of access next time of main frame; If main frame also needs access memory, then change 3, continue the process of internal storage access.
Related operation among the present invention (as the reading and writing internal memory etc.) be basic fundamental general knowledge, adopt the routine techniques means.Inventive point of the present invention is to provide a kind of comparatively advanced memory management flow process.
The present invention with discrete page as the unit that distributes substantially and reclaim, the data storage that allows in logic to link to each other is in discrete page or leaf.This mode has improved the flexibility ratio of Memory Allocation, and correspondingly, the external fragmentation of internal memory is eliminated, and the utilization factor of internal memory is improved.
Description of drawings
Fig. 1 application system structural drawing of the present invention;
The structural drawing of Fig. 2 Memory Allocation function of the present invention;
The process flow diagram of Fig. 3 Memory Allocation function of the present invention;
The sequential of Fig. 4 Memory Allocation process of the present invention;
Memory Allocation example as a result in Fig. 5 system of the present invention operational process;
Fig. 6 logical address is to the mapping of physical address.
Embodiment
Canonical system applied environment of the present invention as shown in Figure 1, wherein memory management unit is an an example of the present invention.The present invention has three big major functions: one, and storage allocation, updating memory recorded information; Two, reclaim internal memory and updating memory recorded information; Three, map addresses.Below in conjunction with the embodiment of in the summary of the invention description of three major function flow processs further being introduced each function.
The structural drawing of Memory Allocation function as shown in Figure 2, the Memory Allocation flow process is as shown in Figure 3.Wherein, the free page resource is managed with the mode that counter and FIFO combine.In the starting stage of distribution, adopt counter to distribute free page, the page or leaf of giving back will deposit among the FIFO, manage free page by FIFO after all pages or leaves are all transferred among the FIFO.The duty of idle page table administrative unit is decided by " allocation model control " register.The initialized process of idle page table has been eliminated in the introducing of counter.Counter also has another effect, robustness for memory management unit in the practical application is considered, when memory management unit occurs when unusual, idle page table administrative unit does not have valid data in distinguishing internal memory after, to come back to original state and (can judge whether there are data in the internal memory according to the binary vector of preserving data identifier, when this vector is complete zero the time, there are not valid data in the expression internal memory).At this moment, need only reset counter, and the free page allocation model is reset to original state.Whole process can be finished in single clock cycle, can not influence the operate as normal of total system.
In the Memory Allocation process, from idle page table, read the available internal memory page or leaf, these pages are written in the data page table by state controller.The data page table is the SRAM structure, and reads and writes as the base address of visit with DataID.After the page of data correspondence all shifts, distribute and finish.Sequential chart when page shifts as shown in Figure 4, wherein RdEn is the enable signal that reads the free memory page information among the FIFO, and UpdateCEn is used for the value of refresh counter, and is ready for shift page next time; WrDataStoreList writes enable signal for the data page table; Whether TransFinish is used to control the page transfer finishes; FreePages is the page number of free memory page or leaf.
It is corresponding with it that each partial data all has a unique ID (DataID) in the internal memory.DataID represents (bitmap) with a scale-of-two array, and each represents a DataID, and the value of DataID is obtained by the position decoding of its corresponding position in bitmap.Memory Allocation not only will be distributed available page or leaf, also will distribute available DataID simultaneously, and DataID obtains by " first null detector " algorithm.The input of first null detector is the bitmap of DataID correspondence, is output as the first available position of DataID in bitmap.The bit wide of DataID can be adjusted according to using, and as representing DataID as employing 4bit, available DataID total amount is 2 in the then expression system
4Individual.
The present invention supports two kinds of internal memory ways of recycling: explicit and implicit expression.Two kinds of internal memory ways of recycling all need visit data page table and idle page table, the collision problem in the time of therefore must handling both well and visit public resource.The explicit recovery of internal memory is initiatively proposed by main frame, before the count-down device timing of data correspondence is overflowed, main frame sends the command request memory management unit and reclaims the shared memory source of this partial data, need comprise the DataID of the data correspondence that will reclaim in the instruction; And the recovery of the implicit expression of internal memory is finished automatically by memory management unit, does not need main frame to participate in.When the Memory Allocation unit is data when becoming internal memory of the distribution of work, will start a count-down device corresponding with this blocks of data, timing be spaced apart 1 second, the initial value T0 of timing can be disposed by the user, T0 got 4 seconds in an embodiment of the present invention.When the count-down device timing arrives zero, memory management unit is outside tasks such as Memory Allocation and the explicit recovery of internal memory, insert the task of a low priority, when data page table and idle page table are all idle, the memory source of the overtime data correspondence mode with implicit expression is reclaimed, from the data page table, read successively and write in the idle page table comprising the page that overtime data block is taken, simultaneously after all pages reclaim, the corresponding binary vector position of Data Labels symbol that this blocks of data is taken resets again, i.e. the data collection identifier resource.Internal memory implicit expression reclaims this function and controls the conversion of its state by the state machine of a special use, avoids the collision problem in data page table and the free page table access process.
In the applied environment of the present invention, data are read-writes continuously, when main frame needs access memory, write the instruction of a request read-write earlier to memory management unit.Wherein, when the main frame rdma read, when sending read request, indicate the pairing data identifier of the data that need read; And when main frame need be write internal memory, only need to send write request, and the pairing identifier of data is managed automatically by memory management unit, and this identifier is distributed by the Memory Allocation unit when the host requests Memory Allocation.The data identifier that uses in the read-write process is designated as ID.Memory management unit is receiving main frame when needing the instruction of access memory, data identifier with institute's visit data correspondence is the base address, skew is zero, be combined into a new address, the page number of the first page of data storage in the reading of data page table, and this page number deposited in " current page number " register.Wherein, the mode of address combination as shown in Figure 6.When main frame begins access memory, the low d position of the logical address of memory management unit intercepting main frame current accessed, as the low d position of physical address, and be the high p position of address with the value CP in " current page number " register, be combined as can access memory physical address.Simultaneously, when the logical address of host access is last byte in one page, memory management unit is in same system cycle, the high p position of the logical address of intercepting main frame current accessed, the data of this p position are added 1 (being designated as p1) and are combined into a new address with the data identifier of current accessed data, with the page number in this address reading data page table management unit, and when next system cycle, the page number that will obtain from the data page table is updated in " current page table " register.Wherein p is defined as w-d, and w is the width of address wire in the internal memory, and d is the page or leaf bias internal of logical address, and correspondingly, the size of each sheet page is 2
dByte (Byte).The mode of address combination as shown in Figure 6.
When main frame is finished visit to a certain blocks of data, need in memory management unit, write the instruction of " finishing visit ", the memory management unit register that this visit is used that resets, and wait for the request of access next time of main frame.
The checking result of the present invention in system as shown in Figure 5, wherein horizontal ordinate is a system time, free memory number of pages purpose real-time change among ordinate (left side) reflection the present invention, and the real-time change of data available ID (DataID) number among ordinate (right side) reflection the present invention.
Claims (1)
1, a kind of dynamic memory management method based on discontinuous page comprises that Memory Allocation, internal memory reclaim and map addresses, is characterized in that:
The method of Memory Allocation is based in the discrete physically page or leaf of data storage that allows to link to each other in logic, and concrete steps comprise:
A, as data during to the host requests Memory Allocation, the surplus resources of the more current internal memory of memory management unit and the memory size of host requests, if the free page total amount is greater than the page total amount of host requests, and still have available Data Labels symbol in the memory management unit, then continue Memory Allocation, otherwise finish Memory Allocation; If continuation Memory Allocation, memory management unit will be from the DataID information be found an available identifier with first zero method that detects, and this identifier distributed to data to the host requests Memory Allocation; Described DataID information is the unique sign of each partial data in the internal memory, represents with binary vector; The method that described head zero detects with the bitmap of DataID correspondence as input, with the first available position of DataID in bitmap as output; The surplus resources of described current internal memory comprises free page total amount and Data Labels symbol;
B, memory management unit are closed new Memory Allocation request responding, and memory management unit is read the page number of available page or leaf from idle page table administrative unit, and is written in the data page table administrative unit according to the number of pages of request; Available page or leaf in the idle page table is decided by the value in the allocation model register from counter or fifo queue, and when the value in this register was 1, idle page table administrative unit obtained the page number of available page or leaf from counter; When the value in this register is 0, from fifo queue, obtain the page number of available page or leaf;
If c distributes to all pages of main frame and all moves on to the data page table from idle page table transfer, then this Memory Allocation is finished, and memory management unit reenters the state that receives the Memory Allocation request, waits for request next time; Do not move on to the data page table from idle page table transfer fully if distribute to all pages of main frame, forward step b to, proceed page and shift;
The method concrete steps that internal memory reclaims comprise:
D, when the host requests Memory Allocation, the surplus resources of the more current internal memory of memory management unit and the memory size of host requests, if the free page total amount is greater than the page total amount of host requests, and still have available Data Labels symbol in the memory management unit, then memory management unit starts the count-down device corresponding with this request, the timing initial value is T0, and the timing step-length is 1 second, and the time reference of timing is imported by the outside;
If the data that are stored in page during e asks with this are when the count-down device timing arrives zero, the data in the page still are not recovered, and then change step g; If with the data that are stored in page in this request before the count-down device timing is to zero, main frame does not re-use the data in this page, write the instruction of explicit recovery internal memory to the internal register of memory management unit, stop count-down device simultaneously and it is reset to T0;
F, when the internal register of memory management unit receives the instruction of explicit recovery internal memory, all pages that Data Labels symbol is corresponding in the instruction are read from the data page table successively, and are written in the idle page table, change step h then; Read identical with the total amount of the shared page of the number of times that writes and this Data Labels symbol;
G, with this request in be stored in page data in the count-down device timing to zero the time, under the situation that data in the page still are not recovered, if when data page table and idle page table are all idle, the page of overtime data occupancy is read successively from the data page table and write in the idle page table, simultaneously after all pages reclaim, the corresponding binary vector position of Data Labels symbol of this data occupancy is resetted again, i.e. data collection identifier resource;
H, internal memory reclaim and finish;
The method concrete steps of map addresses comprise:
I, when main frame needs access memory, write earlier the instruction of a request read-write to memory management unit, wherein, when the main frame rdma read, when sending read request, indicate the pairing data identifier of the data that need read; And when main frame need be write internal memory, only need to send write request, and the pairing identifier of data is managed automatically by memory management unit, and this identifier is distributed by the Memory Allocation unit when the host requests Memory Allocation;
J, memory management unit are receiving main frame when needing the instruction of access memory, data identifier with institute's visit data correspondence is the base address, skew is zero, be combined into a new address, the page number of the first page of data storage in the reading of data page table, and this page number deposited in " current page number " register;
K, when main frame begins access memory, the low d position of the logical address of memory management unit intercepting main frame current accessed, low d position as physical address, and be the high p position of address with the value in " current page number " register, be combined as can access memory physical address, if the logical address of host access is not last byte in one page, then change step m; If the logical address of host access is last byte in one page, memory management unit is in same system cycle, the high p position of the logical address of intercepting main frame current accessed, the data of this p position are added 1 and be combined into a new address with the data identifier of current accessed data, with the page number in this address reading data page table management unit, and when next system cycle, the page number that will obtain from the data page table is updated in " current page table " register; Wherein p is w-d, and w is the width of address wire in the internal memory, and d is the page or leaf bias internal of logical address;
M, if the host access internal memory finishes, then in memory management unit, write the instruction of " finishing visit ", memory management unit " current page table " register that resets, and wait for the request of access next time of main frame; If main frame also needs access memory, then change step k, continue the process of internal storage access.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200810059862A CN100590609C (en) | 2008-02-22 | 2008-02-22 | Method for managing dynamic internal memory base on discontinuous page |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN200810059862A CN100590609C (en) | 2008-02-22 | 2008-02-22 | Method for managing dynamic internal memory base on discontinuous page |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101231619A CN101231619A (en) | 2008-07-30 |
CN100590609C true CN100590609C (en) | 2010-02-17 |
Family
ID=39898112
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200810059862A Expired - Fee Related CN100590609C (en) | 2008-02-22 | 2008-02-22 | Method for managing dynamic internal memory base on discontinuous page |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100590609C (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101667105B (en) * | 2009-09-02 | 2011-12-28 | 龙芯中科技术有限公司 | Dispatching device and method for dynamically reading, writing, accessing and grouping dynamic memories |
CN101901191A (en) * | 2010-05-31 | 2010-12-01 | 深圳市茁壮网络股份有限公司 | Method and device for managing multiclass memories of embedded system |
CN102023821A (en) * | 2010-12-16 | 2011-04-20 | 成都市华为赛门铁克科技有限公司 | Disc space management method and system |
CN102123198A (en) * | 2011-01-11 | 2011-07-13 | 中国联合网络通信集团有限公司 | Memory management method and memory manager for media player |
CN104011645B (en) * | 2011-12-22 | 2018-06-26 | 英特尔公司 | For generating integer phase difference constant integer span wherein in continuous position and smallest positive integral is from the processor of the integer sequence of zero offset integer shifts, method, system and medium containing instruction |
US9753860B2 (en) * | 2012-06-14 | 2017-09-05 | International Business Machines Corporation | Page table entry consolidation |
CN104008061B (en) * | 2013-02-22 | 2018-01-23 | 华为技术有限公司 | Method for recovering internal storage and device |
WO2015061970A1 (en) * | 2013-10-29 | 2015-05-07 | 华为技术有限公司 | Method and device for accessing internal memory |
CN103593300B (en) * | 2013-11-15 | 2017-05-03 | 浪潮电子信息产业股份有限公司 | Memory allocating and collecting method |
CN104090848B (en) * | 2014-07-16 | 2017-03-08 | 云南大学 | EMS memory management process and device that a kind of periodicity big data is processed |
KR102501751B1 (en) * | 2015-09-22 | 2023-02-20 | 삼성전자주식회사 | Memory Controller, Non-volatile Memory System and Operating Method thereof |
CN107291556B (en) * | 2017-08-01 | 2021-01-22 | 上海联影医疗科技股份有限公司 | Medical equipment, memory allocation method and device thereof and storage medium |
CN107704199A (en) * | 2017-09-07 | 2018-02-16 | 郑州云海信息技术有限公司 | A kind of logical partition method and device of solid state hard disc |
CN107864391B (en) * | 2017-09-19 | 2020-03-13 | 北京小鸟科技股份有限公司 | Video stream cache distribution method and device |
CN107908428B (en) * | 2017-11-24 | 2021-09-14 | 中国航空工业集团公司西安航空计算技术研究所 | Frame and page synchronous GPU (graphics processing Unit) graphics instruction buffer synchronization method |
CN109992522A (en) * | 2017-12-29 | 2019-07-09 | 广东欧珀移动通信有限公司 | Application processing method and device, electronic equipment, computer readable storage medium |
CN108804032B (en) * | 2018-05-16 | 2021-05-18 | 山东华芯半导体有限公司 | Self-adaptive wear-balanced garbage recovery accelerating device and method |
CN108717395B (en) * | 2018-05-18 | 2021-07-13 | 记忆科技(深圳)有限公司 | Method and device for reducing memory occupied by dynamic block mapping information |
CN109284234B (en) * | 2018-09-05 | 2020-12-04 | 珠海昇生微电子有限责任公司 | Storage address allocation method and system |
CN110688330B (en) * | 2019-09-23 | 2021-08-31 | 北京航空航天大学 | Virtual memory address translation method based on memory mapping adjacency |
CN110727606A (en) * | 2019-09-27 | 2020-01-24 | Oppo(重庆)智能科技有限公司 | Memory recovery method and device and electronic equipment |
CN110928682B (en) * | 2019-11-13 | 2023-06-09 | 深圳国微芯科技有限公司 | Method for accessing computer memory by external device |
CN111813710B (en) * | 2020-09-11 | 2021-02-05 | 鹏城实验室 | Method and device for avoiding Linux kernel memory fragmentation and computer storage medium |
CN114201444B (en) * | 2021-12-06 | 2023-11-14 | 海飞科(南京)信息技术有限公司 | Method, medium, program product, system, and apparatus for storage management |
WO2024044986A1 (en) * | 2022-08-30 | 2024-03-07 | 晶晨半导体(上海)股份有限公司 | Memory management method and module, chip, electronic device, and storage medium |
-
2008
- 2008-02-22 CN CN200810059862A patent/CN100590609C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101231619A (en) | 2008-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100590609C (en) | Method for managing dynamic internal memory base on discontinuous page | |
CN110113420B (en) | NVM-based distributed message queue management system | |
CN101241446B (en) | Command scheduling method and apparatus of virtual file system embodied in nonvolatile data storage device | |
CN104765575B (en) | information storage processing method | |
CN105373484A (en) | Memory distribution, storage and management method in network communication chip | |
CN109388590B (en) | Dynamic cache block management method and device for improving multichannel DMA (direct memory access) access performance | |
CN102063406B (en) | Network shared Cache for multi-core processor and directory control method thereof | |
CN102339283A (en) | Access control method for cluster file system and cluster node | |
CN107256196A (en) | The caching system and method for support zero-copy based on flash array | |
CN101267361A (en) | A high-speed network data packet capturing method based on zero duplication technology | |
CN112632069B (en) | Hash table data storage management method, device, medium and electronic equipment | |
KR20180025128A (en) | Stream identifier based storage system for managing array of ssds | |
US9569381B2 (en) | Scheduler for memory | |
CN104765574A (en) | Data cloud storage method | |
CN102541757A (en) | Write cache method, cache synchronization method and device | |
CN115080455B (en) | Computer chip, computer board card, and storage space distribution method and device | |
US20220197533A1 (en) | Moving Data in a Memory and Command for Memory Control | |
CN101625703A (en) | Method and system for merging logs of memory database | |
CN101706760B (en) | Matrix transposition automatic control circuit system and matrix transposition method | |
CN103154892A (en) | Method, system and apparatus for multi-level processing | |
EP3494493A1 (en) | Repartitioning data in a distributed computing system | |
CN111651396B (en) | Optimized PCIE (peripheral component interface express) complete packet out-of-order management circuit implementation method | |
CN103617123A (en) | Method and system for memory management by memory block | |
CN101610197A (en) | A kind of buffer management method and system thereof | |
CN111694765A (en) | Mobile application feature-oriented multi-granularity space management method for nonvolatile memory file system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100217 Termination date: 20130222 |