WO2015061970A1

WO2015061970A1 - Method and device for accessing internal memory

Info

Publication number: WO2015061970A1
Application number: PCT/CN2013/086167
Authority: WO
Inventors: 姚传群; 王俊杰; 彭伟林
Original assignee: 华为技术有限公司
Priority date: 2013-10-29
Filing date: 2013-10-29
Publication date: 2015-05-07
Also published as: CN104169891B; CN104169891A

Abstract

The embodiment of the present invention discloses a method and device for accessing internal memory, relating to the field of computing, and effectively increases the security of internal memory. Said method comprises: a data access request from a first device requesting access to a first memory area is obtained, said data access request comprising the physical memory address of the data the first device requests to access, said first memory area being the dedicated physical memory area corresponding to the first device; on the basis of the physical memory address of the data the first device requests to access, the physical memory address information of an I/O virtualisation controller device is queried, said physical memory address information comprising the physical memory address corresponding to the physical memory address of the first memory area; and, if it is determined that the physical memory address of the data the first device requests to access is within the physical memory address information of the I/O virtualisation controller device, then the first memory area is accessed.

Description

Method and device for accessing memory

The present invention relates to the field of computers, and in particular, to a method and device for accessing a memory. Background technique

In the physical memory of the computer system, there is not only system memory for storing the computer operating system, but also dedicated functional memory for storing data when the computer implements a specific function. The dedicated functional memory and the system memory are distributed without isolation. In the memory, for example, in the central processing unit (CPU), the Field-Programmable Gate Array (FPGA) implements the packet forwarding system, the physical memory A memory is allocated for forwarding memory (dedicated functional memory) for storing message queues (Queues), data buffers (Buffers), message pointers, forwarding memory, and system memory without isolation in physical memory. And the FPGA realizes the interaction of the data cache location through the message queue, and then obtains the corresponding data through the obtained message queue content.

The inventors have found that the prior art has at least the following drawbacks: Since there is no isolation and protection between the dedicated functional memory and the system memory, once the address of the dedicated functional memory is accessed, it is possible to step on the system memory, which is easy to cause the system. Reset or hang to cause an accident; With the increasing use of computer systems, the functions that computers can implement will also increase, and the amount of access to physical memory will be greatly increased, thus increasing the system memory. The possibility of accidental stepping reduces the security of the system memory. Summary of the invention

Embodiments of the present invention provide a method and device for accessing a memory, which effectively improves the security of the system memory.

In order to achieve the above object, embodiments of the present invention use the following technical solutions:

In a first aspect, a method of accessing memory is provided, including

Obtaining a data access request of the first device requesting access to the first memory area, where The data access request includes a physical memory address of the data that the first device requests to access; the first memory area is a dedicated physical memory area corresponding to the first device;

Querying physical memory address information in the input/output I/O virtualization controller device according to the physical memory address of the data requested by the first device; wherein the physical memory address information includes the first memory region The physical memory address corresponding to the physical memory address;

If the physical memory address of the data requested by the first device is determined to be

In the physical memory address information in the I/O virtualization controller device, the first memory area is accessed.

With reference to the first aspect, in a first possible implementation manner of the first aspect, before the acquiring, by the first device, the data access request for accessing the first memory area, the method further includes:

Mapping a physical memory address of the first memory area to the I/O virtualization controller device to form the physical memory address information;

Mapping a physical memory address of the first memory area to the first device. With reference to the first aspect or the first possible implementation manner of the first aspect, in the second possible implementation manner of the first aspect, the I/O virtualization controller device includes at least one physical memory address information a physical memory address information base, wherein each physical memory address information corresponds to a different memory area; correspondingly, the physical memory address of the data requested by the first device is queried I/0 virtualization control Physical memory address information in the device, including:

And the physical memory address information database is obtained by the first device, and the physical memory address information corresponding to the memory area corresponding to the first device is obtained.

Querying according to a physical memory address of the data requested by the first device to access

The physical memory address information corresponding to the first memory area in the I/O virtualization controller device.

In conjunction with the first aspect or the first possible implementation of the first aspect or the second possible implementation of the first aspect, in a third possible implementation of the first aspect, The method also includes

If it is determined that the physical memory address of the data requested by the first device is not in the

The data access request is discarded in the physical memory address information in the I/O virtualization controller device.

In conjunction with the third possible implementation of the first aspect, in a fourth possible implementation manner of the first aspect, the method further includes

In the physical memory address information in the I/O virtualization controller device, abnormal information is recorded. The second aspect provides a device for accessing a memory, including,

An acquiring unit, configured to acquire a data access request that the first device requests to access the first memory area, where the data access request includes a physical memory address of the data that the first device requests to access; the first memory area is a dedicated physical memory area i corresponding to a device;

a query unit, configured to query physical memory address information in the I/O virtualization controller device according to a physical memory address of the data requested by the first device acquired by the acquiring unit, where the physical memory address information includes a physical memory address corresponding to a physical memory address of the first memory area;

And an access unit, configured to access the first memory area if the physical unit address of the data requested by the first device to be accessed by the query unit is in the physical memory address information in the I/O virtualization controller device.

With reference to the second aspect, in a first possible implementation manner of the second aspect, the device further includes

a mapping unit, configured to map a physical memory address of the first memory area to the I/O virtualization controller before the obtaining unit acquires a data access request of the first device requesting access to the first memory area Forming, by the device, the physical memory address information;

The mapping unit is further configured to map a physical memory address of the first memory area to the first device. With reference to the second aspect, or the first possible implementation manner of the second aspect, in the second possible implementation manner of the second aspect, the I/O virtualization controller device includes at least one physical memory address information a physical memory address information base, where each physical memory address information corresponds to a different memory area; correspondingly, the query unit is specifically used,

With reference to the second aspect, or the first possible implementation manner of the second aspect, or the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect,

a discarding unit, configured to: if the query unit determines that a physical memory address of data requested by the first device is not in physical memory address information in the I/O virtualization controller device, the data access request is throw away.

In conjunction with the third possible implementation of the second aspect, in a fourth possible implementation of the second aspect, the device further includes

And a recording unit, configured to: if the query unit determines that the physical memory address of the data requested by the first device is not in the physical memory address information in the I/O virtualization controller device, the abnormal information is recorded. The third aspect provides a device for accessing a memory, including,

a processor, configured to acquire a data access request of the first device requesting access to the first memory area, where the data access request includes a physical memory address of data requested by the first device; the first memory area is a dedicated physical memory area corresponding to a device;

An I/O virtualization controller device for requesting access to data according to the first device The physical memory address is queried for the physical memory address information in the I/O virtualization controller device; wherein the physical memory address information includes a physical memory address corresponding to the physical memory address of the first memory region;

a first device, configured to: if the I/O virtualization controller device determines that a physical memory address of the data requested by the first device is in the physical memory address information in the I/O virtualization controller device, The first memory area.

With reference to the third aspect, in a first possible implementation manner of the third aspect, the processor is specifically configured to: before the acquiring, by the first device, a data access request for accessing the first memory area, A physical memory address of a memory area is mapped to the

Forming the physical memory address information in the I/O virtualization controller device;

The processor is further configured to map a physical memory address of the first memory area to the first device.

With reference to the third aspect, or the first possible implementation manner of the third aspect, in a second possible implementation manner of the third aspect, the I/O virtualization controller device includes at least one physical memory address information a physical memory address information base, wherein each physical memory address information corresponds to a different memory area; correspondingly, the I/O virtualization controller device is further used,

With reference to the third aspect, or the first possible implementation manner of the third aspect, or the second possible implementation manner of the third aspect, in a third possible implementation manner of the third aspect, the I/O virtualization The controller device is also used,

The data access request is discarded in the physical memory address information in the I/O virtualization controller device. In conjunction with the third possible implementation of the third aspect, in a fourth possible implementation manner of the third aspect, the I/O virtualization controller device is further configured to:

In the physical memory address information in the I/O virtualization controller device, abnormal information is recorded. In a fourth aspect, a physical machine is provided, including: a device for accessing a memory and a physical memory, where the device for accessing the memory includes a first device and an I/O virtualization controller device;

The device for accessing the memory is used,

Obtaining a data access request that the first device requests access to the first memory area, where the data access request includes a physical memory address of the data that the first device requests to access; the first memory area is dedicated to the first device Physical memory area;

Querying physical memory address information in the I/O virtualization controller device according to the physical memory address of the data requested by the first device; wherein the physical memory address information includes a physical memory address of the first memory region Corresponding physical memory address;

With reference to the fourth aspect, in a first possible implementation manner of the fourth aspect, the device for accessing a memory is further configured to: before the acquiring, by the first device, a data access request for accessing the first memory area, The physical memory address of the first memory area is mapped to the I/O virtualization controller device to form the physical memory address information; the device for accessing the memory is further configured to: physics of the first memory area The memory address is mapped into the first device.

With reference to the fourth aspect, or the first possible implementation manner of the fourth aspect, in a second possible implementation manner of the fourth aspect, the I/O virtualization controller device includes at least one physical memory address information a physical memory address information base, wherein each physical memory address information corresponds to a different memory area; correspondingly, The device for accessing the memory is specifically used,

Obtaining physical memory address information of the memory area corresponding to the first device, by querying the physical memory address information database by requesting the data access request of the first device to access the first memory area;

With reference to the fourth aspect, or the first possible implementation manner of the fourth aspect, or the second possible implementation manner of the fourth aspect, in a third possible implementation manner of the fourth aspect, Used for

A method and device for accessing a memory provided by an embodiment of the present invention, by acquiring a data access request of a first device requesting access to a first memory area, where the data access request includes a physicality of data requested by the first device a memory address; the first memory area is a dedicated physical memory area corresponding to the first device; and the physical memory address information in the I/O virtualization controller device is queried according to the physical memory address of the data requested by the first device; The physical memory address information includes the physical memory address of the data accessed by the first standby request in the physical memory address information in the I/O virtualization controller device, and then accesses the first memory region. Effectively improve the security of system memory. DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is some embodiments of the present invention, and it can be used by those skilled in the art without creative efforts. Other figures are obtained from these figures.

FIG. 1 is a schematic flowchart of a method for accessing a memory according to an embodiment of the present invention; FIG. 2 is a schematic diagram of an internal structure of a physical memory according to an embodiment of the present invention; Schematic diagram of a message pointer and a message queue;

FIG. 3 is a schematic diagram of a scenario of a C P U and an F P G A packet forwarding system according to an embodiment of the present disclosure;

4 is a schematic flow chart of another method for accessing a memory according to an embodiment of the present invention;

FIG. 5 is a schematic flow chart of still another method for accessing a memory according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a scenario in which a plurality of devices access a memory according to an embodiment of the present invention; FIG. 7 is a schematic flowchart of another method for accessing a memory according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an apparatus for accessing a memory device according to an embodiment of the present invention; FIG.

FIG. 9 is a schematic structural diagram of another apparatus for accessing a memory according to an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of another apparatus for accessing a memory according to an embodiment of the present invention;

FIG. 1 is a schematic structural diagram of a device of a physical machine according to an embodiment of the present invention; FIG. 1B is a schematic structural diagram of another device of a physical machine according to an embodiment of the present invention. detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without departing from the inventive scope are the scope of the present invention. Embodiment 1

Embodiment 1 of the present invention provides a method for accessing a memory. Referring to FIG. 1, the method may include:

And obtaining, by the first device, a data access request for accessing the first memory area, where the data access request includes a physical memory address of the data that the first device requests to access; the first memory area is the first The dedicated physical memory area corresponding to the device; wherein, the first device is a device that implements a specific function by accessing the physical memory of the computer, for example, in the CPU of the X 8 6 system and the FPGA packet forwarding system, the first device is an FPGA; or The first device may be a peripheral of the virtual machine in the virtualization platform; the present invention does not specifically limit the type of the first device;

The first memory area is a dedicated physical memory area in which the first device allocated in the physical memory implements the corresponding function. For example, referring to FIG. 2A, the first memory area is included in the physical memory, and the first memory area includes at least a data cache. a message queue and a message pointer; wherein, the data cache is used to store data accessed by the first device in implementing the corresponding function, and the data may be stored in the data cache in the form of a data packet;

The message queue may be a circular queue, and the message queue includes data information arranged in a queue form, and each data information is used to store related information of corresponding data in the data cache, for example, may include a location where the data is stored in the data cache. The physical memory address and the data feature, for example, the data feature may include the type, the size, the length, and the like of the data. The specific content of the data feature included in the data information may be set as needed, and the present invention is not specifically limited;

The depth of the message queue refers to the capacity that the message queue can use to store data information. Each message queue can be a depth-determined and limited circular queue, and the depth of the message queue can be smaller than the capacity of the data cache;

It should be noted that when the depth of the message queue is smaller than the capacity of the data cache, the data information corresponding to each data stored in the data cache may be stored in the message queue, and some of the data information will wait for the message queue to have a free location. Regenerate and store; The message pointer is used to indicate the location of the data information in the message queue. The message pointer is divided into a head pointer and a tail pointer. For example, the head pointer can be used to indicate the last non-idle position in the message queue, and the tail pointer can be used to indicate the number in the message queue. An idle location, so that the location of the data in the message queue and the free location can be clearly indicated by the indication of the message pointer; when the first device reads the data information from the message queue, it can be based on the reference address of the message queue. Adding the actual physical memory address where the data information is stored by adding the message queue position indicated by the message pointer head pointer;

When it is necessary to store data information in the message queue, firstly, according to the message pointer, it is judged whether the message queue is full. If it is full, it waits for the empty position; if it is not full, the data information to be stored is stored in the tail pointer of the message pointer. Indicates the first idle location, and then updates the message pointer to the tail pointer of the message pointer + 1 , that is, keeps the tail pointer of the message pointer indicating the first idle position in the message queue;

Wherein, according to the message pointer to determine whether the message queue is full, generally the message queue (message queue depth - 1) position does not store the data information is empty, can use the judgment of the tail pointer position of the message pointer + 1 is equal to the head pointer Position judgment, if it is equal, it determines that the message queue is full, if not equal, it determines that the message queue is not full; of course, because the message queue is a circular queue, when the tail pointer points to the (message queue depth - 1) position, then the tail Pointer + 1 returns to position 0, so the pointer position + 1 in all embodiments of the present invention is generally defined as (pointer position + 1) % message queue depth, where % is a remainder operator; it should be noted that the present invention The method for indicating the message queue and the method for determining whether the message queue is full are used as an example to describe the indication relationship between the message pointer and the position of the message queue. Of course, the method for indicating the message queue to the message queue and determining whether the message queue is The full method can also use other methods without affecting the results of the present invention. The present invention does not specifically defined;

For example, in the message queue of depth 10 shown in FIG. 2B, the location 0 in the message queue stores data information 1, the location 1 stores data information 2, the location 2 stores data information 3, and the remaining message queue locations are empty. Then, at this time, referring to FIG. 2B, the head pointer of the message pointer indicates the position 0 of the message queue, and the tail pointer indicates the position 3 of the message queue; when the data information 4 is stored in the message queue, the message is first determined. The queue is not full, so Store the data information 4 in the message queue position 3 indicated by the tail pointer, and update the tail pointer of the message queue + 1 to the message queue position 4; when reading the data information from the queue, read the message queue position indicated by the head pointer 0 stores the data information 1, and updates the head pointer of the message pointer + 1 to the message queue position 1;

For example, the data cache stores N data (stored in the form of data packets), which are respectively recorded as data packet 1, packet 2 packet N;

Bay ¹ J , corresponding to N data information, respectively recorded as data information 1, data information 2 data information N, each data information corresponds to a data packet, each data information may contain data corresponding to the data information The physical memory address and data characteristics of the location where the packet is stored in the data cache;

Assume that the message queue has a depth of S and the message queue is empty. The location of the message queue can be recorded as message queue position 0, message queue position 1 message queue position

S-1, where S is far greater than N, storing data information from the message queue position 0, the message queue storing data information 1, data information 2 data information N, the corresponding head pointer in the message pointer indicating the message queue position 0, and the tail pointer indicates the message queue position N;

Assume again that the message queue has a depth of Y and the message queue is empty. The location of the message queue can be recorded as message queue position 0, message queue position 1 message queue position Y-1, where Y is less than N, from the message queue location 0 starts to store data information, the message queue stores data information 1, data information 2 data information Y-1, then, data information Y data information N will wait for the message queue to have an idle location to be generated and stored; corresponding message pointer The head pointer indicates that the message queue location is 0, and the tail pointer indicates the message queue location Y1.

The data access request may be generated by the first device, where the first device reads the data packet in the first memory area and the first device stores the data packet in the first memory area as an example to describe a data access request generation process.

1. The first device reads the data packet in the first memory area;

For example, the first device acquires the physical memory address of the data message in the message pointer in real time, and assumes that the current device acquires the physical memory address of the data information 2, and the first device generates a data access request for accessing a message queue, the data access request including a physical memory address of the data information 2;

It is assumed that the first device obtains the data information 2 from the message queue according to the physical memory address of the data information 2, obtains the physical memory address of the data packet 2 according to the data information 2, and the first device generates a data access request for accessing the data cache, the data access The request contains the physical memory address of packet 2.

2. The first device stores the data packet to the first memory area.

For example, when the first device needs to save the data X to the first memory area, the first device applies to the first memory area for the data cache required to store the data packet X, and obtains the physical memory allocated to the data packet X in the data cache. Memory address

The first device generates a data access request according to a memory allocation to the physical memory address of the data packet X in the data cache, and the data access request includes a physical memory address allocated by the memory to the data packet X in the data cache.

The physical memory address information in the I/O virtualization controller device is queried according to the physical memory address of the data requested by the first device; wherein, the physical memory address;

Further, before step 119, the method may further include:

Mapping the physical memory address of the first memory area to the I/O virtualization controller device to form physical memory address information;

The physical memory address of the first memory area includes a data cache, a message queue, and a physical memory address of the message pointer.

Mapping a physical memory address of the first memory area to the first device.

The physical memory address information is formed by mapping the physical memory address of the first memory area to the I/O virtualization controller device, and the physical memory address information may be in a table form in the I/O virtualization controller device. Existence, see Table 1, may also exist in other forms, and the form of physical memory address information does not affect the result of the present invention, and the present invention does not limit this; Table 1

Physical memory address 1

Physical memory address 2

Physical memory address 3 physical memory address N

Optionally, the I/O virtualization controller device includes a physical memory address information database composed of at least one physical memory address information, where each physical memory address information corresponds to a different memory region;

Exemplarily, when multiple devices access physical memory at the same time, multiple memory areas are allocated in physical memory. Of course, different devices can correspond to the same memory area; by mapping the physical memory address of each memory area to I /O Virtualization controller device forms physical memory information, and the I/O virtualization controller device includes a physical memory information database composed of multiple physical memory information, where each physical memory address information corresponds to a different one. Memory area, different devices can correspond to the same physical memory address information;

The physical memory address information in the physical memory address information database corresponds to a plurality of memory regions, respectively, and the physical memory address information library may exist in the form of a table in the I/O virtualization controller device, see Table 2, of course. The physical memory address information database may also exist in other forms in the I/O virtualization controller device. The form of the physical memory address information database does not affect the result of the present invention, and the present invention does not limit this;

Table 1

It should be noted that multiple devices can correspond to the same memory area, and I/O is virtual. In the physical memory address information library of the controller device, multiple devices may correspond to the same physical memory address information. For example, the physical memory address information of the first device shown in Table 2 may be the physical memory address of the Nth device. The same information;

Correspondingly, the physical memory address information of the I/O virtualization controller device is queried according to the physical memory address of the data requested by the first device, which may include

Querying the physical memory address information base according to the data access request of the first device to access the first memory area, and acquiring physical memory address information corresponding to the memory area corresponding to the first device;

Querying physical memory address information corresponding to the first memory area in the I/O virtualization controller device according to a physical memory address of the data requested by the first device.

If the physical memory address of the data requested by the first device is determined to be in the physical memory address information in the I/O virtualization controller device, accessing the first memory area i or .

Illustratively, if the physical memory address of the data requested by the first device included in the data access request is in the physical memory address information in the I/O virtualization controller device, the first device sends the request to access the first The data access request in the memory area can correctly access the first memory area, and does not accidentally step on the system memory, that is, it does not affect the security of the system memory.

Further, the method may further include

If it is determined that the physical memory address of the data requested by the first device is not in the physical memory address information in the I/O virtualization controller device, the data access request is discarded.

Optionally, the method may further include:

If it is determined that the physical memory address of the data requested by the first device is not in the physical memory address information in the I/O virtualization controller device, the abnormal information is recorded.

The method for accessing the memory provided by the embodiment of the present invention, by acquiring the data access request of the first device requesting access to the first memory area, where the data access request includes the physical memory address of the data requested by the first device The first memory The area is a dedicated physical memory area corresponding to the first device; the physical memory address information in the I/O virtualization controller device is queried according to the physical memory address of the data requested by the first device; wherein the physical memory address information Having the physical memory address of the data accessed by the first memory area in the physical memory address information in the I/O virtualization controller device, accessing the first memory area; effectively improving system memory safety. Embodiment 2

The second embodiment of the present invention provides a method for accessing a memory. In the X86 system, the CPU cooperates with the FPGA in the FPGA packet forwarding system to store data in the memory as an example, and the method for accessing the memory shown in FIG. 1 is described in detail. The specific process of accessing the memory method can be completed by the physical machine where the physical memory is located;

It should be noted that, in FIG. 3, in the CPU of the X86 system and the FPGA packet forwarding system, the interaction data between the FPGA and the physical memory includes the FPGA storing data and reading data to the physical memory, and the embodiment of the present invention only uses the FPGA as the first The device stores data in physical memory as an example to describe the method of accessing memory. The method for accessing memory by other devices is similar to the method for accessing memory by FPGA, and will not be described here.

Referring to Figure 4, the method can include:

401. Allocate a first memory area in physical memory.

According to the requirements of the CPU and the FPGA packet forwarding system, a dedicated physical memory area corresponding to the CPU and the FPGA is allocated in the physical memory, that is, the first memory area is defined as forwarding memory;

For example, the CPU and the FPGA packet forwarding system require 1 kilobit (KiloByte, referred to as KB) physical memory for packet forwarding. In the physical memory, 1 KB of physical memory is allocated as forwarding memory, and the starting physical memory address is 2001H. The physical memory address of the forwarding memory is 2001 H ~ 2400H;

It should be noted that, in this embodiment, a continuous physical memory area is allocated in the physical memory as an example of forwarding memory, and which part of the physical memory is allocated as The forwarding memory is not specifically limited in the present invention.

402. The physical memory address of the forwarding memory is mapped to a Direct Memory Access Remapping (DMA Remapping) structure to form physical memory address information; and the physical memory address of the forwarding memory is mapped to the FPGA;

The DMA Remapping is to cooperate with the I/O virtualization controller device in the X86 system. In this embodiment, the method for accessing the memory is only described by using the X86 as an example. For the type of the I/O virtualization controller device, the embodiment of the present invention Without limitation, it is only necessary to ensure that the I/O virtualization controller device is matched with the system used by the method of the present invention; any method for accessing memory through the I/O virtualization controller device belongs to the protection scope of the present invention; for example; The physical memory address 2001H ~ 2400H of the forwarding memory is mapped into the DMA Remapping structure, and the physical memory address information formed is as shown in Table 3;

table 3

2001H 2002H 2003H

2400H After the physical memory addresses of the forwarding memory are mapped to the DMA Remapping structure and the FPGA respectively, the mapping between the forwarding memory, the DMA Remapping structure and the FPGA is completed; thereafter, the interaction between the FPGA and the forwarding memory The physical memory address contained in the data is monitored and controlled by the DMA Remapping structure.

403. Define a reference address and a message queue depth of the message queue in the forwarding memory. Wherein, according to the requirement of the CPU and the FPGA packet forwarding system, the physical memory area as the message queue is allocated in the forwarding memory, and the reference address of the allocated message queue is included. And message queue depth;

For example, a CPU with an FPGA packet forwarding system requires a message queue of depth 10. According to the requirement, in the forwarding memory, a message queue with a base address of 2001H and a depth of 10 is defined; then, the position in the message queue can be recorded as message queue position 0, message queue position 1, message queue position 2, message queue position 9 ;

Therefore, the device that reads the data packet from the physical memory can obtain the physical memory address of the message queue storing the data information according to the message queue position indicated by the header pointer in the message pointer and the reference address of the message queue;

Correspondingly, the area in the forwarding memory except the message queue and the message pointer is the data buffer area.

404. Initiate a storage request to obtain a physical memory address.

For example, if the FPGA receives a packet X with a size of 1 byte (Byte, abbreviated as B), the packet X needs to be forwarded out. First, the packet X needs to be stored in the forwarding memory.

The storage request is initiated, and the physical memory with a length of 1 B is used to store the data packet X. Assume that the physical memory address of the physical memory with a length of 1 B is 2300H.

405. Obtain a data access request for requesting access to the forwarding memory, where the data access request includes the physical memory address obtained in step 404;

After the physical memory for storing the data packet X is obtained in step 404, a data access request needs to be generated, and the data packet X is requested to be stored in the physical entity obtained in step 404;

For example, the data access request for accessing the forwarding memory is obtained, and the data access request includes the physical memory address obtained in step 404, that is, the application for storing the data packet X in the physical memory with the physical memory address of 2300H.

406. Query the physical memory address information of the DMA Remapping structure according to the physical memory address included in the data access request, and check whether the physical memory address included in the data access request is in the physical memory address information of the DMA Remapping structure; if yes, execute step 407. If not, proceed to step 409;

For example, in step 405, a data access request is obtained, where the data access request includes the physical memory address of the physical memory acquired in step 404, that is, 2300H; The physical memory address 2300H included in the data access request queries the physical memory address information shown in Table 3, and detects whether the physical memory address 2300H included in the obtained data access request is in the physical memory address information of the DMA Remapping structure;

The physical memory address contained in the physical memory address information shown in Table 3 is 2001H - 2400H, and the physical memory address contained in the obtained data access request is 2300H. After detection, the physical content included in the acquired data access request can be determined. The memory address 2300H is in the physical memory address information of the DMA Remapping structure;

For example, if the physical memory address obtained in step 404 is 2600H, the data access request obtained in step 405 includes the physical memory address of the physical memory obtained in step 404, that is, 2600H, and then according to the acquired data. The physical memory address 2600H included in the access request is used to query the physical memory address information shown in Table 3, and it is detected whether the physical memory address 2600H included in the obtained data access request is in the physical memory address information of the DMA Remapping structure;

The physical memory address contained in the physical memory address information shown in Table 3 is 2001H - 2400H, and the physical memory address contained in the obtained data access request is 2600H. After detection, the physical content included in the acquired data access request can be determined. The memory address 2600H is not in the physical memory address information of the DMA Remapping structure.

407. Store the data packet that needs to be forwarded into a physical memory location corresponding to a physical memory address included in the data access request.

For example, step 406 determines, according to the physical memory address information of the physical memory address 2300H included in the obtained data access request, the physical memory address information of the physical memory address 2300H included in the acquired data access request in the DMA Remapping structure. In the middle, the packet X is stored in the physical memory where the physical memory address is 2300H.

408. Generate data information, and store the data information in a message queue, and update the message pointer;

The data characteristics of the data packet can include data size, data type, data length, etc. The data feature is not specifically limited in the present invention;

It should be noted that, before storing the data information in the message queue, first determine whether the message queue is full; if the message queue is full, wait for the message queue to have an idle position and then generate data information; for determining whether the message queue is full The method has been described in detail in the first embodiment, and will not be described again here;

If the message queue is not full, the generated message information is stored in the message queue. In this embodiment, the message queue is not full as an example.

If the message queue is not full, it is generally selected to forward the first idle position in the message queue in the memory, that is, the position indicated by the tail pointer in the message pointer; of course, other idle locations in the message queue may also be selected to store the idle location to store the data packet. Physical memory address and data characteristics, the specific location is not limited;

Further, after the data information is stored in the first idle position of the message queue, the position indicated by the tail pointer in the message pointer is updated, so that the position indicated by the tail pointer in the message pointer is + 1;

For example, after storing the data packet X in the physical memory with the physical memory address of 2 3 0 0 H, the data location of the data packet X, that is, the physical memory address 2 3 0 0 H and the data characteristics of the data packet X, generates data information. X; storing the data information X in the first idle position of the message queue in the forwarding memory, that is, the position indicated by the tail pointer in the message pointer;

Suppose that the tail pointer of the message pointer indicates that the first idle location in the message queue is the message queue location 4, then the data information is stored in the location;

And updating the tail pointer in the message pointer to indicate the message queue position 5;

It should be noted that, in the process of generating the data information X, it is possible to include the wrong physical memory address in the data information X, that is, the physical memory address contained in the data information X is not the location where the data packet X is actually saved; Any kind of error can be detected and corrected by the method of accessing the memory according to the present invention during the process of the first device accessing the physical memory to read the data packet.

4 09, discard data access request;

For example, querying Table 3 in step 060 can determine that the physical memory address contained in the data access request is not in the physical memory address information of the DMA Rema pping structure, so The data packet X can be stored in the physical memory address where the physical memory address is 2600H, and the data access request is discarded.

After discarding the data access request, step 404 is performed to obtain the physical memory address of the physical memory used to store the data packet X;

410. Record error access information.

For example, if the data access request is discarded, the error access information is recorded, so that the device accessing the memory can locate the access problem, thereby improving the maintainability of the system;

It should be noted that, in the process of storing the data packet in the physical memory, the embodiment only uses the request for storing the data packet X in the physical memory as a data access request as an example. In actual use, the physical memory is stored. Any request that includes a physical memory address in the data process can be used as a data access request, which is not limited by the present invention and is within the scope of the present invention.

The method for accessing the memory provided by the embodiment of the present invention obtains a data access request for requesting access to the forwarding memory, where the data access request includes a physical memory address requesting to store the data packet X; and the physical memory address of the data packet X is stored according to the request. Querying the physical memory address information in the DMA Remapping structure; if it is determined that the physical memory address of the request packet X is in the physical memory address information in the DMA Remapping structure, accessing the forwarding memory; detecting whether the physical memory address of the request packet X is stored In the allocated dedicated physical memory area, prevent the physical memory address of the request X from storing the packet X. If it is not in the allocated dedicated physical memory area, the error of storing the packet X in the system memory affects the security of the system memory; Improve the security of system memory. Embodiment 3

A third embodiment of the present invention provides a method for accessing a memory. The method for accessing a memory shown in FIG. 1 is described in detail by taking a data packet from a physical memory as an example. The specific process of accessing the memory may be performed by physical memory. The physical machine where it is located is completed.

Method for allocating physical memory address mapping of the first memory area and the first memory area and definition of the message queue, and step 401, step 402 and steps in the second embodiment The method described in 403 is similar, and this embodiment will not be described herein again; in this embodiment, it is assumed that: the physical address in the first memory area is 2001H ~ 2400H; the message queue depth is 10, and the reference address is 2001H; The physical address of the location where the packet X is stored is 2300H; the data information X corresponding to the packet X is stored in the message queue position 4 of the message queue, and the head pointer of the message pointer indicates the position 4 of the message queue; Background, detailing a detailed process of a method of reading a packet X from physical memory, see FIG. 5, the method may include:

501. Obtaining, in real time, a message queue position indicated by a head pointer in a message pointer in the first memory area to obtain a physical memory address of the data information X;

For example, the real-time acquisition of the last non-empty message queue position indicated by the head pointer in the message pointer in the first memory area is the message queue position 4, and the physical structure of the message queue storing the data information X can be obtained according to the reference address 2001H of the message queue. The memory address is 2005H.

502. Obtain data information X.

For example, according to the physical memory address of the data information X obtained in step 501, the data information X stored at the location is obtained at the location indicated by the physical memory address 2005H in the physical memory.

503. Obtain, according to the data information X obtained in step 502, a physical memory address of a data cache in which the data packet is stored;

For example, according to the data information X obtained in the physical memory address 2005H location in the physical memory, the location where the packet X is stored, that is, the location of the physical memory address 2300H in the physical memory is obtained;

Or, suppose that in the process of storing the data packet X into the physical memory, when the data information X is generated, the physical memory address contained in the generated data information X is not the actual location of the saved data packet X, but the location of the system memory is 2701 H. At this time, when the data information X is obtained in the physical memory address 2005H position in the physical memory, the location where the data packet X is stored is the location of the physical memory address 2701 H in the physical memory.

504. Obtain a data access request for requesting access to the first memory area, where the data access request includes the physical memory address obtained in step 503. For example, obtaining a data access request for accessing the first memory area, where the data access request includes the physical memory address 2300H acquired in step 503, that is, applying for reading the data stored in the location indicated by the physical memory address 2300H in the physical memory;

Alternatively, the data access request for accessing the first memory area is obtained, and the data access request includes the physical memory address 2701H acquired in step 503, that is, the data stored in the location indicated by the physical memory address 2701 H in the physical memory is requested to be read.

505. Query the physical memory address information of the DMA Remapping structure according to the physical memory address included in the data access request, and check whether the physical memory address included in the data access request is in the physical memory address information of the DMA Remapping structure; if yes, execute step 506. If not, proceed to step 507;

For example, according to the physical memory address information shown in Table 3 of the physical memory address 2300H included in the data access request, it is detected whether the physical memory address 2300H included in the data access request is in the physical memory address information of the DMA Remapping structure;

The physical memory address contained in the physical memory address information shown in Table 3 is 2001H - 2400H, and the physical memory address contained in the obtained data access request is 2300H. After detection, the physical content included in the acquired data access request can be determined. The memory address 2300H is in the physical memory address information of the DMA Remapping structure, step 506 is performed;

Or, according to the physical memory address information indicated by the physical memory address 2701H included in the obtained data access request, the physical memory address information included in the obtained data access request is detected in the physical memory of the DMA Rema pp i ng structure. Address information;

The physical memory address contained in the physical memory address information shown in Table 3 is 2001H - 2400H, and the physical memory address included in the obtained data access request is 2701H. After detection, the physical content included in the acquired data access request can be determined. If the memory address 2701 H is not in the physical memory address information of the DMA Remapping structure, step 507 is performed.

506. Read a data packet stored in a physical memory location corresponding to a physical memory address included in the data access request, and update the message pointer. For example, step 503 determines, according to the physical memory address 2300H included in the obtained data access request, the physical memory address information shown in Table 3, and determines that the physical memory address 2300H included in the data access request is in the physical memory address information of the DMA Remapping structure. Then reading the data packet X stored in the physical memory location corresponding to the physical memory address 2300H included in the data access request;

Further, the position indicated by the head pointer in the message pointer is updated such that the position indicated by the head pointer in the message pointer + 1 , that is, the head pointer in the update message pointer indicates the message queue position 5.

507. Discard the data access request.

For example, if it is determined in step 505 that the physical memory address included in the data access request is not in the physical memory address information of the DMA Remapping structure, the access to the memory cannot be performed, and the data access request is discarded;

After discarding the data access request, step 501 is re-executed to obtain the location indicated by the head pointer in the message pointer.

508. Record error access information.

For example, if the data access request is discarded, the error access information is recorded, so that the device accessing the memory can locate the access problem, thereby improving the maintainability of the system.

It should be noted that, in the process of reading data from the physical memory, the embodiment only uses the request for accessing the data packet X in the physical memory address as a data access request as an example. In actual use, the physical memory is used. Any request for a physical memory address in the process of reading data may be used as a data access request, which is not limited by the present invention and is within the scope of the present invention.

A method for accessing a memory by accessing a memory request requesting access to a forwarding memory, wherein the data access request includes a physical memory address of the data requested to be read; a physical memory address of the data read according to the request Querying the physical memory address information in the DMA Remapping structure; if it is determined that the physical memory address of the data requested to be read is in the physical memory address information in the DMA Remapping structure, accessing the forwarding memory; detecting the physical memory address of the data read by the request Whether it is in the dedicated physical memory area allocated, preventing the physical memory stored in the read data packet When the memory address is not in the allocated dedicated physical memory area, the system memory packet is read and received, which affects the security of the system memory and effectively improves the security of the system memory. Embodiment 4

A fourth embodiment of the present invention provides a method for accessing a memory. The method for accessing memory in FIG. 1 is described in detail by taking N devices simultaneously accessing memory in an X86 system. Referring to FIG. 6, in the X86 system, there is a N. Devices access memory, respectively, as devices

1. Device 2, Device 3 Device N, This embodiment describes the device 1, device 2, device 3 device N access memory method;

Referring to Figure 7, the method may include:

701. Allocate a dedicated memory area to each device in physical memory;

For example, in the physical memory, device 1, device 2, device 3 device N are respectively allocated memory area i or 1, memory area i or 2, memory area i or 3 memory area i or N; of course, multiple devices can correspond to the same A memory area, so, in the memory area 1, memory area 2, memory area 3 memory area N can have the same memory area, this embodiment is memory area i or 1, memory area i or 2, memory area i Or 3, ... the memory area N is all different for an example.

702. Map physical memory addresses of the N memory areas to physical memory address information in the DMA Remapping structure.

For example, ^ capture memory area i or 1, memory area i or 2, memory area i or 3 memory area i or

N physical memory address is divided into another 'J mapping to DMA Remapping structure, forming N physical memory address information, recorded as physical memory address information 1, physical memory address information 2, physical memory address information 3 physical memory address information N;

The device, the memory area, and the physical memory address information correspond to each other; physical memory address information 1, physical memory address information 2, physical memory address information 3, ... physical memory address information N constitutes a physical memory address in the DMA Remapping structure database.

703. Obtain the data access of the application sent by the first device to access the first memory area. The data access request includes a physical memory address of data requested by the first device to access;

For example, the data access request sent by the device N to access the memory area N is obtained, where the access request includes the physical memory address of the data that the device N requests to access.

704. Query the physical memory address information base according to the data access request of the first device to access the first memory area, and obtain the physical memory address information corresponding to the first memory area. For example, accessing the data access of the memory area N according to the application sent by the device N. The physical memory address information database corresponding to the first memory area corresponding to the first device is obtained.

705. Query the physical memory address information obtained by the step 704 according to the physical memory address of the data requested by the first device, and check whether the physical memory address of the data requested by the first device is in the physical memory corresponding to the first device in the DMA Remapping structure. In the address information; if yes, step 706 is performed; if not, step 707 is performed;

For example, according to the physical memory address of the data requested by the device N requested by the device N accessed by the device N to access the memory area N, the physical memory address information N is queried, and the physical memory address of the data requested by the device N is determined to be in the DMA. The physical memory address information N corresponding to the device N in the Remapping structure.

706. Access data requested to be accessed in the first memory area.

For example, if the step 705 determines that the physical memory address of the data requested by the device N is in the physical memory address information N corresponding to the device N in the DMA Remapping structure, the data requested in the memory region N is accessed.

707. Discard the data access request.

For example, discard the data access request sent by device N.

708. Record error access information.

For example, if the data access request is discarded and the error access information is recorded, so that the device N locates the access problem, the maintainability of the system can be improved.

The method for accessing the memory provided by the embodiment of the present invention, when a plurality of devices access the memory, requesting the first device to access the data access request of the first memory area, where the data access request includes the first The physical of the data that the device is requesting access to The memory address is obtained by querying the physical memory address information base according to the physical memory address of the data requested by the first device, and acquiring the physical memory address information corresponding to the first memory area; and querying the I/O according to the physical memory address of the data requested by the first device. The physical memory address information corresponding to the first memory area in the virtualization controller device; if it is determined that the physical memory address of the data requested by the first device is in the physical memory address information in the I/O virtualization controller device, access The first memory area; effectively improves the security of the system memory. Embodiment 5

The fifth embodiment of the present invention provides a device for accessing a memory 80. Referring to FIG. 8, the device 80 may include:

The obtaining unit 8 01 is configured to obtain a data access request that the first device requests to access the first memory area, where the data access request includes a physical memory address of the data that the first device requests to access; the first memory area a dedicated physical memory area i corresponding to the first device;

The first device is a device that implements a specific function by accessing a physical memory of the computer. For example, in the CPU and the FPGA packet forwarding system, the first device is a CPU or an FPGA; or the first device may be a virtualized virtual platform. Peripheral of the machine; the present invention does not specifically limit the type of the first device;

The first memory area is a dedicated physical memory area in which the first device allocated in the physical memory implements the corresponding function. For example, referring to FIG. 2, the first memory area is included in the physical memory, and the first memory area includes at least the data cache and the message. a queue and a message pointer; wherein, the data cache is used to store data accessed by the first device in implementing the corresponding function, and the data may be stored in the data cache in the form of a data packet;

The message queue may be a circular queue, and the message queue includes data information arranged in a queue form, and each data information is used to store related information of corresponding data in the data cache, for example, may include a location where the data is stored in the data cache. The physical memory address and data characteristics, for example, the data feature may include the type, size, length, etc. of the data, and the specific content of the data feature included in the data information may be as needed The setting is made, and the present invention is not specifically limited;

It should be noted that when the depth of the message queue is smaller than the capacity of the data cache, the data information corresponding to each data stored in the data cache may store a part of the data information in the message queue, and some of the data information will wait for the message queue to have a free location. Regenerated and stored;

The message pointer is used to indicate the location of the data information in the message queue. The message pointer is divided into a head pointer and a tail pointer. For example, the head pointer can be used to indicate the last non-idle position in the message queue, and the tail pointer can be used to indicate the number in the message queue. An idle location, so that the location of the data in the message queue and the free location can be clearly indicated by the indication of the message pointer; when the first device reads the data information from the message queue, it can be based on the reference address of the message queue. Adding the actual physical memory address where the data information is stored by adding the message queue position indicated by the message pointer head pointer;

For example, the data cache stores N data (stored in the form of data packets), which are respectively recorded as packet 1 and packet 2 packet N.

S - 1 , where S is far greater than N, storing data information from the message queue position 0, the message queue storing data information 1, data information 2 data information N, the corresponding head pointer in the message pointer indicating the message queue position 0 , and the tail pointer indicates the message queue position N;

Assume again that the message queue has a depth of Y and the message queue is empty. The location of the message queue can be recorded as message queue position 0, message queue position 1 message queue. Position Y-l, where Υ is less than Ν, data information is stored from message queue position 0, data message 1 is stored in message queue, data information 2 data information Y-1, then data information Υ data information Ν will wait for message The queue has an idle location that is regenerated and stored; the head pointer in the corresponding message pointer indicates the message queue location 0, and the tail pointer indicates the message queue location Y-l.

1. The first device reads the data packet in the first memory area;

For example, the first device acquires the physical memory address of the data message in the message pointer in real time, and assumes that the first device acquires the physical memory address of the data information 2, and the first device generates a data access request for accessing the message queue, where the data access request includes The physical memory address of data information 2;

2. The first device stores the data packet to the first memory area.

The query unit 802 is configured to query physical memory address information in the I/O virtualization controller device according to the physical memory address of the data requested by the first device acquired by the acquiring unit 810; wherein, the physical The memory address information is further included with the first one. Referring to FIG. 9, the device may further include The mapping unit 804 is configured to map the physical memory address of the first memory area to the I/O virtualization controller device before the acquiring unit 801 acquires the data access request of the first device requesting access to the first memory area Forming physical memory address information; wherein, the physical memory address of the first memory area includes a physical memory address of the data cache, the message queue, and the message pointer.

The mapping unit 804 is further configured to map the physical memory address of the first memory area to the first device.

The physical memory address information is formed by mapping the physical memory address of the first memory area to the I/O virtualization controller device, and the physical memory address information may be in a table form in the I/O virtualization controller device. Existence, see Table 1, may also exist in other forms, and the form of physical memory address information does not affect the result of the present invention, and the present invention does not limit this;

Correspondingly, the query unit 802 can be specifically used to:

Querying the physical according to the data access request of the first device requesting access to the first memory area The memory address information base acquires physical memory address information corresponding to the memory area corresponding to the first device;

The physical memory address information corresponding to the first memory area in the I/O virtualization controller device;

The access unit 803 is configured to: if the query unit 802 determines that the physical memory address of the data requested by the first device is in the physical memory address information in the I/O virtualization controller device, accessing the first memory Area

Further, the device 80 may further include

The discarding unit 805 is configured to: if the query unit 802 determines that the physical memory address of the data requested by the first device is not in the physical memory address information in the I/O virtualization controller device, the data is Access request is discarded.

Optionally, the device 80 may further include

The recording unit 806 is configured to: if the query unit 802 determines that the physical memory address of the data requested by the first device is not in the physical memory address information in the I/O virtualization controller device, the abnormal information is recorded.

The device 80 for accessing the memory provided by the embodiment of the present invention acquires a data access request of the first memory area by requesting the first device, where the data access request includes the physical memory of the data requested by the first device. The first memory area is a dedicated physical memory area corresponding to the first device; and the physical memory address information in the I/O virtualization controller device is queried according to the physical memory address of the data requested by the first device; The physical memory address information includes a physical memory address of the data accessed by the first memory in the I/O virtualization controller device In the memory address information, the first memory area is accessed; the security of the system memory is effectively improved. Embodiment 6

The sixth embodiment of the present invention provides a device 100 for accessing a memory. Referring to FIG. 10, the device 100 may include:

The processor 1001, the I/O virtualization controller device 1002, the first device 1003, and at least one communication bus 1004 are configured to implement connection and mutual communication between the devices. The processor 1001 may be a central processing unit (English: Central processing unit, referred to as CPU);

The processor 1001 is configured to obtain a data access request that the first device 1003 requests to access the first memory area, where the data access request includes a physical memory address of the data that the first device requests to access; The memory area is a dedicated physical memory area corresponding to the first device;

The first device is a device that implements a specific function by accessing a physical memory of the computer. For example, in the CPU and the FPG A packet forwarding system, the first device is a CPU or an FPGA; or the first device may be in a virtualization platform. The peripheral device of the virtual machine; the present invention does not specifically limit the type of the first device;

The message queue may be a circular queue, and the message queue includes data information arranged in a queue form, and each data information is used to store related information of corresponding data in the data cache, for example, may include a location where the data is stored in the data cache. The physical memory address and the data feature, for example, the data feature may include the type, the size, the length, and the like of the data. The specific content of the data feature included in the data information may be set as needed, and the present invention is not specifically limited; The depth of the message queue refers to the capacity that the message queue can use to store data information. Each message queue can be a depth-determined and limited circular queue, and the depth of the message queue can be smaller than the capacity of the data cache;

Assume again that the message queue has a depth of Y and the message queue is empty. The location of the message queue can be recorded as message queue position 0, message queue position 1 message queue position Y - 1 , where Y is less than N, from the message queue location 0 starts to store data information, The message queue stores data information 1 and data information 2 data information Y-1. Then, the data information Y data information N will wait for the message queue to have an idle location to be regenerated and stored; the head pointer in the corresponding message pointer indicates the message queue position. 0 , and the tail pointer indicates the message queue position Y- l.

1. The first device reads the data packet in the first memory area;

For example, the first device acquires the physical memory address of the data message in the message pointer in real time, and assumes that the current device acquires the physical memory address of the data information 2, and the first device generates a data access request for accessing the message queue, where the data access request includes The physical memory address of data information 2;

2. The first device stores the data packet to the first memory area.

The I/O virtualization controller device 1 002 is configured to query physical memory address information in the I/O virtualization controller device 1 002 according to a physical memory address of the data requested by the first device 1 003; The physical memory address information is included in the first step, and the processor 1 001 may be specifically configured to: before the acquiring, by the first device, a data access request for accessing the first memory area, the first Memory area Mapping a physical memory address of the domain into the I/O virtualization controller device to form the physical memory address information;

The processor 1001 is further configured to: map a physical memory address of the first memory area to the first device.

Correspondingly, the I/O virtualization controller device 1002 is further configured to: query the physical memory address information database according to the data access request of the first device 1003 to access the first memory area, and obtain the corresponding Memory area corresponding Physical memory address information;

The physical memory address information corresponding to the first memory area in the I/O virtualization controller device 1002 is queried according to the physical memory address of the data requested by the first device 1003.

The first device 1003 is configured to: if the I/O virtualization controller device 1002 determines the physical memory address information of the physical memory address of the data requested by the first device 1003 in the I/O virtualization controller device 1002 Accessing the first memory area; exemplarily, if the physical memory address of the data requested by the first device included in the data access request is in the physical memory address information in the I/O virtualization controller device, The data access request sent by the first device to access the first memory area can correctly access the first memory area, and the system memory is not accidentally stepped on, that is, the system memory security is not affected.

Further, the I/O virtualization controller device 1002 is further configured to: if it is determined that the physical memory address of the data requested by the first device 1003 is not in the physical state of the I/O virtualization controller device 1002 In the memory address information, the data access request is discarded.

Optionally, the I/O virtualization controller device 1002 is further configured to: if it is determined that the physical memory address of the data requested by the first device 1003 is not in the physical of the I/O virtualization controller device In the memory address information, the abnormal information is recorded.

The device 100 for accessing the memory provided by the embodiment of the present invention acquires a data access request of the first memory area by requesting the first device, where the data access request includes the physical memory of the data requested by the first device. The first memory area is a dedicated physical memory area corresponding to the first device; and the physical memory address information in the I/O virtualization controller device is queried according to the physical memory address of the data requested by the first device; The physical memory address information includes a physical memory address of the data accessed by the first memory in the physical memory address information in the I/O virtualization controller device, and the first memory area is accessed. Effectively improved the system Memory security. Example 7

The seventh embodiment of the present invention provides a physical machine 110. Referring to FIG. 11A and FIG. 11B, the physical machine 110 may include:

The device 80 or 90 for accessing the memory according to any of the above embodiments;

The physical memory 1101 may include read only memory and random access memory for storing data of the device 80 or 90 accessing the memory; a portion of the physical memory 1101 may also include non-volatile random access memory (NVRAM).

The device for accessing the memory includes a first device and an I/O virtualization controller device;

The device 80 or 90 that accesses the memory can be used,

And if it is determined that the physical memory address of the data requested by the first device is in the physical memory address information in the I/O virtualization controller device, accessing the first memory area.

Further, the device 80 or 90 for accessing the memory may be further configured to: map the physical memory address of the first memory area to the location before the acquiring the first device requests the data access request of the first memory area In the I/O virtualization controller device, the physical memory address information is formed;

Mapping a physical memory address of the first memory area to the first device. Optionally, the I/O virtualization controller device includes a physical memory address information library composed of at least one physical memory address information, where each physical memory location The address information respectively corresponds to a different memory area; correspondingly, the device 80 or 90 for accessing the memory is specifically used,

Further, the device 80 or 90 that accesses the memory can also be used,

The physical machine 1 1 0 provided by the embodiment of the present invention obtains a data access request of the first memory area by requesting the first device, where the data access request includes the physical memory of the data requested by the first device. The first memory area is a dedicated physical memory area corresponding to the first device; and the physical memory address information in the I/O virtualization controller device is queried according to the physical memory address of the data requested by the first device; The physical memory address information includes a physical memory address corresponding to a physical memory address of the first memory area; if it is determined that the physical memory address of the data requested by the first device is in the I/O virtualization controller In the physical memory address information in the device, accessing the first memory area effectively improves the security of the system memory.

A person skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can be referred to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, such as multiple units or groups. Pieces can be combined or integrated into another system, or some features can be ignored, or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical or otherwise.

The units described as separate components may or may not be physically separated, and the components displayed as the units may or may not be physical units, and may be located in one place or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiment of the present embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

The above-described integrated unit implemented in the form of a software functional unit can be stored in a computer readable storage medium. The software functional unit described above is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform portions of the steps of the various embodiments of the present invention. The foregoing storage medium includes: a U disk, a mobile hard disk, a read only memory (R ea dO nly Memo ry, abbreviated as), a random access memory (Ra ndom A ccess Memo ry, RAM for short), a magnetic disk or an optical disk, and the like. A medium that can store program code.

It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

claims

1. A method of accessing memory, characterized by:

Obtain a data access request from the first device to access the first memory area, where the data access request includes the physical memory address of the data that the first device requests to access; the first memory area is dedicated to the first device. physical memory area;

Query the physical memory address information in the input/output I/O virtualization controller device according to the physical memory address of the data requested to be accessed by the first device; wherein, the physical memory address;

If it is determined that the physical memory address of the data requested to be accessed by the first device is in the physical memory address information in the I/O virtualization controller device, the first memory area is accessed.

2. The method of accessing memory according to claim 1, characterized in that, before obtaining the data access request of the first device requesting access to the first memory area, the method further includes:

Map the physical memory address of the first memory area to the I/O virtualization controller device to form the physical memory address information;

Map the physical memory address of the first memory area to the first device.

3. The method of accessing memory according to claim 1 or 2, characterized in that the I/O virtualization controller device contains a physical memory address information library composed of at least one physical memory address information, wherein each Each piece of physical memory address information corresponds to a different memory area; accordingly, querying the physical memory address information in the I/O virtualization controller device according to the physical memory address of the data requested to be accessed by the first device includes,

Query the physical memory address information library according to the data access request of the first device to access the first memory area, and obtain the physical memory address information of the memory area corresponding to the first device;

Query the physical memory address information corresponding to the first memory area in the I/O virtualization controller device according to the physical memory address of the data requested to be accessed by the first device.

4. The method of accessing memory according to any one of claims 1 to 3, characterized in that the method further includes:

If it is determined that the physical memory address of the data requested to be accessed by the first device is not in the physical memory address information in the I/O virtualization controller device, the data access request is discarded.

5. The method of accessing memory according to claim 4, characterized in that the method further includes:

If it is determined that the physical memory address of the data requested to be accessed by the first device is not in the physical memory address information in the I/O virtualization controller device, exception information is recorded.

6. A device for accessing memory, characterized by:

An acquisition unit configured to acquire a data access request from a first device requesting access to a first memory area, wherein the data access request includes the physical memory address of the data requested by the first device to access; the first memory area is the A dedicated physical memory area corresponding to a device;

A query unit configured to query the physical memory address information in the I/O virtualization controller device according to the physical memory address of the data requested to be accessed by the first device obtained by the acquisition unit; wherein, the physical memory address information includes a physical memory address corresponding to the physical memory address of the first memory area;

The access unit is configured to access the first memory area if the query unit determines that the physical memory address of the data requested to be accessed by the first device is in the physical memory address information in the I/O virtualization controller device.

7. The device for accessing memory according to claim 6, characterized in that the device further includes:

A mapping unit configured to map the physical memory address of the first memory area to the I/O virtualization controller before the acquisition unit obtains the data access request of the first device requesting access to the first memory area. In the device, the physical memory address information is formed; the mapping unit is also used to map the physical memory address of the first memory area to the first device.

8. The device for accessing memory according to claim 6 or 7, characterized in that, The I/O virtualization controller device contains a physical memory address information library composed of at least one physical memory address information, where each physical memory address information corresponds to a different memory area; accordingly, the query unit Specifically used for,

Query the physical memory address information library according to the data access request of the first device to access the first memory area, and obtain the physical memory address information corresponding to the memory area corresponding to the first device;

9. The device for accessing memory according to any one of claims 6 to 8, characterized in that the device further includes:

a discarding unit configured to, if the query unit determines that the physical memory address of the data requested to be accessed by the first device is not in the physical memory address information in the I/O virtualization controller device, discard the data access request Discard.

10. The device for accessing memory according to claim 9, characterized in that the device further includes:

A recording unit, configured to record exception information if the query unit determines that the physical memory address of the data requested to be accessed by the first device is not in the physical memory address information in the I/O virtualization controller device.

1 1. A device for accessing memory, characterized by: including

A processor configured to obtain a data access request from a first device requesting access to a first memory area, wherein the data access request includes the physical memory address of the data requested to be accessed by the first device; the first memory area is the A dedicated physical memory area corresponding to a device;

I/O virtualization controller device, configured to query the physical memory address information in the I/O virtualization controller device according to the physical memory address of the data requested to be accessed by the first device; wherein, the physical memory address The information includes a physical memory address corresponding to the physical memory address of the first memory area;

The first device is used if the I/O virtualization controller device determines that the first device requests If the address information is stored in the first memory area, the first memory area is accessed.

12. The device for accessing memory according to claim 11, wherein the processor is specifically configured to, before obtaining the data access request of the first device requesting access to the first memory area, obtain the first data access request from the first device. The physical memory address of the memory area is mapped to the I/O virtualization controller device to form the physical memory address information;

The processor is specifically configured to map the physical memory address of the first memory area to the first device.

13. The device for accessing memory according to claim 11 or 12, characterized in that, the I/O virtualization controller device contains a physical memory address information library composed of at least one physical memory address information, wherein, each Each piece of physical memory address information corresponds to a different memory area; accordingly, the I/O virtualization controller device is also used to query the physical memory address according to the data access request of the first device requesting access to the first memory area. Information database, obtain physical memory address information corresponding to the memory area corresponding to the first device;

14. The device for accessing memory according to any one of claims 11 to 13, characterized in that the I/O virtualization controller device is also used to:

15. The device for accessing memory according to claim 14, characterized in that the I/O virtualization controller device is also used to:

16. A physical machine, characterized in that it includes a device that accesses memory and a physical memory, wherein the device that accesses memory includes a first device and an I/O virtualization controller device;

The device for accessing memory is used to, Obtain a data access request from the first device to access the first memory area, where the data access request includes the physical memory address of the data that the first device requests to access; the first memory area is dedicated to the first device. physical memory area;

Query the physical memory address information in the I/O virtualization controller device according to the physical memory address of the data requested to be accessed by the first device; wherein, if the physical memory address determines the data requested to be accessed by the first device The physical memory address is in the physical memory address information in the I/O virtualization controller device, then the first memory area is accessed.

17. The physical machine according to claim 16, wherein the device for accessing memory is further configured to: before obtaining the data access request of the first device requesting access to the first memory area, obtain the first data access request from the first device. The physical memory address of the memory area is mapped to the I/O virtualization controller device to form the physical memory address information;

Map the physical memory address of the first memory area to the first device.

18. The physical machine according to claim 16 or 17, characterized in that the I/O virtualization controller device contains a physical memory address information library composed of at least one physical memory address information, wherein each physical memory address information library is composed of at least one physical memory address information. The memory address information respectively corresponds to a different memory area; accordingly, the device that accesses the memory is specifically used to:

19. The physical machine according to any one of claims 16 to 18, characterized in that the device for accessing memory is also used to: