CN109308269B

CN109308269B - Memory management method and device

Info

Publication number: CN109308269B
Application number: CN201710619868.3A
Authority: CN
Inventors: 余攀
Original assignee: Huawei Technologies Co Ltd
Current assignee: Chengdu Huawei Technology Co Ltd
Priority date: 2017-07-26
Filing date: 2017-07-26
Publication date: 2021-02-23
Anticipated expiration: 2037-07-26
Also published as: CN109308269A

Abstract

The embodiment of the application discloses a memory management method and device, relates to the technical field of storage, and solves the problem of memory waste. The specific scheme is as follows: receiving a memory allocation request sent by a target processor for requesting allocation of memory blocks in a computer memory, wherein the computer memory comprises a plurality of processors, the memory comprises a data region and an address region, the data region comprises M memory blocks, the address region comprises N subregions, each subregion stores address information of at least one memory block, the address information stored in different subregions is different, each processor is allocated with an affinity subregion in the N subregions, M is greater than 1, N is greater than 1, and M is greater than or equal to N; identifying an affinity region of a target processor; if the address information of the memory block is not recorded in the affinity sub-area of the target processor, the address information of the memory block is acquired from the first sub-area, and the memory block identified by the acquired address information of the memory block is allocated to the target processor.

Description

Memory management method and device

Technical Field

The embodiment of the application relates to the technical field of storage, in particular to a memory management method and device.

Background

The Memory management is to divide the Memory of the computer into a plurality of Memory pools (Memory pools), place a plurality of Memory blocks in each Memory Pool, and manage each Memory block independently, so as to ensure that each service in the computer can acquire a corresponding Memory space in time, and simultaneously, the operation of other services is not influenced.

Fixed-length memory pool management is a common type of memory management. In the computer, a general fixed-length memory pool management method is as follows: a continuous memory with a fixed capacity (i.e., a fixed-length memory pool, which is subsequently represented by the fixed-length memory pool) includes a plurality of memory blocks with the same length, a plurality of sub-regions storing address information of at least one memory block, and a global queue storing address information of at least one memory block that is not allocated and not stored to any of the sub-regions, each processor (or processor core) in the computer is allocated with a dedicated sub-region in the plurality of sub-regions, and a memory block identified by address information stored in the dedicated sub-region can only be allocated to a processor (or processor core) corresponding to the dedicated sub-region; when memory needs to be allocated to a certain service, firstly, judging whether a special sub-area of a processor (or a processor core) called by the service is empty, namely judging whether the special sub-area of the processor (or the processor core) called by the service records address information; if the special sub-area of the processor (or the processor core) is empty, reading address information of one or some memory blocks from the global queue, writing the read address information into the special sub-area of the processor (or the processor core), and allocating memory for the service according to the stored address information of the processor (or the processor core); if the dedicated sub-area of the processor (or processor core) is not empty, memory is allocated to the service directly according to the address information stored in the processor (or processor core).

The method can access the global queue only when the special sub-area of the processor (or the processor core) called by the service is empty, and the performance is high. However, for any service, the memory in this memory pool may be allocated for that service only in the case of a dedicated global queue of the processor (or processor core) called by that service. However, when the dedicated sub-area of the processor (or processor core) called by the service is empty, the global queue is empty, and the dedicated sub-areas of other processors (or processor cores) are not empty, the memory in the memory pool cannot be allocated to the service any more, which results in memory waste.

Disclosure of Invention

The embodiment of the application provides a memory management method and device, which can solve the problem of memory waste.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, a memory management method is provided for a computer including a plurality of processors, the memory of the computer comprises a data area and an address area, wherein the data area comprises M memory blocks (M >1), the address area comprises N (N >1, N is less than or equal to M) sub-areas, each sub-area is used for storing the address information of at least one memory block, and the address information stored in different sub-regions is different, each processor is allocated with an affinity sub-region in N sub-regions, the memory block identified by the address information stored in the affinity sub-region is preferentially allocated to the processor corresponding to the affinity sub-region, specifically, after receiving a memory allocation request which is sent by a target processor and used for requesting to allocate a memory block in a memory of the computer, responding to the memory allocation request, and identifying an affinity sub-region of the target processor; when the affinity sub-area of the target processor does not record the address information of the memory block, acquiring the address information of one memory block from the first sub-area, and allocating the memory block identified by the acquired address information of the memory block to the target processor, where the first sub-area is one of the N sub-areas except for the affinity sub-area of the target processor.

In the memory management method provided in the embodiment of the present application, each sub-region in the memory may be occupied by multiple processors in the computer, and each processor of the computer is allocated with one affinity sub-region, so that when a memory needs to be allocated to a target processor in the multiple processors, a memory block is preferentially allocated to the target processor according to address information stored in the affinity sub-region of the target processor. When the affinity sub-region of the target processor does not record the address information of the memory block, the address information of one memory block may still be acquired from a sub-region (e.g., the first sub-region) other than the affinity sub-region of the target processor, and the memory block identified by the acquired address information of the memory block is allocated to the target processor, which effectively reduces the waste of memory.

Optionally, in a possible implementation manner of the present application, the memory of the computer further includes address information for storing at least one memory block that is not allocated and is not stored in the address area, so that the method of "acquiring address information of one memory block from the first sub-area when address information of the memory block is not recorded in the affinity sub-area of the target processor" includes: when the address information of the memory block is not recorded in the affinity subarea of the target processor, identifying a global queue; when the address information of the memory block is not recorded in the global queue, the address information of one memory block is acquired from the first subregion.

When the affinity subarea of the target processor does not record the address information of the memory, the address information of the memory block is preferentially acquired from the global queue, so that the memory block occupation of other processors is effectively protected. It is easy to understand that, when the address information of the memory blocks is recorded in the global queue, the address information of a preset number of memory blocks is obtained from the global queue, and the obtained address information of the memory blocks is stored in the affinity sub-region of the target processor, so that the memory blocks can be allocated to the target processor according to the address information stored in the affinity sub-region of the target processor.

Optionally, in another possible implementation manner of the present application, the memory of the computer further includes a latest idle variable, where the latest idle variable is used to indicate a sub-region that is unoccupied and has a shortest time difference from a time point of the unoccupied sub-region to a current time point, and accordingly, the method of "obtaining address information of one memory block from the first sub-region" includes: when the sub-region indicated by the latest idle variable is a first sub-region, determining whether the first sub-region is occupied currently; when the first sub-area is not occupied currently, address information of one memory block is acquired from the first sub-area.

The most recent idle variable is used to indicate the sub-region that is unoccupied and for which the time difference from the moment of being unoccupied to the current moment is the shortest. In practical applications, a sub-region (e.g., sub-region a) is unoccupied, and the time difference from the unoccupied time to the current time is the shortest, the value of the latest idle variable indicates the sub-region a. If no other sub-region is unoccupied within a long period of time during which sub-region a is unoccupied, the value of the most recent idle variable always represents sub-region a within that period of time. Of course, during this long period of time, sub-region A may again be occupied, but no other sub-regions are unoccupied, so that the value of the most recent idle variable still represents sub-region A.

Each sub-area in the memory can be occupied by a plurality of processors in the computer, so that when the address information of the memory block is not recorded in the affinity sub-area of the target processor, the area indicated by the latest idle variable can be directly acquired, whether the area is occupied or not is determined, and the memory allocation efficiency is improved. It can be understood that if the first sub-region indicated by the last idle variable is already occupied, the memory block cannot be allocated to the target processor according to the first sub-region.

Optionally, in another possible implementation manner of the present application, when the sub-region indicated by the latest idle variable is a second sub-region different from the first sub-region, it is determined whether the second sub-region is currently occupied; when the second sub-region is occupied currently, sequentially traversing the N sub-regions from a third sub-region, wherein the third sub-region is a sub-region which is arranged behind the second sub-region and is adjacent to the second sub-region in the N sub-regions; when the first sub-area is determined to be unoccupied and the address information of the memory block is recorded in the first sub-area in the traversal process, the address information of one memory block is acquired from the first sub-area.

Optionally, in another possible implementation manner of the present application, when there is no address information of a memory block in an affinity sub-region of a target processor, sequentially traversing N-1 sub-regions from any sub-region except the affinity sub-region of the target processor, and when it is determined that a first sub-region is not occupied in the traversing process and address information of the memory block is recorded in the first sub-region, acquiring address information of one memory block from the first sub-region.

In the case that the affinity sub-region of the target processor does not have the address information of the memory block, the address information of the memory block may be obtained in any one of the above manners, and then the memory block is allocated to the target processor.

Optionally, in another possible implementation manner of the present application, the address area in the memory of the computer further includes N occupation identifiers, each sub-area has an occupation identifier, and the occupation identifier is used to indicate whether the corresponding sub-area is occupied or not; in this way, after the affinity sub-region of the target processor is identified according to the target processor, whether the affinity sub-region of the target processor is occupied can be determined according to the occupation identifier of the affinity sub-region of the target processor; when the affinity sub-area of the target processor is not occupied, whether address information of the memory block is recorded in the affinity sub-area of the target processor is determined.

When the affinity sub-region of the target processor is occupied, the memory block identified by the address information of the memory block held by the affinity sub-region of the target processor can no longer be allocated to the target processor. The occupation identifier in the embodiment of the application may be represented by an atomic variable, and whether a sub-region is occupied or not is determined according to the occupation identifier, that is, whether the memory block identified by the address information of the memory block stored in the sub-region can be primarily determined to be allocated to the target processor or not is determined, so that the memory allocation efficiency is improved.

In a second aspect, a memory management device is provided, which includes a receiving unit, an identifying unit, an obtaining unit, and an allocating unit. The receiving unit is configured to receive a memory allocation request sent by a target processor, where the memory allocation request is used to request allocation of a memory block in a memory of a computer for the target processor, the computer includes multiple processors, the target processor is one of the multiple processors, the memory includes a data region and an address region, the data region includes M memory blocks, the address region includes N sub-regions, each sub-region is used to store address information of at least one memory block, and address information stored in different sub-regions is different, each processor is allocated an affinity sub-region in the N sub-regions, the memory block identified by the address information stored in the affinity sub-region is preferentially allocated to a processor corresponding to the affinity sub-region, where M >1, N >1, and M > N. The identifying unit is configured to identify, in response to the memory allocation request received by the receiving unit, an affinity sub-region of the target processor according to the target processor. The obtaining unit is configured to, when the affinity sub-area of the target processor identified by the identifying unit does not record address information of the memory block, obtain address information of one memory block from a first sub-area, where the first sub-area is one of the N sub-areas except for the affinity sub-area of the target processor. The allocation unit is configured to allocate the memory block identified by the address information of the memory block acquired by the acquisition unit to the target processor.

Optionally, in a possible implementation manner of the present application, the memory of the computer further includes a global queue, where the global queue is used to store address information of at least one memory block that is not allocated and is not stored in the address area. Correspondingly, the identification unit is further configured to identify the global queue when address information of the memory block is not recorded in the affinity sub-area of the target processor. The obtaining unit is specifically configured to obtain address information of one memory block from the first sub-area when the address information of the memory block is not recorded in the global queue.

Optionally, in another possible implementation manner of the present application, the memory of the computer further includes a last idle variable, where the last idle variable is used to indicate a sub-region that is unoccupied and has a shortest time difference from a time point of the unoccupied sub-region to a current time point. Correspondingly, the memory management device in the embodiment of the present application further includes a determining unit, where the determining unit is configured to determine whether the first sub-region is currently occupied when the sub-region indicated by the most recent idle variable is the first sub-region. The obtaining unit is specifically configured to obtain address information of one memory block from the first sub-area when the determining unit determines that the first sub-area is not occupied currently.

Optionally, in another possible implementation manner of the present application, the determining unit is further configured to determine whether the second sub-region is currently occupied when the sub-region indicated by the latest idle variable is the second sub-region, where the second sub-region is a different region from the first sub-region. The memory management device in the embodiment of the application further includes a traversing unit, where the traversing unit is configured to sequentially traverse the N sub-regions from a third sub-region when the determining unit determines that the second sub-region is currently occupied, where the third sub-region is a sub-region that is arranged behind the second sub-region and adjacent to the second sub-region in the N sub-regions. The obtaining unit is specifically configured to determine that the first sub-region is not occupied in the traversal process, record address information of the memory block in the first sub-region, and obtain address information of one memory block from the first sub-region.

Optionally, in another possible implementation manner of the present application, the address area in the memory of the computer further includes N occupation identifiers, each sub-area has one occupation identifier, and the occupation identifier is used to indicate whether the corresponding sub-area is occupied. The determining unit is further configured to determine, after the identifying unit identifies the affinity sub-region of the target processor, whether the affinity sub-region of the target processor is occupied according to an occupation identifier of the affinity sub-region of the target processor, and determine, when the affinity sub-region of the target processor is not occupied, whether address information of the memory block is recorded in the affinity sub-region of the target processor.

In a third aspect, a computer is provided, where the computer includes the memory management device, the at least one processor, and a storage medium described in the second aspect and any possible implementation manner of the second aspect, where the memory management device, the at least one processor, and the storage medium are connected to each other, and the storage medium includes a memory block of the computer.

In a fourth aspect, there is also provided a computer-readable storage medium having instructions stored therein; when the method is executed on the memory management device according to the second aspect and any one of the possible implementations of the second aspect, the memory management device is caused to execute the memory management method according to the first aspect and any one of the possible implementations of the first aspect.

In a fifth aspect, there is also provided a computer program product containing instructions, which when run on the memory management device of the second aspect, causes the memory management device to execute the memory management method of the first aspect and any one of its possible implementations.

In the present application, the names of the memory management devices do not limit the devices or the functional modules themselves, and in actual implementation, the devices or the functional modules may appear by other names. Insofar as the functions of the respective devices or functional modules are similar to those of the present application, they fall within the scope of the claims of the present application and their equivalents.

For a detailed description of the second, third, fourth, fifth and their various implementations in this application, reference may be made to the detailed description of the first aspect and its various implementations; moreover, the beneficial effects of the second aspect, the third aspect, the fourth aspect, the fifth aspect and various implementation manners thereof may refer to the beneficial effect analysis of the first aspect and various implementation manners thereof, and are not described herein again.

In a sixth aspect, a memory management method is provided for a computer including a plurality of processors, the memory of the computer comprises a data area and an address area, wherein the data area comprises M memory blocks (M >1), the address area comprises N (N >1, N is less than or equal to M) sub-areas, each sub-area is used for storing the address information of at least one memory block, and the address information stored in different sub-regions is different, each processor is allocated with an affinity sub-region in N sub-regions, the memory block identified by the address information stored in the affinity sub-region is preferentially allocated to the processor corresponding to the affinity sub-region, specifically, after receiving a memory release request which is sent by a target processor and used for requesting to write address information of a memory block to be released into a memory of a server, responding to the memory release request and identifying an affinity sub-region of the target processor; when the remaining storage space of the affinity sub-area of the target processor is zero, writing the address information of the memory block to be released into a first sub-area, wherein the first sub-area is one of the N sub-areas except the affinity sub-area of the target processor.

Similar to the process of requesting allocation of a memory block described in the first aspect, when address information of a memory block to be released needs to be written into a memory of a server, it is preferentially determined whether a remaining storage space of an affinity sub-region of a target processor is zero. When the remaining storage space of the affinity sub-region of the target processor is zero, the address information of the memory block to be released may be written into a sub-region (e.g., the first sub-region) other than the affinity sub-region of the target processor, so as to improve the utilization rate of the memory.

Optionally, in a possible implementation manner of the present application, the address area further includes N occupation identifiers, each sub-area has an occupation identifier, and the occupation identifier is used to indicate whether the corresponding sub-area is occupied. Thus, after the affinity sub-region of the target processor is identified according to the target processor, whether the affinity sub-region of the target processor is occupied or not can be determined according to the occupation identifier of the affinity sub-region of the target processor; when the affinity sub-region of the target processor is unoccupied, it is determined whether the remaining memory space of the affinity sub-region of the target processor is zero.

Optionally, in another possible implementation manner of the present application, the memory of the computer further includes a last idle variable, where the last idle variable is used to indicate a sub-region that is unoccupied and has a shortest time difference from a time point of the unoccupied sub-region to a current time point. The method for writing the address information of the memory block to be released into the first subregion includes: and when the latest idle sub-region indicated by the latest idle variable is the first sub-region and the first sub-region is not occupied currently, writing the address information of the memory block to be released into the first sub-region.

Optionally, in another possible implementation manner of the present application, when the last idle variable indicates that the last idle sub-region is the second sub-region and the second sub-region is currently occupied, sequentially traversing N sub-regions from a third sub-region, where the third sub-region is a sub-region that is arranged behind the second sub-region and adjacent to the second sub-region in the N sub-regions; and when the first sub-area is determined to be unoccupied and the residual storage space of the first sub-area is not zero in the traversal process, writing the address information of the memory block to be released into the first sub-area.

Optionally, in another possible implementation manner of the present application, when the remaining storage space of the affinity sub-region of the target processor is zero, sequentially traversing N-1 sub-regions from any sub-region except the affinity sub-region of the target processor, and when it is determined that the first sub-region is not occupied during the traversal process and the remaining storage space of the first sub-region is not zero, writing the address information of the memory block to be released into the first sub-region.

When the remaining memory space of the affinity sub-area of the target processor is zero, the address information of the memory block to be released may be written into the first sub-area in any one of the manners described above.

A seventh aspect provides a memory management device, including a receiving unit, an identifying unit, and a writing unit. The receiving unit is configured to receive a memory release request sent by a target processor, where the memory release request is used to request that address information of a memory block to be released is written into a memory of a server, the computer includes multiple processors, the target processor is one of the multiple processors, the memory includes a data region and an address region, the data region includes M memory blocks, the address region includes N sub-regions, each sub-region is used to store address information of at least one memory block, and address information stored in different sub-regions is different, each processor is allocated an affinity sub-region in the N sub-regions, and a memory block identified by address information stored in the affinity sub-region is preferentially allocated to a processor corresponding to the affinity sub-region, where M >1, N >1, and M > N. The identifying unit is configured to identify the affinity sub-region of the target processor in response to the memory release request received by the receiving unit. The writing unit is configured to, when the remaining storage space of the affinity sub-area of the target processor identified by the identifying unit is zero, write the address information of the memory block to be released into a first sub-area, where the first sub-area is one of the N sub-areas except for the affinity sub-area of the target processor.

Optionally, in a possible implementation manner of the present application, the address area further includes N occupation identifiers, each sub-area has an occupation identifier, and the occupation identifier is used to indicate whether the corresponding sub-area is occupied. Correspondingly, the memory management device provided in this embodiment of the application further includes a determining unit, where the determining unit is configured to determine, after the identifying unit identifies the affinity sub-region of the target processor according to the target processor, whether the affinity sub-region of the target processor is occupied according to the occupation identifier of the affinity sub-region of the target processor, and determine, when the affinity sub-region of the target processor is not occupied, whether a remaining storage space of the affinity sub-region of the target processor is zero.

Optionally, in another possible implementation manner of the present application, the memory of the computer further includes a last idle variable, where the last idle variable is used to indicate a sub-region that is unoccupied and has a shortest time difference from a time point of the unoccupied sub-region to a current time point. In this way, the write unit is specifically configured to write the address information of the memory block to be released into the first sub-region when the last idle sub-region indicated by the last idle variable is the first sub-region and the first sub-region is not occupied currently.

Optionally, in another possible implementation manner of the present application, the memory management device provided in the embodiment of the present application further includes a traversal unit, where the traversal unit is configured to, when the recent idle variable indicates that the recent idle sub-region is the second sub-region and the second sub-region is currently occupied, sequentially traverse N sub-regions from a third sub-region, where the third sub-region is a sub-region that is arranged behind the second sub-region and adjacent to the second sub-region in the N sub-regions. The writing unit is specifically configured to write the address information of the memory block to be released into the first sub-region when it is determined that the first sub-region is not occupied and the remaining storage space of the first sub-region is not zero in the traversal process.

Optionally, in another possible implementation manner of the present application, the traversal unit may be further configured to sequentially traverse N-1 sub-regions from any sub-region except the affinity sub-region of the target processor when the remaining memory space of the affinity sub-region of the target processor is zero. Correspondingly, the writing unit is specifically configured to write the address information of the memory block to be released into the first sub-region when it is determined that the first sub-region is not occupied during the traversal process and the remaining storage space of the first sub-region is not zero.

In an eighth aspect, a computer is provided, where the computer includes the memory management device, the at least one processor, and a storage medium described in the seventh aspect and any possible implementation manner of the seventh aspect, where the memory management device, the at least one processor, and the storage medium are connected to each other, and the storage medium includes a memory block of the computer.

In a ninth aspect, there is also provided a computer-readable storage medium having instructions stored therein; when the method is executed on the memory management device according to the seventh aspect and any one of the possible implementations of the seventh aspect, the memory management device is caused to execute the memory management method according to the sixth aspect and any one of the possible implementations of the sixth aspect.

In a tenth aspect, there is further provided a computer program product containing instructions, which when run on the memory management device of the seventh aspect, causes the memory management device to execute the memory management method of the sixth aspect and any possible implementation manner thereof.

For a detailed description of the seventh aspect, the eighth aspect, the ninth aspect, the tenth aspect, and various implementations thereof in the present application, reference may be made to the detailed description of the sixth aspect and various implementations thereof; moreover, for the beneficial effects of the seventh aspect, the eighth aspect, the ninth aspect, the tenth aspect and various implementation manners thereof, reference may be made to beneficial effect analysis in the sixth aspect and various implementation manners thereof, and details are not repeated here.

These and other aspects of the present application will be more readily apparent from the following description.

Drawings

Fig. 1 is a schematic structural diagram of a conventional fixed-length memory pool;

FIG. 2 is a schematic diagram of a hardware structure of a computer according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a logical structure of a computer according to an embodiment of the present disclosure;

fig. 4 is a first flowchart illustrating a memory management method according to an embodiment of the present application;

fig. 5 is a second flowchart illustrating a memory management method according to an embodiment of the present application;

fig. 6 is a third schematic flow chart illustrating a memory management method according to an embodiment of the present application;

fig. 7 is a first schematic structural diagram of a memory management device according to an embodiment of the present application;

fig. 8 is a second schematic structural diagram of a memory management device according to an embodiment of the present application.

Detailed Description

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and the above-described drawings are used for distinguishing between different objects and not for limiting a particular order.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Generally, a memory of a computer includes a storage medium and a memory management device. The storage space provided by the storage medium is divided into a plurality of memory pools, and the storage space of each memory pool is divided into a data area for storing a plurality of memory blocks, an address area comprising a plurality of sub-areas and an area for storing a global queue. Each sub-region is used for storing address information of at least one memory block, and the address information stored in different sub-regions is different. The global queue is used for storing address information of at least one memory block which is not allocated and is not stored in the address area. The structure of the global queue may be a stack structure, and address information of the memory blocks stored by the stack structure follows a rule of "last-in first-out". The memory management device is used for managing the allocation and the release of each memory block in the storage medium. The memory management method provided by the embodiment of the application is executed by the memory management device.

Fixed-length memory pool management is a common type of memory management. As shown in fig. 1, for a computer including N processors, an existing fixed-length memory pool (e.g., a memory pool one) includes M memory blocks (e.g., a memory block 1, a memory block 2, … …, a memory block M) with the same length, an address area formed by N sub-areas, and a global queue, where each processor is allocated with a dedicated sub-area in the N sub-areas, and a memory block identified by address information stored in the dedicated sub-area can only be allocated to a processor corresponding to the dedicated sub-area. In addition, the fixed-length memory pool also comprises a memory pool control head and M memory block control heads, and each memory block is provided with a memory block control head. The memory pool control head records the number of memory blocks included in the fixed-length memory pool, the length of each memory block, and information such as an identifier (Identity, ID) of the fixed-length memory pool; for a memory block control head of a certain memory block, the memory block control head records information such as the latest allocation release time of the memory block, and an identifier of a service calling the memory block. The address information of the memory blocks stored in the global queue may be stored in an array form, and in order to ensure the security of the memory blocks in the fixed-length memory pool, the global queue further has a lock interface. In the memory management process, the memory management device mainly realizes the allocation and release of the memory according to the memory pool control head, the memory block control head, the global queue and the address area.

Currently, when a memory management device needs to allocate a memory for a service Y1 running on a processor a, the memory management device may determine whether the memory allocation for the service Y1 is successful by combining the determination results of whether a dedicated sub-area of the processor a is empty and whether a global queue is empty. In the case where the dedicated sub-region of processor a is empty and the global queue is empty, the dedicated sub-regions of other processors may not be empty, but since each sub-region is a dedicated sub-region of a certain processor, even if the dedicated sub-regions of other processors are not empty, the allocation of memory to traffic Y1 may no longer be continued, resulting in wasted memory.

In view of the above problem of memory waste, an embodiment of the present application provides a memory management method, where each sub-region in a memory of a computer can be occupied by multiple processors in the computer, each processor is allocated with an affinity sub-region, and when a memory needs to be allocated to a target processor in the multiple processors, a memory block is preferentially allocated to the target processor according to address information stored in the affinity sub-region of the target processor. When the affinity sub-region of the target processor does not record the address information of the memory block, the address information of one memory block may still be acquired from a sub-region (e.g., the first sub-region) other than the affinity sub-region of the target processor, and the memory block identified by the acquired address information of the memory block is allocated to the target processor, which effectively reduces the waste of memory.

As can be seen from the above description, the memory management method provided in the embodiment of the present application can be applied to a computer, as shown in fig. 2, where the computer includes a memory management device 01 and a storage medium 02 connected to the memory management device 01. The storage medium 02 includes a memory pool of the computer (that is, the storage medium 02 includes a plurality of memory blocks in the computer), and can store data, software programs, modules, and the like. The storage medium 02 may be, but is not limited to, a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, the computer may further include a processor 03, where the processor 03 includes N processor cores (core 1, … …, core k, … …, core N), such as at least one Central Processing Unit (CPU), and each CPU may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The plurality of processor cores may occupy the memory blocks stored in the storage medium 02 at the same time or at the same time. For convenience of description, the memory management device 01, the storage medium 02 and the processor 03 are described in the following by taking an example in which one processor includes one processor core, and thus, the memory management device 01 may be specifically used for managing allocation and release of memory blocks in the storage medium 02 and reducing the load of the processor 03. The memory management device 01, the storage medium 02, and the processor 03 may be disposed independently of each other, or at least two of them may be integrated in one device, which is not specifically limited in this embodiment of the present application.

The structure of the memory pool of the computer shown in fig. 2 is similar to that of the memory pool shown in fig. 1, and includes a memory pool control head, M memory block control heads, a global queue, N sub-regions, and M memory blocks. Differently, each sub-region in the memory pool in the embodiment of the present application includes an occupation identifier (in fig. 2, an occupation identifier is denoted by F, the following content of the present application refers to an occupation identifier "1" as indicating that the sub-region is occupied, and an occupation identifier "0" as indicating that the sub-region is not occupied, where the occupation identifier may be denoted by a 32-bit (bit) atomic variable) and address information of at least one memory block, and each processor is allocated with one affinity sub-region in N sub-regions. The memory block identified by the address information stored in the affinity sub-region is preferentially allocated to the processor corresponding to the affinity sub-region. For example, the computer includes a processor 1 and a processor 2, where the affinity sub-region of the processor 1 is sub-region 1, and the affinity sub-region of the processor 2 is sub-region 2, the memory block identified by the address information held by sub-region 1 is preferentially allocated to the processor 1, and the memory block identified by the address information held by sub-region 2 is preferentially allocated to the processor 2.

The computer may further include a plurality of service modules 04, each service module 04 may be run on the at least one processor, and the running of each service module 04 may cause the allocation and release process of the memory block. Specifically, as shown in fig. 3, the computer includes a plurality of service modules 04, each service module 04 operates in at least one processor, any service module 04 triggers the processor operated by the service module to send a memory allocation request (or a memory release request) in an operation process, and correspondingly, the memory management device 01 allocates a memory (or releases a corresponding memory) to the processor according to the memory allocation matching request (or the memory release request).

For convenience of understanding, the embodiment of the present application is described by taking an example that the first service module runs on the target processor, and requests to allocate/release the memory during the running process. Since the memory management device allocates and releases the memory blocks in each memory pool in the same process, the memory management device allocates and releases the memory blocks in the first memory pool in the embodiment of the present application as an example. As shown in fig. 4, a memory management method provided in an embodiment of the present application includes:

s400, the target processor sends a memory allocation request carrying the identifier of the first memory pool to the memory management device, and the memory allocation request is used for requesting to allocate the memory blocks in the first memory pool for the target processor.

The computer includes a plurality of processors, and the target processor is one of the plurality of processors. The memory of the computer includes a plurality of memory pools, where the first memory pool may be the first memory pool shown in fig. 2 or the second memory pool.

Referring to fig. 2, the first memory pool includes a memory pool control header, a memory block control header of each memory block, a global queue, N sub-regions, and M memory blocks with the same length. The memory pool control head may record the number M of memory blocks included in the memory pool, the length L of each memory block, the ID of the memory pool, and the like, and each memory block control head records information such as the latest allocation release time of a memory block corresponding to the memory block control head, an identifier for calling a service of the memory block, and the like, each sub-region in the N sub-regions may be occupied by the N processors, and each processor in the N processors is allocated with an affinity sub-region in the N sub-regions. For each processor, the memory block identified by the address information held by the affinity subarea of the processor is preferentially allocated to the processor, wherein M is greater than 1, N is greater than 1, and M is greater than or equal to N. Wherein the affinity region of each processor is predetermined by the system.

For example, as shown in fig. 2, sub-region 1 is an affinity sub-region of processor 1, sub-region N is an affinity sub-region of processor N, a memory block identified by address information held by sub-region 1 is preferentially allocated to processor 1, and a memory block identified by address information held by sub-region 2 is preferentially allocated to processor 2. Of course, the memory block identified by the address information stored in the sub-region 1 may also be allocated to a processor other than the processor 1, and similarly, the memory block identified by the address information stored in the sub-region N may also be allocated to a processor other than the processor N.

It is easily understood that, if the memory of the computer only includes one memory pool, the memory allocation request in the embodiment of the present application may not carry the identifier of the memory pool.

S401, responding to the memory allocation request, and identifying the affinity sub-region of the target processor in the first memory pool by the memory management device according to the target processor.

The memory pool control header in this embodiment of the present application further includes a first variable, where the first variable is used to record an identifier of an affinity sub-region of each processor, and the memory management device may directly obtain the identifier of the affinity sub-region of a currently running processor (i.e., a target processor) by reading the first variable. It should be noted that, when initializing the first variable, each processor in the computer needs to run, so that the memory management device can obtain the affinity region of any processor.

For example, the first variable is cache _ id, and with reference to the above example, if the currently running processor is 1, the cache _ id is 1, and the memory management device may determine that the affinity sub-region of the processor 1 is the sub-region 1 according to the cache _ id being 1.

Specifically, the memory management device reads a first variable from a memory pool control head of the first memory pool, and determines an affinity region of the target processor according to the target processor and the first variable.

S402, the memory management device determines whether the affinity sub-region of the target processor identified in the S401 is occupied.

Since each sub-region in the embodiment of the present application can be occupied by any processor, after acquiring the affinity sub-region of the target processor, the memory management device needs to determine whether the affinity sub-region of the target processor is occupied.

As can be seen from fig. 2, each sub-region in the embodiment of the present application includes an occupation identifier used to indicate whether the sub-region is occupied and address information of at least one memory block, so that after the memory management device identifies an affinity sub-region of a target processor, it can determine whether the affinity sub-region of the target processor is occupied according to the occupation identifier included in the affinity sub-region of the target processor.

Specifically, if the occupation flag of the affinity sub-region of the target processor is "1", which indicates that the affinity sub-region of the target processor is occupied, the memory management device performs S403. If the occupation flag of the affinity sub-region of the target processor is "0", which indicates that the affinity sub-region of the target processor is not occupied, the memory management device executes S407.

S403, the memory management device reads the latest idle variable and identifies the sub-area indicated by the latest idle variable.

Optionally, the memory pool control header in this embodiment of the present application may further include a last idle variable, where the last idle variable is used to indicate a sub-region that is unoccupied and has a shortest time difference from a time point of the unoccupied sub-region to a current time point.

Each processor in the computer can occupy a certain idle sub-area at any time, and can also release the occupation of a certain sub-area at any time, so that the value of the latest idle variable is changed.

It should be noted that, if a certain sub-region (taking the sub-region 3 as an example) is unoccupied, the value of the most recent idle variable is the identifier of the sub-region 3, and there may be no other sub-region unoccupied within a period of time after the sub-region 3 is unoccupied, and the value of the most recent idle variable remains unchanged. Even if sub-region 3 is occupied by a processor during this time, the value of the most recent idle variable is still the identity of sub-region 3.

S404, the memory management device determines whether the sub-region indicated by the latest idle variable is occupied currently.

As can be seen from the above description, the sub-region indicated by the most recent idle variable may be occupied, and therefore, after the memory management device identifies the sub-region indicated by the most recent idle variable, it needs to determine whether the sub-region is currently occupied.

The method for determining whether the sub-region indicated by the most recent idle variable is currently occupied by the memory management device may refer to the method for determining whether the affinity sub-region of the target processor is occupied by the memory management device, which is not described in detail herein.

S405a, if the sub-region indicated by the most recent idle variable is the second sub-region, when it is determined that the second sub-region is currently occupied, the memory management device sequentially traverses the N sub-regions from the third sub-region.

The third sub-region is a sub-region which is arranged behind the second sub-region and adjacent to the first sub-region among the N sub-regions. For example, referring to fig. 2, if the second subregion is subregion 1, then the third subregion is subregion 2.

Specifically, if the memory management device determines that the first sub-region is not occupied and address information of the memory block is recorded in the first sub-region in the traversal process, the memory management device terminates the traversal, occupies the first sub-region, acquires address information of one memory block from the first sub-region, and allocates the memory block identified by the acquired address information of the memory block to the target processor.

If the memory management device determines that all the sub-regions are unavailable (i.e., all the sub-regions are occupied or all the sub-regions do not record the address information of the memory block) in the traversal process, the memory allocation is terminated. Since all sub-regions are not available, the target processor cannot be allocated a block of memory.

Optionally, when it is determined that the second sub-region is currently occupied, the memory management device may further sequentially traverse the N sub-regions from any sub-region other than the affinity sub-region and the second sub-region of the target processor.

S405b, if the sub-region indicated by the most recent idle variable is the first sub-region, when it is determined that the first sub-region is not occupied and address information of the memory block is recorded in the first sub-region, the memory management device occupies the first sub-region, acquires address information of one memory block from the first sub-region, and allocates the memory block identified by the acquired address information of the memory block to the target processor.

In combination with the description of the last idle variable, the memory management device may occupy the first sub-region indicated by the last idle variable when the first sub-region is not occupied, and modify the occupancy flag of the first sub-region from "0" to "1".

After allocating the memory block identified by the acquired address information of the memory block to the target processor in S405a or S405b, the memory management apparatus executes S406.

S406, the memory management device releases the occupation of the first sub-area.

And after the memory management device allocates the memory block identified by the acquired address information of the memory block to the target processor, the memory management device releases occupation of the first sub-area. In addition, the memory management device also needs to modify the value of the second variable.

For example, if the first sub-region acquired by the memory management device in S403 is the sub-region 3, the value of the second variable is the identifier "3" of the sub-region 3, and if the sub-region 3 is not occupied, the memory management device occupies the sub-region 3, and if the sub-region 7 is idle at this time, the value of the second variable is modified from "3" to "7". When the memory management device allocates the memory block identified by the first address information in the sub-region 3 to the target processor, the memory management device releases the occupation of the sub-region 3, so that the value of the second variable is modified from "7" to "3".

S407, the memory management device occupies the affinity sub-region of the target processor, and determines whether the affinity sub-region of the target processor records the address information of the memory block.

S408, if the affinity sub-region of the target processor records address information of a memory block, the memory management device obtains address information of a memory block from the affinity sub-region of the target processor, and allocates the memory block identified by the obtained address information of the memory block to the target processor.

S409, if the affinity sub-region of the target processor does not record the address information of the memory block, the memory management device identifies the global queue and determines whether the global queue records the address information of the memory block.

Specifically, the memory management device acquires a lock of the global queue, reads the global queue after acquiring the lock of the global queue, and determines whether the global queue records address information of the memory block. If the global queue records address information of the memory block, the memory management device executes S410. If the global queue does not record the address information of the memory block, the memory management device executes S403.

S410, the memory management device reads a first preset number of address information from the global queue and writes the read address information into an affinity sub-area of the target processor.

S411, the memory management device obtains address information of one memory block from the affinity sub-area of the target processor after writing the address information, and allocates the memory block identified by the obtained address information of the memory block to the target processor.

It can be seen that even if the address information of the memory block is not recorded in the affinity sub-area of the target processor, the memory management device can still obtain the address information of one memory block from other sub-areas, such as the first sub-area, and allocate the memory block identified by the obtained address information to the target processor, thereby effectively reducing the waste of memory.

Further, before the memory management device allocates the memory to the target processor, the memory management device needs to create a first memory pool. With reference to fig. 4, as shown in fig. 5, before S400, the memory management method provided in the embodiment of the present application further includes S500-S503.

S500, the first processor sends a memory creating request carrying M and the size L of each memory block to the memory management device to request for creating the first memory pool.

The first processor and the target processor may be the same processor or different processors. If the first processor and the target processor are different devices, the first processor and the target processor may share the first memory pool.

S501, the memory management device calculates the lengths of the M memory blocks according to M and L.

S502, the memory management device calculates a first length according to the lengths of the M memory blocks, the length of the preset memory pool control header, the length of the preset N sub-regions, the length of the preset global queue, and the length of the preset M memory block control headers.

In the embodiment of the present application, the length of the memory pool control head, the length of each sub-region, the length of the global queue, and the length of the control head of each memory block are all preset.

For example, if the first length is represented by Total _ size, the length of the memory Pool control header is represented by Pool _ ctrl _ size, the length of each memory block control header is represented by Obj _ ctrl _ size, the length of the Global queue is represented by Global _ queue _ size, and the length of each sub-region is represented by Cpu _ cache _ size, the memory management device may calculate the first length by using the following formula:

Total_size＝Pool_ctrl_size+Obj_ctrl_size×M+Global_queue_size

+Cpu_cache_size×N+M×L

s503, the memory management device creates a first memory pool with a first length.

Specifically, the memory management device allocates a continuous memory with a first length from the memory of the computer, and uses the continuous memory as the first memory pool.

The memory management device divides a first memory Pool according to Pool _ ctrl _ size, Obj _ ctrl _ size × M, Global _ queue _ size, Cpu _ cache _ size × N, and M × L, and determines a memory Pool control header of the first memory Pool, a memory block control header of each of M memory blocks, a global queue, N sub-regions, and M memory blocks. After the memory management device divides the first memory pool, the memory management device initializes a memory pool control head of the first memory pool, a memory block control head of each memory block in the M memory blocks, the global queue, the N sub-regions, and the M memory blocks.

In the initialization process of the memory pool control head, mainly, the distribution information of the first memory pool, such as the number M of memory blocks included in the first memory pool, the length L of each memory block, the identifier of the first memory pool, and the like, is recorded in the memory pool control head. The initialization procedure of each memory block control head is to set each memory block control head to 0. The initialization process of the global queue is a process of dividing the continuous memory, the memory management device divides the continuous memory into M memory blocks with the length of L, and sequentially records the address information of all the memory blocks into the global queue, and in addition, the memory management device needs to initialize the lock of the global queue. In the process of creating the first memory pool, each sub-region is not occupied, so that the occupied identifier of each sub-region is set to "0", and each sub-region does not record the address information of the memory block.

Further, after the memory management device creates the first memory pool, the memory management device stores the address information of the memory pool control head of the first memory pool into the global memory pool control head array. Optionally, the address information of the first memory pool control header may be used as the identifier of the first memory pool in the array subscript of the global memory pool control header array.

As can be seen from the embodiment shown in fig. 4, the memory management device may allocate memory for the target processor. Correspondingly, when the target processor needs to release a certain memory, the memory management device may also release the memory for the target processor.

Specifically, as shown in fig. 6, the memory management method provided in the embodiment of the present application includes:

s600, the target processor sends a memory release request carrying the identifier of the first memory pool and the address information of the memory block to be released to the memory management device, and requests to write the address information of the memory block to be released into the first memory pool of the memory of the server.

As in the embodiment shown in fig. 4, the first memory pool in this embodiment may be the first memory pool or the second memory pool in fig. 2.

The structure of the first memory pool in this embodiment is the same as that in the embodiment shown in fig. 4, and details are not repeated here.

It is easily understood that, if the memory of the computer only includes one memory pool, the memory release request in the embodiment of the present application may not carry the identifier of the memory pool.

S601, responding to the memory allocation request, and identifying the affinity sub-region of the target processor in the first memory pool by the memory management device according to the target processor.

S601 may refer to S401 described above, and details are not repeated here.

S602, the memory management device determines whether the affinity sub-region of the target processor identified in S601 is occupied.

If the affinity sub-region of the target processor is not occupied, the memory management device executes S603; if the affinity sub-region of the target processor is already occupied, the memory management device proceeds to step S607.

S603, the memory management device occupies the affinity sub-region of the target processor and determines whether the remaining storage space of the affinity sub-region of the target processor is zero.

S604, if the remaining storage space of the affinity sub-area of the target processor is not zero, the memory management device writes the address information of the memory block to be released into the affinity sub-area of the target processor.

And S605, if the remaining storage space of the affinity sub-area of the target processor is zero, the memory management device writes the address information of the memory block to be released into the global queue.

Specifically, the memory management device acquires a lock of the global queue, and writes the address information of the memory block to be released into the global queue after acquiring the lock of the global queue. In this way, the memory block identified by the address information of the memory block to be released is released.

After S604 or S605, the memory management device deallocates the affinity sub-region of the target processor. The method for the memory management device to deallocate the affinity sub-region of the target processor in this embodiment may refer to the method for the memory management device to deallocate the affinity sub-region of the target processor in the embodiment shown in fig. 4, and details are not repeated here.

Optionally, after the memory management device writes the address information of the memory block to be released into the global queue, S606 may also be executed.

S606, the memory management device reads a second preset number of address information from the affinity subregion of the target processor and writes the read address information into the global queue.

Since the remaining storage space of the affinity sub-region of the target processor in S605 is zero, in order to ensure that the affinity sub-region of the target processor is available, the memory management device reads a second preset amount of address information from the affinity sub-region of the target processor, and writes the read address information into the global queue after acquiring the lock of the global queue, thereby further reducing the waste of memory.

S607, the memory management device reads the latest idle variable and identifies the sub-region indicated by the latest idle variable.

S607 can refer to S403 described above, and details are not repeated here.

S608, the memory management device determines whether the sub-region indicated by the most recent idle variable is currently occupied.

The last idle variable in this embodiment is the same as the last idle variable described in the embodiment shown in fig. 4, and detailed description thereof is omitted here.

And S609, if the sub-region indicated by the most recent idle variable is the first sub-region, when it is determined that the first sub-region is not occupied and the remaining storage space of the first sub-region is not zero, the memory management device writes the address information of the memory block to be released into the first sub-region.

S610, if the sub-region indicated by the most recent idle variable is the second sub-region, when it is determined that the second sub-region is currently occupied, the memory management device sequentially traverses the N sub-regions from the third sub-region.

The second sub-area is currently occupied, which indicates that the memory management device cannot write the address information of the memory block to be released into the second sub-area. In this case, the memory management device may sequentially traverse all the sub-regions from the third sub-region. The second sub-zone here is identical to the second sub-zone described in the embodiment shown in fig. 4, and the third sub-zone is identical to the third sub-zone described in the embodiment shown in fig. 4.

Specifically, if the memory management device determines that the first sub-region is not occupied and the remaining storage space of the first sub-region is not zero in the traversal process, the memory management device stops the traversal, and writes the address information of the memory block to be released into the first sub-region.

To sum up, the memory management device in the embodiment of the present application only obtains the lock of the global queue and accesses the global queue under the condition that the affinity sub-region of the target processor is not occupied and the remaining storage space of the affinity sub-region of the target processor is zero, so that time waste caused by lock acquisition is reduced, and the performance of memory release is improved. According to the memory management method provided by the embodiment of the application, even under the condition that the affinity sub-region of the target processor does not record the address information of the memory block or the affinity sub-region of the target processor is occupied, the memory management device can still realize the allocation and release of the memory through other sub-regions, so that the waste of the memory is reduced.

The embodiment of the present application provides a memory management device, which is configured to execute the steps executed by the memory management device in the above memory management method. The memory management device provided by the embodiment of the application may include modules corresponding to the corresponding steps.

In the embodiment of the present application, the memory management device may be divided into the functional modules according to the method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The division of the modules in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

Fig. 7 shows a schematic diagram of a possible structure of the memory management device according to the foregoing embodiment, in a case where each functional module is divided according to each function. As shown in fig. 7, the memory management apparatus 700 includes a receiving unit 70, an identifying unit 71, an obtaining unit 72, an allocating unit 73, a determining unit 74, and a traversing unit 75. The receiving unit 70 is used to support the memory management device 700 to execute the processes of S400, S500, and/or S600, etc. in the above embodiments, and/or other processes for the technologies described herein; the identification unit 71 is configured to support the memory management device 700 to perform the processes of S401, S403, S409, S601, and/or S607, etc. in the above embodiments, and/or other processes for the technologies described herein; the obtaining unit 72 is configured to support the memory management device 700 to execute S401, S403, S601, and/or S607 and the like in the foregoing embodiments, and/or other processes for the technology described herein; allocation unit 73 is used to support the memory management device 700 to perform operations S405b, S408, and/or S411, etc. in the above embodiments, and/or other processes for the techniques described herein; the determining unit 74 is configured to support the memory management device 700 to perform the processes of S402, S404, S409, S602, S603, and/or S608 in the foregoing embodiments, and/or other processes for the technologies described herein; traversal unit 76 is configured to support the memory management device 700 to perform S604, S605, S606, and/or S609, etc. in the above embodiments, and/or other processes for the techniques described herein. All relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again. Of course, the memory management device 700 provided in the embodiment of the present application includes, but is not limited to, the above modules, for example, the memory management device 700 may further include the writing unit 76, the sending unit 77, and the storing unit 78. The write unit is used for writing address information of the memory block to be released. The transmitting unit 77 is used for communication with other devices. The memory unit 78 may be used to store program codes and data for the memory management device.

It should be noted that all relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

For example, in the case of using an integrated unit, a schematic structural diagram of the memory management device provided in the embodiment of the present application is shown in fig. 8. In fig. 8, the memory management device includes: a processing module 80 and a communication module 81. The processing module 80 is used for controlling and managing the actions of the memory management device, for example, executing the steps executed by the above-mentioned identifying unit 71, obtaining unit 72, assigning unit 73, determining unit 74, traversing unit 75, and writing unit 76, and/or other processes for executing the techniques described herein. The communication module 81 is used to support the interaction between the memory management device and other devices, for example, to execute the steps executed by the receiving unit 70 and the sending unit 77. As shown in fig. 8, the memory management device may further include a storage module 82, where the storage module 82 is used to store program codes and data of the memory management device, for example, to store the contents stored in the storage unit 78.

Accordingly, an embodiment of the present application further provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the instructions are executed on a memory management device, the memory management device is enabled to execute each step executed by the memory management device in the method flow shown in the foregoing method embodiment.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any combination thereof. When implemented using a software program, may take the form of a computer program product, either entirely or partially. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical functional division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another device, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may be one physical unit or a plurality of physical units, that is, may be located in one place, or may be distributed in a plurality of different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partially contributed to by the prior art, or all or part of the technical solutions may be embodied in the form of a software product, where the software product is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory management method, comprising:

receiving a memory allocation request sent by a target processor, where the memory allocation request is used to request that a memory block in a memory of a computer is allocated to the target processor, the computer includes multiple processors, the target processor is one of the multiple processors, the memory includes a data region and an address region, the data region includes M memory blocks, the address region includes N sub-regions, each sub-region is used to store address information of at least one memory block, and the address information stored in different sub-regions is different, each processor is allocated with an affinity sub-region in the N sub-regions, and the memory block identified by the address information stored in the affinity sub-region is preferentially allocated to the processor corresponding to the affinity sub-region, where M >1, N >1, and M is greater than or equal to N;

responding to the memory allocation request, and identifying an affinity sub-region of the target processor according to the target processor;

the memory comprises a global queue, wherein the global queue is used for storing address information of at least one memory block which is not distributed and is not stored in the address area; when address information of a memory block is not recorded in an affinity subregion of the target processor, identifying the global queue;

when address information of a memory block is not recorded in the global queue, acquiring address information of one memory block from a first sub-region, where the first sub-region is one of the N sub-regions except for an affinity sub-region of the target processor; and allocating the memory block identified by the acquired address information of the memory block to the target processor.

2. The memory management method according to claim 1, wherein the memory further includes a last idle variable indicating a sub-region that is unoccupied and has a shortest time difference from a time of the unoccupied time to a current time;

the obtaining address information of one memory block from the first sub-area includes:

when the sub-region indicated by the latest idle variable is the first sub-region, determining whether the first sub-region is occupied currently;

when the first sub-area is not occupied currently, address information of one memory block is acquired from the first sub-area.

3. The memory management method according to claim 2, further comprising:

when the sub-region indicated by the latest idle variable is a second sub-region, determining whether the second sub-region is occupied currently, wherein the second sub-region is a different region from the first sub-region;

when the second sub-region is occupied currently, sequentially traversing the N sub-regions from a third sub-region, wherein the third sub-region is a sub-region which is arranged behind the second sub-region and adjacent to the second sub-region in the N sub-regions;

when it is determined that the first sub-region is not occupied in the traversal process and address information of a memory block is recorded in the first sub-region, address information of one memory block is acquired from the first sub-region.

4. The memory management method according to any one of claims 1 to 3, wherein the address region further includes N occupation identifiers, one occupation identifier is provided for each sub-region, and the occupation identifiers are used to indicate whether the corresponding sub-region is occupied or not;

after identifying the affinity sub-region of the target processor according to the target processor, the memory management method further includes:

determining whether the affinity sub-region of the target processor is occupied or not according to the occupation identifier of the affinity sub-region of the target processor;

when the affinity sub-area of the target processor is not occupied, determining whether address information of the memory block is recorded in the affinity sub-area of the target processor.

5. A memory management device, comprising:

a receiving unit, configured to receive a memory allocation request sent by a target processor, where the memory allocation request is used to request that a memory block in a memory of a computer be allocated to the target processor, the computer including a plurality of processors, the target processor being one of the plurality of processors, the memory comprises a data area and an address area, wherein the data area comprises M memory blocks, the address area comprises N sub-areas, each sub-area is used for storing the address information of at least one memory block, and the address information held by different sub-regions is different, each processor is allocated with an affinity sub-region in the N sub-regions, the memory block identified by the address information stored in the affinity sub-region is preferentially allocated to the processor corresponding to the affinity sub-region, wherein M >1, N >1, and M > N;

the identification unit is used for responding to the memory allocation request received by the receiving unit and identifying an affinity subregion of the target processor according to the target processor;

an obtaining unit, configured to obtain address information of one memory block from a first sub-region when the address information of the memory block is not recorded in the affinity sub-region of the target processor identified by the identifying unit, where the first sub-region is one of the N sub-regions except for the affinity sub-region of the target processor;

the allocation unit is configured to allocate the memory block identified by the address information of the memory block acquired by the acquisition unit to the target processor;

the memory further comprises a global queue, wherein the global queue is used for storing address information of at least one memory block which is not allocated and is not stored in the address area;

the identification unit is further configured to identify the global queue when address information of a memory block is not recorded in an affinity sub-area of the target processor;

the obtaining unit is specifically configured to obtain address information of one memory block from the first sub-area when address information of the memory block is not recorded in the global queue.

6. The memory management device according to claim 5, wherein the memory further includes a last idle variable indicating a sub-region that is unoccupied and has a shortest time difference from a time of the unoccupied time to a current time;

the memory management device further comprises a determination unit,

the determining unit is configured to determine whether the first sub-region is currently occupied or not when the sub-region indicated by the most recent idle variable is the first sub-region;

the obtaining unit is specifically configured to obtain address information of one memory block from the first sub-area when the determining unit determines that the first sub-area is not occupied currently.

7. The memory management device according to claim 6,

the determining unit is further configured to determine whether a second sub-region indicated by the most recent idle variable is currently occupied when the second sub-region is a second sub-region, where the second sub-region is a different region from the first sub-region;

the memory management device also comprises a traversal unit,

the traversing unit is configured to sequentially traverse the N sub-regions from a third sub-region when the determining unit determines that the second sub-region is currently occupied, where the third sub-region is a sub-region that is arranged behind the second sub-region and adjacent to the second sub-region in the N sub-regions;

the obtaining unit is specifically configured to determine that the first sub-region is not occupied in a traversal process, record address information of a memory block in the first sub-region, and obtain address information of one memory block from the first sub-region.

8. The memory management device according to any one of claims 5 to 7, wherein the address region further includes N occupation identifiers, one occupation identifier is provided for each sub-region, and the occupation identifiers are used to indicate whether the corresponding sub-region is occupied or not;

the determining unit is further configured to determine, after the identifying unit identifies the affinity sub-region of the target processor, whether the affinity sub-region of the target processor is occupied according to an occupation identifier of the affinity sub-region of the target processor, and determine, when the affinity sub-region of the target processor is not occupied, whether address information of a memory block is recorded in the affinity sub-region of the target processor.